-#define MIPS32_OP_BEQ 0x04
-#define MIPS32_OP_BNE 0x05
-#define MIPS32_OP_ADDI 0x08
-#define MIPS32_OP_AND 0x24
-#define MIPS32_OP_COP0 0x10
-#define MIPS32_OP_LUI 0x0F
-#define MIPS32_OP_LW 0x23
-#define MIPS32_OP_LBU 0x24
-#define MIPS32_OP_LHU 0x25
-#define MIPS32_OP_MFHI 0x10
-#define MIPS32_OP_MTHI 0x11
-#define MIPS32_OP_MFLO 0x12
-#define MIPS32_OP_MTLO 0x13
-#define MIPS32_OP_SB 0x28
-#define MIPS32_OP_SH 0x29
-#define MIPS32_OP_SW 0x2B
-#define MIPS32_OP_ORI 0x0D
-
-#define MIPS32_COP0_MF 0x00
-#define MIPS32_COP0_MT 0x04
-
-#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | ((rd) << 11)| ((shamt) << 6) | (funct))
-#define MIPS32_I_INST(opcode, rs, rt, immd) (((opcode) << 26) |((rs) << 21) | ((rt) << 16) | (immd))
-#define MIPS32_J_INST(opcode, addr) (((opcode) << 26) |(addr))
-
-#define MIPS32_NOP 0
-#define MIPS32_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
-#define MIPS32_AND(reg, off, val) MIPS32_R_INST(0, off, val, reg, 0, MIPS32_OP_AND)
-#define MIPS32_B(off) MIPS32_BEQ(0, 0, off)
-#define MIPS32_BEQ(src,tar,off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
-#define MIPS32_BNE(src,tar,off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
-#define MIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
-#define MIPS32_MTC0(gpr,cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
-#define MIPS32_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
-#define MIPS32_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
-#define MIPS32_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
-#define MIPS32_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
-#define MIPS32_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
-#define MIPS32_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
-#define MIPS32_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
-#define MIPS32_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
-#define MIPS32_ORI(src, tar, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
-#define MIPS32_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
-#define MIPS32_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
-#define MIPS32_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
+struct mips32_algorithm {
+ int common_magic;
+ enum mips32_isa_mode isa_mode;
+};
+
+#define MIPS32_OP_ADDU 0x21u
+#define MIPS32_OP_ADDIU 0x09u
+#define MIPS32_OP_ANDI 0x0Cu
+#define MIPS32_OP_BEQ 0x04u
+#define MIPS32_OP_BGTZ 0x07u
+#define MIPS32_OP_BNE 0x05u
+#define MIPS32_OP_ADDI 0x08u
+#define MIPS32_OP_AND 0x24u
+#define MIPS32_OP_CACHE 0x2Fu
+#define MIPS32_OP_COP0 0x10u
+#define MIPS32_OP_J 0x02u
+#define MIPS32_OP_JR 0x08u
+#define MIPS32_OP_LUI 0x0Fu
+#define MIPS32_OP_LW 0x23u
+#define MIPS32_OP_LB 0x20u
+#define MIPS32_OP_LBU 0x24u
+#define MIPS32_OP_LHU 0x25u
+#define MIPS32_OP_MFHI 0x10u
+#define MIPS32_OP_MTHI 0x11u
+#define MIPS32_OP_MFLO 0x12u
+#define MIPS32_OP_MTLO 0x13u
+#define MIPS32_OP_RDHWR 0x3Bu
+#define MIPS32_OP_SB 0x28u
+#define MIPS32_OP_SH 0x29u
+#define MIPS32_OP_SW 0x2Bu
+#define MIPS32_OP_ORI 0x0Du
+#define MIPS32_OP_XORI 0x0Eu
+#define MIPS32_OP_XOR 0x26u
+#define MIPS32_OP_SLTU 0x2Bu
+#define MIPS32_OP_SRL 0x03u
+#define MIPS32_OP_SYNCI 0x1Fu
+#define MIPS32_OP_SLL 0x00u
+#define MIPS32_OP_SLTI 0x0Au
+#define MIPS32_OP_MOVN 0x0Bu
+
+#define MIPS32_OP_REGIMM 0x01u
+#define MIPS32_OP_SDBBP 0x3Fu
+#define MIPS32_OP_SPECIAL 0x00u
+#define MIPS32_OP_SPECIAL2 0x07u
+#define MIPS32_OP_SPECIAL3 0x1Fu
+
+#define MIPS32_COP0_MF 0x00u
+#define MIPS32_COP0_MT 0x04u
+
+#define MIPS32_R_INST(opcode, rs, rt, rd, shamt, funct) \
+ (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | ((rd) << 11) | ((shamt) << 6) | (funct))
+#define MIPS32_I_INST(opcode, rs, rt, immd) \
+ (((opcode) << 26) | ((rs) << 21) | ((rt) << 16) | (immd))
+#define MIPS32_J_INST(opcode, addr) (((opcode) << 26) | (addr))
+
+#define MIPS32_ISA_NOP 0
+#define MIPS32_ISA_ADDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDI, src, tar, val)
+#define MIPS32_ISA_ADDIU(tar, src, val) MIPS32_I_INST(MIPS32_OP_ADDIU, src, tar, val)
+#define MIPS32_ISA_ADDU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_ADDU)
+#define MIPS32_ISA_AND(dst, src, tar) MIPS32_R_INST(0, src, tar, dst, 0, MIPS32_OP_AND)
+#define MIPS32_ISA_ANDI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ANDI, src, tar, val)
+
+#define MIPS32_ISA_B(off) MIPS32_ISA_BEQ(0, 0, off)
+#define MIPS32_ISA_BEQ(src, tar, off) MIPS32_I_INST(MIPS32_OP_BEQ, src, tar, off)
+#define MIPS32_ISA_BGTZ(reg, off) MIPS32_I_INST(MIPS32_OP_BGTZ, reg, 0, off)
+#define MIPS32_ISA_BNE(src, tar, off) MIPS32_I_INST(MIPS32_OP_BNE, src, tar, off)
+#define MIPS32_ISA_CACHE(op, off, base) MIPS32_I_INST(MIPS32_OP_CACHE, base, op, off)
+#define MIPS32_ISA_J(tar) MIPS32_J_INST(MIPS32_OP_J, (0x0FFFFFFFu & (tar)) >> 2)
+#define MIPS32_ISA_JR(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_JR)
+
+#define MIPS32_ISA_LB(reg, off, base) MIPS32_I_INST(MIPS32_OP_LB, base, reg, off)
+#define MIPS32_ISA_LBU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LBU, base, reg, off)
+#define MIPS32_ISA_LHU(reg, off, base) MIPS32_I_INST(MIPS32_OP_LHU, base, reg, off)
+#define MIPS32_ISA_LUI(reg, val) MIPS32_I_INST(MIPS32_OP_LUI, 0, reg, val)
+#define MIPS32_ISA_LW(reg, off, base) MIPS32_I_INST(MIPS32_OP_LW, base, reg, off)
+
+#define MIPS32_ISA_MFC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MF, gpr, cpr, 0, sel)
+#define MIPS32_ISA_MTC0(gpr, cpr, sel) MIPS32_R_INST(MIPS32_OP_COP0, MIPS32_COP0_MT, gpr, cpr, 0, sel)
+#define MIPS32_ISA_MFLO(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFLO)
+#define MIPS32_ISA_MFHI(reg) MIPS32_R_INST(0, 0, 0, reg, 0, MIPS32_OP_MFHI)
+#define MIPS32_ISA_MTLO(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTLO)
+#define MIPS32_ISA_MTHI(reg) MIPS32_R_INST(0, reg, 0, 0, 0, MIPS32_OP_MTHI)
+
+#define MIPS32_ISA_MOVN(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_MOVN)
+#define MIPS32_ISA_ORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_ORI, src, tar, val)
+#define MIPS32_ISA_RDHWR(tar, dst) MIPS32_R_INST(MIPS32_OP_SPECIAL3, 0, tar, dst, 0, MIPS32_OP_RDHWR)
+#define MIPS32_ISA_SB(reg, off, base) MIPS32_I_INST(MIPS32_OP_SB, base, reg, off)
+#define MIPS32_ISA_SH(reg, off, base) MIPS32_I_INST(MIPS32_OP_SH, base, reg, off)
+#define MIPS32_ISA_SW(reg, off, base) MIPS32_I_INST(MIPS32_OP_SW, base, reg, off)
+
+#define MIPS32_ISA_SLL(dst, src, sa) MIPS32_R_INST(MIPS32_OP_SPECIAL, 0, src, dst, sa, MIPS32_OP_SLL)
+#define MIPS32_ISA_SLTI(tar, src, val) MIPS32_I_INST(MIPS32_OP_SLTI, src, tar, val)
+#define MIPS32_ISA_SLTU(dst, src, tar) MIPS32_R_INST(MIPS32_OP_SPECIAL, src, tar, dst, 0, MIPS32_OP_SLTU)
+#define MIPS32_ISA_SRL(reg, src, off) MIPS32_R_INST(0, 0, src, reg, off, MIPS32_OP_SRL)
+#define MIPS32_ISA_SYNC 0xFu
+#define MIPS32_ISA_SYNCI(off, base) MIPS32_I_INST(MIPS32_OP_REGIMM, base, MIPS32_OP_SYNCI, off)
+
+#define MIPS32_ISA_XOR(reg, val1, val2) MIPS32_R_INST(0, val1, val2, reg, 0, MIPS32_OP_XOR)
+#define MIPS32_ISA_XORI(tar, src, val) MIPS32_I_INST(MIPS32_OP_XORI, src, tar, val)
+
+#define MIPS32_ISA_SYNCI_STEP 0x1 /* reg num od address step size to be used with synci instruction */
+
+/**
+ * Cache operations definitions
+ * Operation field is 5 bits long :
+ * 1) bits 1..0 hold cache type
+ * 2) bits 4..2 hold operation code
+ */
+#define MIPS32_CACHE_D_HIT_WRITEBACK ((0x1 << 0) | (0x6 << 2))
+#define MIPS32_CACHE_I_HIT_INVALIDATE ((0x0 << 0) | (0x4 << 2))
+
+/* ejtag specific instructions */
+#define MIPS32_ISA_DRET 0x4200001Fu
+/* MIPS32_ISA_J_INST(MIPS32_ISA_OP_SPECIAL2, MIPS32_ISA_OP_SDBBP) */
+#define MIPS32_ISA_SDBBP 0x7000003Fu
+#define MIPS16_ISA_SDBBP 0xE801u
+
+/*MICRO MIPS INSTRUCTIONS, see doc MD00582 */
+#define POOL32A 0X00u
+#define POOL32AXf 0x3Cu
+#define POOL32B 0x08u
+#define POOL32I 0x10u
+#define MMIPS32_OP_ADDI 0x04u
+#define MMIPS32_OP_ADDIU 0x0Cu
+#define MMIPS32_OP_ADDU 0x150u
+#define MMIPS32_OP_AND 0x250u
+#define MMIPS32_OP_ANDI 0x34u
+#define MMIPS32_OP_BEQ 0x25u
+#define MMIPS32_OP_BGTZ 0x06u
+#define MMIPS32_OP_BNE 0x2Du
+#define MMIPS32_OP_CACHE 0x06u
+#define MMIPS32_OP_J 0x35u
+#define MMIPS32_OP_JALR 0x03Cu
+#define MMIPS32_OP_LB 0x07u
+#define MMIPS32_OP_LBU 0x05u
+#define MMIPS32_OP_LHU 0x0Du
+#define MMIPS32_OP_LUI 0x0Du
+#define MMIPS32_OP_LW 0x3Fu
+#define MMIPS32_OP_MFC0 0x03u
+#define MMIPS32_OP_MTC0 0x0Bu
+#define MMIPS32_OP_MFLO 0x075u
+#define MMIPS32_OP_MFHI 0x035u
+#define MMIPS32_OP_MTLO 0x0F5u
+#define MMIPS32_OP_MTHI 0x0B5u
+#define MMIPS32_OP_MOVN 0x018u
+#define MMIPS32_OP_ORI 0x14u
+#define MMIPS32_OP_RDHWR 0x1ACu
+#define MMIPS32_OP_SB 0x06u
+#define MMIPS32_OP_SH 0x0Eu
+#define MMIPS32_OP_SW 0x3Eu
+#define MMIPS32_OP_SLTU 0x390u
+#define MMIPS32_OP_SLL 0x000u
+#define MMIPS32_OP_SLTI 0x24u
+#define MMIPS32_OP_SRL 0x040u
+#define MMIPS32_OP_SYNCI 0x10u
+#define MMIPS32_OP_XOR 0x310u
+#define MMIPS32_OP_XORI 0x1Cu
+
+#define MMIPS32_ADDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDI, tar, src, val)
+#define MMIPS32_ADDIU(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ADDIU, tar, src, val)
+#define MMIPS32_ADDU(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_ADDU)
+#define MMIPS32_AND(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_AND)
+#define MMIPS32_ANDI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ANDI, tar, src, val)
+
+#define MMIPS32_B(off) MMIPS32_BEQ(0, 0, off)
+#define MMIPS32_BEQ(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BEQ, tar, src, off)
+#define MMIPS32_BGTZ(reg, off) MIPS32_I_INST(POOL32I, MMIPS32_OP_BGTZ, reg, off)
+#define MMIPS32_BNE(src, tar, off) MIPS32_I_INST(MMIPS32_OP_BNE, tar, src, off)
+#define MMIPS32_CACHE(op, off, base) MIPS32_R_INST(POOL32B, op, base, MMIPS32_OP_CACHE << 1, 0, off)
+
+#define MMIPS32_J(tar) MIPS32_J_INST(MMIPS32_OP_J, ((0x07FFFFFFu & ((tar) >> 1))))
+#define MMIPS32_JR(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_JALR, POOL32AXf)
+#define MMIPS32_LB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LB, reg, base, off)
+#define MMIPS32_LBU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LBU, reg, base, off)
+#define MMIPS32_LHU(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LHU, reg, base, off)
+#define MMIPS32_LUI(reg, val) MIPS32_I_INST(POOL32I, MMIPS32_OP_LUI, reg, val)
+#define MMIPS32_LW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_LW, reg, base, off)
+
+#define MMIPS32_MFC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MFC0, POOL32AXf)
+#define MMIPS32_MFLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFLO, POOL32AXf)
+#define MMIPS32_MFHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MFHI, POOL32AXf)
+#define MMIPS32_MTC0(gpr, cpr, sel) MIPS32_R_INST(POOL32A, gpr, cpr, sel, MMIPS32_OP_MTC0, POOL32AXf)
+#define MMIPS32_MTLO(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTLO, POOL32AXf)
+#define MMIPS32_MTHI(reg) MIPS32_R_INST(POOL32A, 0, reg, 0, MMIPS32_OP_MTHI, POOL32AXf)
+
+#define MMIPS32_MOVN(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_MOVN)
+#define MMIPS32_NOP 0
+#define MMIPS32_ORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_ORI, tar, src, val)
+#define MMIPS32_RDHWR(tar, dst) MIPS32_R_INST(POOL32A, dst, tar, 0, MMIPS32_OP_RDHWR, POOL32AXf)
+#define MMIPS32_SB(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SB, reg, base, off)
+#define MMIPS32_SH(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SH, reg, base, off)
+#define MMIPS32_SW(reg, off, base) MIPS32_I_INST(MMIPS32_OP_SW, reg, base, off)
+
+#define MMIPS32_SRL(reg, src, off) MIPS32_R_INST(POOL32A, reg, src, off, 0, MMIPS32_OP_SRL)
+#define MMIPS32_SLTU(dst, src, tar) MIPS32_R_INST(POOL32A, tar, src, dst, 0, MMIPS32_OP_SLTU)
+#define MMIPS32_SYNCI(off, base) MIPS32_I_INST(POOL32I, MMIPS32_OP_SYNCI, base, off)
+#define MMIPS32_SLL(dst, src, sa) MIPS32_R_INST(POOL32A, dst, src, sa, 0, MMIPS32_OP_SLL)
+#define MMIPS32_SLTI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_SLTI, tar, src, val)
+#define MMIPS32_SYNC 0x00001A7Cu /* MIPS32_R_INST(POOL32A, 0, 0, 0, 0x1ADu, POOL32AXf) */
+
+#define MMIPS32_XOR(reg, val1, val2) MIPS32_R_INST(POOL32A, val1, val2, reg, 0, MMIPS32_OP_XOR)
+#define MMIPS32_XORI(tar, src, val) MIPS32_I_INST(MMIPS32_OP_XORI, tar, src, val)
+
+#define MMIPS32_SYNCI_STEP 0x1u /* reg num od address step size to be used with synci instruction */
+