-//----------------------------------------------------------------
-
-//----------------------------------------------------------------
-// Register Select Encoding (eonce_rev.1.0_0208081.pdf@14)
-//----------------------------------------------------------------
-#define DSP5680XX_ONCE_NOREG 0x00 /* No register selected */
-#define DSP5680XX_ONCE_OCR 0x01 /* OnCE Debug Control Register */
-#define DSP5680XX_ONCE_OCNTR 0x02 /* OnCE Breakpoint and Trace Counter */
-#define DSP5680XX_ONCE_OSR 0x03 /* EOnCE status register */
-#define DSP5680XX_ONCE_OBAR 0x04 /* OnCE Breakpoint Address Register */
-#define DSP5680XX_ONCE_OBASE 0x05 /* EOnCE Peripheral Base Address register */
-#define DSP5680XX_ONCE_OTXRXSR 0x06 /* EOnCE TXRX Status and Control Register (OTXRXSR) */
-#define DSP5680XX_ONCE_OTX 0x07 /* EOnCE Transmit register (OTX) */
-#define DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */
-#define DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */
-#define DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */
-#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */
-#define DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */
-#define DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */
-#define DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */
-#define DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */
-#define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */
-#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
-#define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */
-//----------------------------------------------------------------
-
-#define FLUSH_COUNT_READ_WRITE 8192 // This value works, higher values (and lower...) may work as well.
+ /**
+ * ----------------------------------------------------------------
+ */
+
+ /** ----------------------------------------------------------------
+ * Register Select Encoding (eonce_rev.1.0_0208081.pdf:14)
+ * ----------------------------------------------------------------
+ */
+#define DSP5680XX_ONCE_NOREG 0x00 /* No register selected */
+#define DSP5680XX_ONCE_OCR 0x01 /* OnCE Debug Control Register */
+#define DSP5680XX_ONCE_OCNTR 0x02 /* OnCE Breakpoint and Trace Counter */
+#define DSP5680XX_ONCE_OSR 0x03 /* EOnCE status register */
+#define DSP5680XX_ONCE_OBAR 0x04 /* OnCE Breakpoint Address Register */
+#define DSP5680XX_ONCE_OBASE 0x05 /* EOnCE Peripheral Base Address register */
+#define DSP5680XX_ONCE_OTXRXSR 0x06 /* EOnCE TXRX Status and Control Register (OTXRXSR) */
+#define DSP5680XX_ONCE_OTX 0x07 /* EOnCE Transmit register (OTX) */
+#define DSP5680XX_ONCE_OPDBR 0x08 /* EOnCE Program Data Bus Register (OPDBR) */
+#define DSP5680XX_ONCE_OTX1 0x09 /* EOnCE Upper Transmit register (OTX1) */
+#define DSP5680XX_ONCE_OPABFR 0x0A /* OnCE Program Address Register—Fetch cycle */
+#define DSP5680XX_ONCE_ORX 0x0B /* EOnCE Receive register (ORX) */
+#define DSP5680XX_ONCE_OCNTR_C 0x0C /* Clear OCNTR */
+#define DSP5680XX_ONCE_ORX1 0x0D /* EOnCE Upper Receive register (ORX1) */
+#define DSP5680XX_ONCE_OTBCR 0x0E /* EOnCE Trace Buffer Control Reg (OTBCR) */
+#define DSP5680XX_ONCE_OPABER 0x10 /* OnCE Program Address Register—Execute cycle */
+#define DSP5680XX_ONCE_OPFIFO 0x11 /* OnCE Program address FIFO */
+#define DSP5680XX_ONCE_OBAR1 0x12 /* EOnCE Breakpoint 1 Unit 0 Address Reg.(OBAR1) */
+#define DSP5680XX_ONCE_OPABDR 0x13 /* OnCE Program Address Register—Decode cycle (OPABDR) */
+ /**
+ * ----------------------------------------------------------------
+ */
+
+#define FLUSH_COUNT_READ_WRITE 8192 /* This value works, higher values (and lower...) may work as well. */