-#if 0
-/*
- * Cortex-A8 Core register functions
- */
-static int cortex_a8_load_core_reg_u32(struct target *target, int num,
- armv4_5_mode_t mode, uint32_t * value)
-{
- int retval;
- struct arm *armv4_5 = target_to_armv4_5(target);
-
- if ((num <= ARM_CPSR))
- {
- /* read a normal core register */
- retval = cortex_a8_dap_read_coreregister_u32(target, value, num);
-
- if (retval != ERROR_OK)
- {
- LOG_ERROR("JTAG failure %i", retval);
- return ERROR_JTAG_DEVICE_ERROR;
- }
- LOG_DEBUG("load from core reg %i value 0x%" PRIx32, num, *value);
- }
- else
- {
- return ERROR_INVALID_ARGUMENTS;
- }
-
- /* Register other than r0 - r14 uses r0 for access */
- if (num > 14)
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 0).dirty =
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 0).valid;
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 15).dirty =
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, 15).valid;
-
- return ERROR_OK;
-}
-
-static int cortex_a8_store_core_reg_u32(struct target *target, int num,
- armv4_5_mode_t mode, uint32_t value)
-{
- int retval;
-// uint32_t reg;
- struct arm *armv4_5 = target_to_armv4_5(target);
-
-#ifdef ARMV7_GDB_HACKS
- /* If the LR register is being modified, make sure it will put us
- * in "thumb" mode, or an INVSTATE exception will occur. This is a
- * hack to deal with the fact that gdb will sometimes "forge"
- * return addresses, and doesn't set the LSB correctly (i.e., when
- * printing expressions containing function calls, it sets LR=0.) */
-
- if (num == 14)
- value |= 0x01;
-#endif
-
- if ((num <= ARM_CPSR))
- {
- retval = cortex_a8_dap_write_coreregister_u32(target, value, num);
- if (retval != ERROR_OK)
- {
- LOG_ERROR("JTAG failure %i", retval);
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, num).dirty =
- ARMV4_5_CORE_REG_MODE(armv4_5->core_cache,
- armv4_5->core_mode, num).valid;
- return ERROR_JTAG_DEVICE_ERROR;
- }
- LOG_DEBUG("write core reg %i value 0x%" PRIx32, num, value);
- }
- else
- {
- return ERROR_INVALID_ARGUMENTS;
- }
-
- return ERROR_OK;
-}
-#endif
-
-
-static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
- int num, enum armv4_5_mode mode, uint32_t value);
-
-static int cortex_a8_read_core_reg(struct target *target, struct reg *r,
- int num, enum armv4_5_mode mode)
-{
- uint32_t value;
- int retval;
- struct arm *armv4_5 = target_to_armv4_5(target);
- struct reg *cpsr_r = NULL;
- uint32_t cpsr = 0;
- unsigned cookie = num;
-
- /* avoid some needless mode changes
- * FIXME move some of these to shared ARM code...
- */
- if (mode != armv4_5->core_mode) {
- if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
- && (mode == ARMV4_5_MODE_USR))
- mode = ARMV4_5_MODE_ANY;
- else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
- mode = ARMV4_5_MODE_ANY;
-
- if (mode != ARMV4_5_MODE_ANY) {
- cpsr_r = armv4_5->cpsr;
- cpsr = buf_get_u32(cpsr_r->value, 0, 32);
- cortex_a8_write_core_reg(target, cpsr_r,
- 16, ARMV4_5_MODE_ANY, mode);
- }
- }
-
- if (num == 16) {
- switch (mode) {
- case ARMV4_5_MODE_USR:
- case ARMV4_5_MODE_SYS:
- case ARMV4_5_MODE_ANY:
- /* CPSR */
- break;
- default:
- /* SPSR */
- cookie++;
- break;
- }
- }
-
- cortex_a8_dap_read_coreregister_u32(target, &value, cookie);
- retval = jtag_execute_queue();
- if (retval == ERROR_OK) {
- r->valid = 1;
- r->dirty = 0;
- buf_set_u32(r->value, 0, 32, value);
- }
-
- if (cpsr_r)
- cortex_a8_write_core_reg(target, cpsr_r,
- 16, ARMV4_5_MODE_ANY, cpsr);
- return retval;
-}
-
-static int cortex_a8_write_core_reg(struct target *target, struct reg *r,
- int num, enum armv4_5_mode mode, uint32_t value)
-{
- int retval;
- struct arm *armv4_5 = target_to_armv4_5(target);
- struct reg *cpsr_r = NULL;
- uint32_t cpsr = 0;
- unsigned cookie = num;
-
- /* avoid some needless mode changes
- * FIXME move some of these to shared ARM code...
- */
- if (mode != armv4_5->core_mode) {
- if ((armv4_5->core_mode == ARMV4_5_MODE_SYS)
- && (mode == ARMV4_5_MODE_USR))
- mode = ARMV4_5_MODE_ANY;
- else if ((mode != ARMV4_5_MODE_FIQ) && (num <= 12))
- mode = ARMV4_5_MODE_ANY;
-
- if (mode != ARMV4_5_MODE_ANY) {
- cpsr_r = armv4_5->cpsr;
- cpsr = buf_get_u32(cpsr_r->value, 0, 32);
- cortex_a8_write_core_reg(target, cpsr_r,
- 16, ARMV4_5_MODE_ANY, mode);
- }
- }
-
-
- if (num == 16) {
- switch (mode) {
- case ARMV4_5_MODE_USR:
- case ARMV4_5_MODE_SYS:
- case ARMV4_5_MODE_ANY:
- /* CPSR */
- break;
- default:
- /* SPSR */
- cookie++;
- break;
- }
- }
-
- cortex_a8_dap_write_coreregister_u32(target, value, cookie);
- if ((retval = jtag_execute_queue()) == ERROR_OK) {
- buf_set_u32(r->value, 0, 32, value);
- r->valid = 1;
- r->dirty = 0;
- }
-
- if (cpsr_r)
- cortex_a8_write_core_reg(target, cpsr_r,
- 16, ARMV4_5_MODE_ANY, cpsr);
- return retval;
-}
-
-