-/* Store register
- * Rd: register to store
- * Rn: base register
- */
-#define ARMV4_5_STR(Rd, Rn) (0xe5800000 | (Rd << 12) | (Rn << 16))
-
-/* Load register
- * Rd: register to load
- * Rn: base register
- */
-#define ARMV4_5_LDR(Rd, Rn) (0xe5900000 | (Rd << 12) | (Rn << 16))
-
-/* Move general purpose register to PSR
- * R=1: SPSR R=0: CPSR
- * Field: Field mask
- * 1: control field 2: extension field 4: status field 8: flags field
- * Rm: source register
- */
-#define ARMV4_5_MSR_GP(Rm, Field, R) (0xe120f000 | Rm | (Field << 16) | (R << 22))
-#define ARMV4_5_MSR_IM(Im, Rotate, Field, R) (0xe320f000 | (Im) | (Rotate << 8) | (Field << 16) | (R << 22))
-
-/* Load Register Halfword Immediate Post-Index
- * Rd: register to load
- * Rn: base register
- */
-#define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | (Rd << 12) | (Rn << 16))
-
-/* Load Register Byte Immediate Post-Index
- * Rd: register to load
- * Rn: base register
- */
-#define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | (Rd << 12) | (Rn << 16))
-
-/* Store register Halfword Immediate Post-Index
- * Rd: register to store
- * Rn: base register
- */
-#define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | (Rd << 12) | (Rn << 16))
-
-/* Store register Byte Immediate Post-Index
- * Rd: register to store
- * Rn: base register
- */
-#define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | (Rd << 12) | (Rn << 16))
-
-/* Branch (and Link)
- * Im: Branch target (left-shifted by 2 bits, added to PC)
- * L: 1: branch and link 0: branch only
- */
-#define ARMV4_5_B(Im, L) (0xea000000 | Im | (L << 24))
-
-/* Branch and exchange (ARM state)
- * Rm: register holding branch target address
- */
-#define ARMV4_5_BX(Rm) (0xe12fff10 | Rm)
-
-/* Move to ARM register from coprocessor
- * CP: Coprocessor number
- * op1: Coprocessor opcode
- * Rd: destination register
- * CRn: first coprocessor operand
- * CRm: second coprocessor operand
- * op2: Second coprocessor opcode
- */
-#define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | CRm | (op2 << 5) | (CP << 8) | (Rd << 12) | (CRn << 16) | (op1 << 21))
-
-/* Move to coprocessor from ARM register
- * CP: Coprocessor number
- * op1: Coprocessor opcode
- * Rd: destination register
- * CRn: first coprocessor operand
- * CRm: second coprocessor operand
- * op2: Second coprocessor opcode
- */
-#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | CRm | (op2 << 5) | (CP << 8) | (Rd << 12) | (CRn << 16) | (op1 << 21))
-
-
-/* Thumb mode instructions
- */
-
-/* Store register (Thumb mode)
- * Rd: source register
- * Rn: base register
- */
-#define ARMV4_5_T_STR(Rd, Rn) ((0x6000 | Rd | (Rn << 3)) | ((0x6000 | Rd | (Rn << 3)) << 16))
-
-/* Load register (Thumb state)
- * Rd: destination register
- * Rn: base register
- */
-#define ARMV4_5_T_LDR(Rd, Rn) ((0x6800 | (Rn << 3) | Rd) | ((0x6800 | (Rn << 3) | Rd) << 16))
-
-/* Move hi register (Thumb mode)
- * Rd: destination register
- * Rm: source register
- */
-#define ARMV4_5_T_MOV(Rd, Rm) ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) | ((0x4600 | (Rd & 0x7) | ((Rd & 0x8) << 4) | ((Rm & 0x7) << 3) | ((Rm & 0x8) << 3)) << 16))
-
-/* No operation (Thumb mode)
- */
-#define ARMV4_5_T_NOP (0x1c3f | (0x1c3f << 16))
-
-/* Move immediate to register (Thumb state)
- * Rd: destination register
- * Im: 8-bit immediate value
- */
-#define ARMV4_5_T_MOV_IM(Rd, Im) ((0x2000 | (Rd << 8) | Im) | ((0x2000 | (Rd << 8) | Im) << 16))
-
-/* Branch and Exchange
- * Rm: register containing branch target
- */
-#define ARMV4_5_T_BX(Rm) ((0x4700 | (Rm << 3)) | ((0x4700 | (Rm << 3)) << 16))