- reg_cache_t *core_cache;
- enum armv4_5_mode core_mode;
- enum armv4_5_state core_state;
- int (*full_context)(struct target_s *target);
- int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
- int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, u32 value);
+ struct reg_cache *core_cache;
+
+ /** Handle to the CPSR; valid in all core modes. */
+ struct reg *cpsr;
+
+ /** Handle to the SPSR; valid only in core modes with an SPSR. */
+ struct reg *spsr;
+
+ const int *map;
+
+ /**
+ * Indicates what registers are in the ARM state core register set.
+ * ARM_MODE_ANY indicates the standard set of 37 registers,
+ * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
+ * more registers are shadowed, for "Secure Monitor" mode.
+ */
+ enum arm_mode core_type;
+
+ enum arm_mode core_mode;
+ enum arm_state core_state;
+
+ /** Flag reporting unavailability of the BKPT instruction. */
+ bool is_armv4;
+
+ /** Flag reporting whether semihosting is active. */
+ bool is_semihosting;
+
+ /** Value to be returned by semihosting SYS_ERRNO request. */
+ int semihosting_errno;
+
+ /** Backpointer to the target. */
+ struct target *target;
+
+ /** Handle for the debug module, if one is present. */
+ struct arm_dpm *dpm;
+
+ /** Handle for the Embedded Trace Module, if one is present. */
+ struct etm_context *etm;
+
+ /* FIXME all these methods should take "struct arm *" not target */
+
+ int (*full_context)(struct target *target);
+ int (*read_core_reg)(struct target *target, struct reg *reg,
+ int num, enum arm_mode mode);
+ int (*write_core_reg)(struct target *target, struct reg *reg,
+ int num, enum arm_mode mode, uint32_t value);
+
+ /** Read coprocessor register. */
+ int (*mrc)(struct target *target, int cpnum,
+ uint32_t op1, uint32_t op2,
+ uint32_t CRn, uint32_t CRm,
+ uint32_t *value);
+
+ /* Write coprocessor register. */
+ int (*mcr)(struct target *target, int cpnum,
+ uint32_t op1, uint32_t op2,
+ uint32_t CRn, uint32_t CRm,
+ uint32_t value);
+