+/**
+ * Transport-neutral representation of queued DAP transactions, supporting
+ * both JTAG and SWD transports. All submitted transactions are logically
+ * queued, until the queue is executed by run(). Some implementations might
+ * execute transactions as soon as they're submitted, but no status is made
+ * available until run().
+ */
+struct dap_ops {
+ /** DP register read. */
+ int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
+ uint32_t *data);
+ /** DP register write. */
+ int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
+ uint32_t data);
+
+ /** AP register read. */
+ int (*queue_ap_read)(struct adiv5_dap *dap, unsigned reg,
+ uint32_t *data);
+ /** AP register write. */
+ int (*queue_ap_write)(struct adiv5_dap *dap, unsigned reg,
+ uint32_t data);
+
+ /** AP operation abort. */
+ int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
+
+ /** Executes all queued DAP operations. */
+ int (*run)(struct adiv5_dap *dap);
+};
+
+/*
+ * Access Port classes
+ */
+enum ap_class {
+ AP_CLASS_NONE = 0x00000, /* No class defined */
+ AP_CLASS_MEM_AP = 0x10000, /* MEM-AP */
+};
+
+/*
+ * Access Port types
+ */
+enum ap_type {
+ AP_TYPE_JTAG_AP = 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */
+ AP_TYPE_AHB_AP = 0x1, /* AHB Memory-AP */
+ AP_TYPE_APB_AP = 0x2, /* APB Memory-AP */
+ AP_TYPE_AXI_AP = 0x4, /* AXI Memory-AP */
+};
+
+/**
+ * Queue a DP register read.
+ * Note that not all DP registers are readable; also, that JTAG and SWD
+ * have slight differences in DP register support.
+ *
+ * @param dap The DAP used for reading.
+ * @param reg The two-bit number of the DP register being read.
+ * @param data Pointer saying where to store the register's value
+ * (in host endianness).
+ *
+ * @return ERROR_OK for success, else a fault code.
+ */
+static inline int dap_queue_dp_read(struct adiv5_dap *dap,
+ unsigned reg, uint32_t *data)
+{
+ assert(dap->ops != NULL);
+ return dap->ops->queue_dp_read(dap, reg, data);
+}
+
+/**
+ * Queue a DP register write.
+ * Note that not all DP registers are writable; also, that JTAG and SWD
+ * have slight differences in DP register support.
+ *
+ * @param dap The DAP used for writing.
+ * @param reg The two-bit number of the DP register being written.
+ * @param data Value being written (host endianness)
+ *
+ * @return ERROR_OK for success, else a fault code.
+ */
+static inline int dap_queue_dp_write(struct adiv5_dap *dap,
+ unsigned reg, uint32_t data)