+ /* true if packed transfers are supported by the MEM-AP */
+ bool packed_transfers;
+
+ /* true if unaligned memory access is not supported by the MEM-AP */
+ bool unaligned_access_bad;
+
+ /* true if tar_value is in sync with TAR register */
+ bool tar_valid;
+};
+
+
+/**
+ * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
+ * A DAP has two types of component: one Debug Port (DP), which is a
+ * transport agent; and at least one Access Port (AP), controlling
+ * resource access.
+ *
+ * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
+ * Accordingly, this interface is responsible for hiding the transport
+ * differences so upper layer code can largely ignore them.
+ *
+ * When the chip is implemented with JTAG-DP or SW-DP, the transport is
+ * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
+ * a choice made at board design time (by only using the SWD pins), or
+ * as part of setting up a debug session (if all the dual-role JTAG/SWD
+ * signals are available).
+ */
+struct adiv5_dap {
+ const struct dap_ops *ops;
+
+ /* dap transaction list for WAIT support */
+ struct list_head cmd_journal;
+
+ struct jtag_tap *tap;
+ /* Control config */
+ uint32_t dp_ctrl_stat;
+
+ struct adiv5_ap ap[256];
+
+ /* The current manually selected AP by the "dap apsel" command */
+ uint32_t apsel;
+
+ /**
+ * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
+ * indicates no cached value and forces rewrite of the register.
+ */
+ uint32_t select;
+
+ /* information about current pending SWjDP-AHBAP transaction */
+ uint8_t ack;
+
+ /**
+ * Holds the pointer to the destination word for the last queued read,
+ * for use with posted AP read sequence optimization.
+ */
+ uint32_t *last_read;
+
+ /* The TI TMS470 and TMS570 series processors use a BE-32 memory ordering
+ * despite lack of support in the ARMv7 architecture. Memory access through
+ * the AHB-AP has strange byte ordering these processors, and we need to
+ * swizzle appropriately. */
+ bool ti_be_32_quirks;
+
+ /**
+ * Signals that an attempt to reestablish communication afresh
+ * should be performed before the next access.
+ */
+ bool do_reconnect;
+
+ /** Flag saying whether to ignore the syspwrupack flag in DAP. Some devices
+ * do not set this bit until later in the bringup sequence */
+ bool ignore_syspwrupack;
+};
+
+/**
+ * Transport-neutral representation of queued DAP transactions, supporting
+ * both JTAG and SWD transports. All submitted transactions are logically
+ * queued, until the queue is executed by run(). Some implementations might
+ * execute transactions as soon as they're submitted, but no status is made
+ * available until run().
+ */
+struct dap_ops {
+ /** connect operation for SWD */
+ int (*connect)(struct adiv5_dap *dap);
+ /** DP register read. */
+ int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
+ uint32_t *data);
+ /** DP register write. */
+ int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
+ uint32_t data);
+
+ /** AP register read. */
+ int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
+ uint32_t *data);
+ /** AP register write. */
+ int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
+ uint32_t data);
+
+ /** AP operation abort. */
+ int (*queue_ap_abort)(struct adiv5_dap *dap, uint8_t *ack);
+
+ /** Executes all queued DAP operations. */
+ int (*run)(struct adiv5_dap *dap);
+
+ /** Executes all queued DAP operations but doesn't check
+ * sticky error conditions */
+ int (*sync)(struct adiv5_dap *dap);
+};
+
+/*
+ * Access Port classes
+ */
+enum ap_class {
+ AP_CLASS_NONE = 0x00000, /* No class defined */
+ AP_CLASS_MEM_AP = 0x10000, /* MEM-AP */
+};
+
+/*
+ * Access Port types
+ */
+enum ap_type {
+ AP_TYPE_JTAG_AP = 0x0, /* JTAG-AP - JTAG master for controlling other JTAG devices */
+ AP_TYPE_AHB_AP = 0x1, /* AHB Memory-AP */
+ AP_TYPE_APB_AP = 0x2, /* APB Memory-AP */
+ AP_TYPE_AXI_AP = 0x4, /* AXI Memory-AP */