tcl/target/ti_k3.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2 # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
   3 #
   4 # Texas Instruments K3 devices:
   5 # * AM654x: https://www.ti.com/lit/pdf/spruid7
   6 #  Has 4 ARMV8 Cores and 2 R5 Cores and an M3
   7 # * J721E: https://www.ti.com/lit/pdf/spruil1
   8 #  Has 2 ARMV8 Cores and 6 R5 Cores and an M3
   9 # * J7200: https://www.ti.com/lit/pdf/spruiu1
  10 #  Has 2 ARMV8 Cores and 4 R5 Cores and an M3
  11 # * AM642: https://www.ti.com/lit/pdf/spruim2
  12 #  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
  13 #
  14
  15 if { [info exists SOC] } {
  16         set _soc $SOC
  17 } else {
  18         set _soc am654
  19 }
  20
  21 # set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
  22 if { [info exists V8_SMP_DEBUG] } {
  23         set _v8_smp_debug $V8_SMP_DEBUG
  24 } else {
  25         set _v8_smp_debug 0
  26 }
  27
  28 # Common Definitions
  29
  30 # System Controller is the very first processor - all current SoCs have it.
  31 set CM3_CTIBASE         {0x3C016000}
  32
  33 # sysctrl power-ap unlock offsets
  34 set _sysctrl_ap_unlock_offsets {0xf0 0x44}
  35
  36 # All the ARMV8s are the next processors.
  37 #                  CL0,CORE0  CL0,CORE1  CL1,CORE0  CL1,CORE1
  38 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
  39 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
  40
  41 # And we add up the R5s
  42 #               (0)MCU 0   (1)MCU 1   (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
  43 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
  44 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
  45 set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
  46
  47 # Finally an General Purpose(GP) MCU
  48 set CM4_CTIBASE         {0x20001000}
  49
  50 # General Purpose MCU (M4) may be present on some very few SoCs
  51 set _gp_mcu_cores 0
  52 # General Purpose MCU power-ap unlock offsets
  53 set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
  54
  55 # Set configuration overrides for each SOC
  56 switch $_soc {
  57         am654 {
  58                 set _CHIPNAME am654
  59                 set _K3_DAP_TAPID 0x0bb5a02f
  60
  61                 # AM654 has 2 clusters of 2 A53 cores each.
  62                 set _armv8_cpu_name a53
  63                 set _armv8_cores 4
  64
  65                 # AM654 has 1 cluster of 2 R5s cores.
  66                 set _r5_cores 2
  67                 set R5_NAMES {mcu_r5.0 mcu_r5.1}
  68
  69                 # Sysctrl power-ap unlock offsets
  70                 set _sysctrl_ap_unlock_offsets {0xf0 0x50}
  71         }
  72         am642 {
  73                 set _CHIPNAME am642
  74                 set _K3_DAP_TAPID 0x0bb3802f
  75
  76                 # AM642 has 1 clusters of 2 A53 cores each.
  77                 set _armv8_cpu_name a53
  78                 set _armv8_cores 2
  79                 set ARMV8_DBGBASE {0x90010000 0x90110000}
  80                 set ARMV8_CTIBASE {0x90020000 0x90120000}
  81
  82                 # AM642 has 2 cluster of 2 R5s cores.
  83                 set _r5_cores 4
  84                 set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
  85                 set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
  86                 set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
  87
  88                 # M4 processor
  89                 set _gp_mcu_cores 1
  90         }
  91         j721e {
  92                 set _CHIPNAME j721e
  93                 set _K3_DAP_TAPID 0x0bb6402f
  94                 # J721E has 1 cluster of 2 A72 cores.
  95                 set _armv8_cpu_name a72
  96                 set _armv8_cores 2
  97
  98                 # J721E has 3 clusters of 2 R5 cores each.
  99                 set _r5_cores 6
 100         }
 101         j7200 {
 102                 set _CHIPNAME j7200
 103                 set _K3_DAP_TAPID 0x0bb6d02f
 104
 105                 # J7200 has 1 cluster of 2 A72 cores.
 106                 set _armv8_cpu_name a72
 107                 set _armv8_cores 2
 108
 109                 # J7200 has 2 clusters of 2 R5 cores each.
 110                 set _r5_cores 4
 111                 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
 112                 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
 113
 114                 # M3 CTI base
 115                 set CM3_CTIBASE {0x20001000}
 116         }
 117         default {
 118                 echo "'$_soc' is invalid!"
 119         }
 120 }
 121
 122 jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
 123 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 124
 125 set _TARGETNAME $_CHIPNAME.cpu
 126
 127 set _CTINAME $_CHIPNAME.cti
 128
 129 # sysctrl is always present
 130 cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
 131 target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
 132 $_TARGETNAME.sysctrl configure -event reset-assert { }
 133
 134 proc sysctrl_up {} {
 135         # To access sysctrl, we need to enable the JTAG access for the same.
 136         # Ensure Power-AP unlocked
 137         $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
 138         $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
 139
 140         $::_TARGETNAME.sysctrl arp_examine
 141 }
 142
 143 $_TARGETNAME.sysctrl configure -event gdb-attach {
 144         sysctrl_up
 145         # gdb-attach default rule
 146         halt 1000
 147 }
 148
 149 proc _cpu_no_smp_up {} {
 150         set _current_target [target current]
 151         set _current_type [$_current_target cget -type]
 152
 153         $_current_target arp_examine
 154         $_current_target $_current_type dbginit
 155 }
 156
 157 proc _armv8_smp_up {} {
 158         for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
 159                 $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
 160                 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
 161                 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
 162         }
 163         # Set Default target as core 0
 164         targets $::_TARGETNAME.$::_armv8_cpu_name.0
 165 }
 166
 167 set _v8_smp_targets ""
 168
 169 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
 170
 171         cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
 172                 -baseaddr [lindex $ARMV8_CTIBASE $_core]
 173
 174         target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \
 175                 -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
 176
 177         set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
 178
 179         if { $_v8_smp_debug == 0 } {
 180                 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
 181                         _cpu_no_smp_up
 182                         # gdb-attach default rule
 183                         halt 1000
 184                 }
 185         } else {
 186                 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
 187                         _armv8_smp_up
 188                         # gdb-attach default rule
 189                         halt 1000
 190                 }
 191         }
 192 }
 193
 194 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
 195 set _armv8_up_cmd "$_armv8_cpu_name"_up
 196 # Available if V8_SMP_DEBUG is set to non-zero value
 197 set _armv8_smp_cmd "$_armv8_cpu_name"_smp
 198
 199 if { $_v8_smp_debug == 0 } {
 200         proc $_armv8_up_cmd { args } {
 201                 foreach _core $args {
 202                         targets $_core
 203                         _cpu_no_smp_up
 204                 }
 205         }
 206 } else {
 207         proc $_armv8_smp_cmd { args } {
 208                 _armv8_smp_up
 209         }
 210         # Declare SMP
 211         target smp $:::_v8_smp_targets
 212 }
 213
 214 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
 215         set _r5_name [lindex $R5_NAMES $_core]
 216         cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
 217                 -baseaddr [lindex $R5_CTIBASE $_core]
 218
 219         # inactive core examination will fail - wait till startup of additional core
 220         target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
 221                 -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
 222
 223         $_TARGETNAME.$_r5_name configure -event gdb-attach {
 224                 _cpu_no_smp_up
 225                 # gdb-attach default rule
 226                 halt 1000
 227         }
 228 }
 229
 230 proc r5_up { args } {
 231         foreach  _core $args {
 232                 targets $_core
 233                 _cpu_no_smp_up
 234         }
 235 }
 236
 237 if { $_gp_mcu_cores != 0 } {
 238         cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
 239         target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
 240         $_TARGETNAME.gp_mcu configure -event reset-assert { }
 241
 242         proc gp_mcu_up {} {
 243                 # To access GP MCU, we need to enable the JTAG access for the same.
 244                 # Ensure Power-AP unlocked
 245                 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
 246                 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
 247
 248                 $::_TARGETNAME.gp_mcu arp_examine
 249         }
 250
 251         $_TARGETNAME.gp_mcu configure -event gdb-attach {
 252                 gp_mcu_up
 253                 # gdb-attach default rule
 254                 halt 1000
 255         }
 256 }