1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
4 # Texas Instruments K3 devices:
5 # * AM654x: https://www.ti.com/lit/pdf/spruid7
6 # Has 4 ARMV8 Cores and 2 R5 Cores and an M3
7 # * J721E: https://www.ti.com/lit/pdf/spruil1
8 # Has 2 ARMV8 Cores and 6 R5 Cores and an M3
9 # * J7200: https://www.ti.com/lit/pdf/spruiu1
10 # Has 2 ARMV8 Cores and 4 R5 Cores and an M3
11 # * J721S2: https://www.ti.com/lit/pdf/spruj28
12 # Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
13 # * AM642: https://www.ti.com/lit/pdf/spruim2
14 # Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
15 # * AM625: https://www.ti.com/lit/pdf/spruiv7a
16 # Has 4 ARMV8 Cores and 1 R5 Core and an M4F
17 # * AM62a7: https://www.ti.com/lit/pdf/spruj16a
18 # Has 4 ARMV8 Cores and 2 R5 Cores
21 source [find target/swj-dp.tcl]
23 if { [info exists SOC] } {
29 # set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
30 if { [info exists V8_SMP_DEBUG] } {
31 set _v8_smp_debug $V8_SMP_DEBUG
38 # System Controller is the very first processor - all current SoCs have it.
39 set CM3_CTIBASE {0x3C016000}
41 # sysctrl power-ap unlock offsets
42 set _sysctrl_ap_unlock_offsets {0xf0 0x44}
44 # All the ARMV8s are the next processors.
45 # CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
46 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
47 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
49 # And we add up the R5s
50 # (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
51 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
52 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
53 set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
55 # Finally an General Purpose(GP) MCU
56 set CM4_CTIBASE {0x20001000}
58 # General Purpose MCU (M4) may be present on some very few SoCs
60 # General Purpose MCU power-ap unlock offsets
61 set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
63 # Set configuration overrides for each SOC
67 set _K3_DAP_TAPID 0x0bb5a02f
69 # AM654 has 2 clusters of 2 A53 cores each.
70 set _armv8_cpu_name a53
73 # AM654 has 1 cluster of 2 R5s cores.
75 set R5_NAMES {mcu_r5.0 mcu_r5.1}
77 # Sysctrl power-ap unlock offsets
78 set _sysctrl_ap_unlock_offsets {0xf0 0x50}
82 set _K3_DAP_TAPID 0x0bb3802f
84 # AM642 has 1 clusters of 2 A53 cores each.
85 set _armv8_cpu_name a53
87 set ARMV8_DBGBASE {0x90010000 0x90110000}
88 set ARMV8_CTIBASE {0x90020000 0x90120000}
90 # AM642 has 2 cluster of 2 R5s cores.
92 set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
93 set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
94 set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
101 set _K3_DAP_TAPID 0x0bb7e02f
103 # AM625 has 1 clusters of 4 A53 cores.
104 set _armv8_cpu_name a53
106 set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
107 set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
109 # AM625 has 1 cluster of 1 R5s core.
111 set R5_NAMES {main0_r5.0}
112 set R5_DBGBASE {0x9d410000}
113 set R5_CTIBASE {0x9d418000}
116 set CM3_CTIBASE {0x20001000}
117 # Sysctrl power-ap unlock offsets
118 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
122 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
124 # Setup DMEM access descriptions
125 # DAPBUS (Debugger) description
126 set _dmem_base_address 0x740002000
127 set _dmem_ap_address_offset 0x100
129 # Emulated AP description
130 set _dmem_emu_base_address 0x760000000
131 set _dmem_emu_base_address_map_to 0x1d500000
132 set _dmem_emu_ap_list 1
136 set _K3_DAP_TAPID 0x0bb8d02f
138 # AM62a7 has 1 clusters of 4 A53 cores.
139 set _armv8_cpu_name a53
141 set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
142 set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
144 # AM62a7 has 2 cluster of 1 R5s core.
146 set R5_NAMES {main0_r5.0 mcu0_r5.0}
147 set R5_DBGBASE {0x9d410000 0x9d810000}
148 set R5_CTIBASE {0x9d418000 0x9d818000}
151 set CM3_CTIBASE {0x20001000}
152 # Sysctrl power-ap unlock offsets
153 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
157 set _K3_DAP_TAPID 0x0bb6402f
158 # J721E has 1 cluster of 2 A72 cores.
159 set _armv8_cpu_name a72
162 # J721E has 3 clusters of 2 R5 cores each.
167 set _K3_DAP_TAPID 0x0bb6d02f
169 # J7200 has 1 cluster of 2 A72 cores.
170 set _armv8_cpu_name a72
173 # J7200 has 2 clusters of 2 R5 cores each.
175 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
176 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
179 set CM3_CTIBASE {0x20001000}
183 set _K3_DAP_TAPID 0x0bb7502f
185 # J721s2 has 1 cluster of 2 A72 cores.
186 set _armv8_cpu_name a72
189 # J721s2 has 3 clusters of 2 R5 cores each.
193 set CM3_CTIBASE {0x20001000}
194 # Sysctrl power-ap unlock offsets
195 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
199 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
202 echo "'$_soc' is invalid!"
206 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
208 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
210 set _TARGETNAME $_CHIPNAME.cpu
212 set _CTINAME $_CHIPNAME.cti
214 # sysctrl is always present
215 cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
216 target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
217 $_TARGETNAME.sysctrl configure -event reset-assert { }
220 # To access sysctrl, we need to enable the JTAG access for the same.
221 # Ensure Power-AP unlocked
222 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
223 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
225 $::_TARGETNAME.sysctrl arp_examine
228 $_TARGETNAME.sysctrl configure -event gdb-attach {
230 # gdb-attach default rule
234 proc _cpu_no_smp_up {} {
235 set _current_target [target current]
236 set _current_type [$_current_target cget -type]
238 $_current_target arp_examine
239 $_current_target $_current_type dbginit
242 proc _armv8_smp_up {} {
243 for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
244 $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
245 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
246 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
248 # Set Default target as core 0
249 targets $::_TARGETNAME.$::_armv8_cpu_name.0
252 set _v8_smp_targets ""
254 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
256 cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
257 -baseaddr [lindex $ARMV8_CTIBASE $_core]
259 target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \
260 -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
262 set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
264 if { $_v8_smp_debug == 0 } {
265 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
267 # gdb-attach default rule
271 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
273 # gdb-attach default rule
279 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
280 set _armv8_up_cmd "$_armv8_cpu_name"_up
281 # Available if V8_SMP_DEBUG is set to non-zero value
282 set _armv8_smp_cmd "$_armv8_cpu_name"_smp
284 if { $_v8_smp_debug == 0 } {
285 proc $_armv8_up_cmd { args } {
286 foreach _core $args {
292 proc $_armv8_smp_cmd { args } {
296 target smp $:::_v8_smp_targets
299 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
300 set _r5_name [lindex $R5_NAMES $_core]
301 cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
302 -baseaddr [lindex $R5_CTIBASE $_core]
304 # inactive core examination will fail - wait till startup of additional core
305 target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
306 -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
308 $_TARGETNAME.$_r5_name configure -event gdb-attach {
310 # gdb-attach default rule
315 proc r5_up { args } {
316 foreach _core $args {
322 if { $_gp_mcu_cores != 0 } {
323 cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
324 target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
325 $_TARGETNAME.gp_mcu configure -event reset-assert { }
328 # To access GP MCU, we need to enable the JTAG access for the same.
329 # Ensure Power-AP unlocked
330 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
331 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
333 $::_TARGETNAME.gp_mcu arp_examine
336 $_TARGETNAME.gp_mcu configure -event gdb-attach {
338 # gdb-attach default rule
343 # In case of DMEM access, configure the dmem adapter with offsets from above.
344 if { 0 == [string compare [adapter name] dmem ] } {
345 if { [info exists _dmem_base_address] } {
346 # DAPBUS (Debugger) description
347 dmem base_address $_dmem_base_address
348 dmem ap_address_offset $_dmem_ap_address_offset
349 dmem max_aps $_dmem_max_aps
351 # The following are the details of APs to be emulated for direct address access.
352 # Debug Config (Debugger) description
353 dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to
354 dmem emu_ap_list $_dmem_emu_ap_list
355 # We are going local bus, so speed is really dummy here.
358 puts "ERROR: ${SOC} data is missing to support dmem access!"