1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
4 # Texas Instruments K3 devices:
5 # * AM243: https://www.ti.com/lit/pdf/spruim2
6 # Has 4 R5 Cores, M4F and an M3
7 # * AM263: https://www.ti.com/lit/pdf/spruj17
8 # Has 4 R5 Cores and an M3
9 # * AM273: https://www.ti.com/lit/pdf/spruiu0
10 # Has 2 R5 Cores and an M3
11 # * AM625: https://www.ti.com/lit/pdf/spruiv7a
12 # Has 4 ARMV8 Cores and 1 R5 Core and an M4F
13 # * AM62A7: https://www.ti.com/lit/pdf/spruj16a
14 # Has 4 ARMV8 Cores and 2 R5 Cores
15 # * AM62P: https://www.ti.com/lit/pdf/spruj83
16 # Has 4 ARMV8 Cores and 2 R5 Cores
17 # * AM642: https://www.ti.com/lit/pdf/spruim2
18 # Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
19 # * AM654x: https://www.ti.com/lit/pdf/spruid7
20 # Has 4 ARMV8 Cores and 2 R5 Cores and an M3
21 # * J7200: https://www.ti.com/lit/pdf/spruiu1
22 # Has 2 ARMV8 Cores and 4 R5 Cores and an M3
23 # * J721E: https://www.ti.com/lit/pdf/spruil1
24 # Has 2 ARMV8 Cores and 6 R5 Cores and an M3
25 # * J721S2: https://www.ti.com/lit/pdf/spruj28
26 # Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
27 # * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
28 # Has 8 ARMV8 Cores and 8 R5 Cores
31 source [find target/swj-dp.tcl]
33 if { [info exists SOC] } {
39 # set V8_SMP_DEBUG to non 0 value in board if you'd like to use SMP debug
40 if { [info exists V8_SMP_DEBUG] } {
41 set _v8_smp_debug $V8_SMP_DEBUG
48 # System Controller is the very first processor - all current SoCs have it.
49 set CM3_CTIBASE {0x3C016000}
51 # sysctrl power-ap unlock offsets
52 set _sysctrl_ap_unlock_offsets {0xf0 0x44}
55 # All the ARMV8s are the next processors.
56 # CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
57 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90810000 0x90910000}
58 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
60 # And we add up the R5s
61 # (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
62 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
63 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
64 set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
67 # Finally an General Purpose(GP) MCU
68 set CM4_CTIBASE {0x20001000}
70 # General Purpose MCU (M4) may be present on some very few SoCs
72 # General Purpose MCU power-ap unlock offsets
73 set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
75 # Generic mem-ap port number
78 # Set configuration overrides for each SOC
81 set _K3_DAP_TAPID 0x2bb7d02f
86 # AM263 has 0 ARMV8 CPUs
89 # AM263 has 2 cluster of 2 R5s cores.
91 set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
92 set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000}
93 set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000}
97 set _K3_DAP_TAPID 0x1bb6a02f
102 # system controller is on AP0
103 set _sysctrl_ap_num 0
105 # AM273 has 0 ARMV8 CPUs
108 # AM273 has 1 cluster of 2 R5s cores.
110 set R5_NAMES {main0_r5.0 main0_r5.1}
111 set R5_DBGBASE {0x90030000 0x90032000}
112 set R5_CTIBASE {0x90038000 0x90039000}
116 set _K3_DAP_TAPID 0x0bb5a02f
118 # AM654 has 2 clusters of 2 A53 cores each.
119 set _armv8_cpu_name a53
122 # AM654 has 1 cluster of 2 R5s cores.
124 set R5_NAMES {mcu_r5.0 mcu_r5.1}
126 # Sysctrl power-ap unlock offsets
127 set _sysctrl_ap_unlock_offsets {0xf0 0x50}
131 set _K3_DAP_TAPID 0x0bb3802f
133 # AM642 has 1 clusters of 2 A53 cores each.
134 set _armv8_cpu_name a53
136 set ARMV8_DBGBASE {0x90010000 0x90110000}
137 set ARMV8_CTIBASE {0x90020000 0x90120000}
139 # AM642 has 2 cluster of 2 R5s cores.
141 set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
142 set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
143 set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
148 # Overrides for am243
149 if { "$_soc" == "am243" } {
150 # Uses the same JTAG ID
155 set _K3_DAP_TAPID 0x0bb7e02f
157 # AM625 has 1 clusters of 4 A53 cores.
158 set _armv8_cpu_name a53
160 set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
161 set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
163 # AM625 has 1 cluster of 1 R5s core.
165 set R5_NAMES {main0_r5.0}
166 set R5_DBGBASE {0x9d410000}
167 set R5_CTIBASE {0x9d418000}
170 set CM3_CTIBASE {0x20001000}
171 # Sysctrl power-ap unlock offsets
172 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
176 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
178 # Setup DMEM access descriptions
179 # DAPBUS (Debugger) description
180 set _dmem_base_address 0x740002000
181 set _dmem_ap_address_offset 0x100
183 # Emulated AP description
184 set _dmem_emu_base_address 0x760000000
185 set _dmem_emu_base_address_map_to 0x1d500000
186 set _dmem_emu_ap_list 1
190 set _K3_DAP_TAPID 0x0bb8d02f
192 # AM62a7/AM62P has 1 cluster of 4 A53 cores.
193 set _armv8_cpu_name a53
195 set ARMV8_DBGBASE {0x90010000 0x90110000 0x90210000 0x90310000}
196 set ARMV8_CTIBASE {0x90020000 0x90120000 0x90220000 0x90320000}
198 # AM62a7/AM62P has 2 cluster of 1 R5 core.
200 set R5_NAMES {main0_r5.0 mcu0_r5.0}
201 set R5_DBGBASE {0x9d410000 0x9d810000}
202 set R5_CTIBASE {0x9d418000 0x9d818000}
205 set CM3_CTIBASE {0x20001000}
206 # Sysctrl power-ap unlock offsets
207 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
209 # Overrides for am62p
210 if { "$_soc" == "am62p" } {
211 set _K3_DAP_TAPID 0x0bb9d02f
212 set R5_NAMES {wkup0_r5.0 mcu0_r5.0}
216 set _K3_DAP_TAPID 0x0bb6402f
217 # J721E has 1 cluster of 2 A72 cores.
218 set _armv8_cpu_name a72
221 # J721E has 3 clusters of 2 R5 cores each.
224 # Setup DMEM access descriptions
225 # DAPBUS (Debugger) description
226 set _dmem_base_address 0x4c40002000
227 set _dmem_ap_address_offset 0x100
229 # Emulated AP description
230 set _dmem_emu_base_address 0x4c60000000
231 set _dmem_emu_base_address_map_to 0x1d600000
232 set _dmem_emu_ap_list 1
235 set _K3_DAP_TAPID 0x0bb6d02f
237 # J7200 has 1 cluster of 2 A72 cores.
238 set _armv8_cpu_name a72
241 # J7200 has 2 clusters of 2 R5 cores each.
243 set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
244 set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
247 set CM3_CTIBASE {0x20001000}
250 set _K3_DAP_TAPID 0x0bb7502f
252 # J721s2 has 1 cluster of 2 A72 cores.
253 set _armv8_cpu_name a72
256 # J721s2 has 3 clusters of 2 R5 cores each.
260 set CM3_CTIBASE {0x20001000}
261 # Sysctrl power-ap unlock offsets
262 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
266 set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
269 set _K3_DAP_TAPID 0x0bb8002f
271 # j784s4 has 2 cluster of 4 A72 cores each.
272 set _armv8_cpu_name a72
274 set ARMV8_DBGBASE {0x90410000 0x90510000 0x90610000 0x90710000
275 0x90810000 0x90910000 0x90a10000 0x90b10000}
276 set ARMV8_CTIBASE {0x90420000 0x90520000 0x90620000 0x90720000
277 0x90820000 0x90920000 0x90a20000 0x90b20000}
279 # J721s2 has 4 clusters of 2 R5 cores each.
281 set R5_DBGBASE {0x9d010000 0x9d012000
282 0x9d410000 0x9d412000
283 0x9d510000 0x9d512000
284 0x9d610000 0x9d612000}
285 set R5_CTIBASE {0x9d018000 0x9d019000
286 0x9d418000 0x9d419000
287 0x9d518000 0x9d519000
288 0x9d618000 0x9d619000}
289 set R5_NAMES {mcu_r5.0 mcu_r5.1
290 main0_r5.0 main0_r5.1
291 main1_r5.0 main1_r5.1
292 main2_r5.0 main2_r5.1}
295 set CM3_CTIBASE {0x20001000}
296 # Sysctrl power-ap unlock offsets
297 set _sysctrl_ap_unlock_offsets {0xf0 0x78}
300 echo "'$_soc' is invalid!"
304 proc _get_rtos_type_for_cpu { target_name } {
305 if { [info exists ::RTOS($target_name)] } {
306 return $::RTOS($target_name)
313 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
315 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
317 set _TARGETNAME $_CHIPNAME.cpu
319 set _CTINAME $_CHIPNAME.cti
321 # sysctrl is always present
322 cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \
323 -ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0]
325 target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \
326 -ap-num $_sysctrl_ap_num -defer-examine \
327 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
329 $_TARGETNAME.sysctrl configure -event reset-assert { }
332 # To access sysctrl, we need to enable the JTAG access for the same.
333 # Ensure Power-AP unlocked
334 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
335 $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
337 $::_TARGETNAME.sysctrl arp_examine
340 $_TARGETNAME.sysctrl configure -event gdb-attach {
342 # gdb-attach default rule
346 proc _cpu_no_smp_up {} {
347 set _current_target [target current]
348 set _current_type [$_current_target cget -type]
350 $_current_target arp_examine
351 $_current_target $_current_type dbginit
354 proc _armv8_smp_up {} {
355 for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
356 $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
357 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
358 $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
360 # Set Default target as core 0
361 targets $::_TARGETNAME.$::_armv8_cpu_name.0
364 set _v8_smp_targets ""
366 for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
368 cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
369 -baseaddr [lindex $ARMV8_CTIBASE $_core]
371 target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
372 -dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
373 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]
375 set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
377 if { $_v8_smp_debug == 0 } {
378 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
380 # gdb-attach default rule
384 $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
386 # gdb-attach default rule
392 if { $_armv8_cores > 0 } {
393 # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
394 set _armv8_up_cmd "$_armv8_cpu_name"_up
395 # Available if V8_SMP_DEBUG is set to non-zero value
396 set _armv8_smp_cmd "$_armv8_cpu_name"_smp
398 if { $_v8_smp_debug == 0 } {
399 proc $_armv8_up_cmd { args } {
400 foreach _core $args {
406 proc $_armv8_smp_cmd { args } {
410 target smp {*}$_v8_smp_targets
414 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
415 set _r5_name [lindex $R5_NAMES $_core]
416 cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
417 -baseaddr [lindex $R5_CTIBASE $_core]
419 # inactive core examination will fail - wait till startup of additional core
420 target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
421 -dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
422 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
424 $_TARGETNAME.$_r5_name configure -event gdb-attach {
426 # gdb-attach default rule
431 proc r5_up { args } {
432 foreach _core $args {
438 if { $_gp_mcu_cores != 0 } {
439 cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
440 target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
441 -rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
442 $_TARGETNAME.gp_mcu configure -event reset-assert { }
445 # To access GP MCU, we need to enable the JTAG access for the same.
446 # Ensure Power-AP unlocked
447 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
448 $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
450 $::_TARGETNAME.gp_mcu arp_examine
453 $_TARGETNAME.gp_mcu configure -event gdb-attach {
455 # gdb-attach default rule
460 # In case of DMEM access, configure the dmem adapter with offsets from above.
461 if { 0 == [string compare [adapter name] dmem ] } {
462 if { [info exists _dmem_base_address] } {
463 # DAPBUS (Debugger) description
464 dmem base_address $_dmem_base_address
465 dmem ap_address_offset $_dmem_ap_address_offset
466 dmem max_aps $_dmem_max_aps
468 # The following are the details of APs to be emulated for direct address access.
469 # Debug Config (Debugger) description
470 dmem emu_base_address_range $_dmem_emu_base_address $_dmem_emu_base_address_map_to
471 dmem emu_ap_list $_dmem_emu_ap_list
472 # We are going local bus, so speed is really dummy here.
475 puts "ERROR: ${SOC} data is missing to support dmem access!"
478 # AXI AP access port for SoC address map
479 target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num