tcl/target/stm32wbax.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # script for stm32wbax family
   4
   5 #
   6 # stm32wba devices support both JTAG and SWD transports.
   7 #
   8 source [find target/swj-dp.tcl]
   9 source [find mem_helper.tcl]
  10
  11 if { [info exists CHIPNAME] } {
  12     set _CHIPNAME $CHIPNAME
  13 } else {
  14     set _CHIPNAME stm32wbax
  15 }
  16
  17 # Work-area is a space in RAM used for flash programming
  18 # By default use 64kB
  19 if { [info exists WORKAREASIZE] } {
  20     set _WORKAREASIZE $WORKAREASIZE
  21 } else {
  22     set _WORKAREASIZE 0x10000
  23 }
  24
  25 #jtag scan chain
  26 if { [info exists CPUTAPID] } {
  27     set _CPUTAPID $CPUTAPID
  28 } else {
  29     if { [using_jtag] } {
  30         set _CPUTAPID 0x6ba00477
  31     } else {
  32         # SWD IDCODE (single drop, arm)
  33         set _CPUTAPID 0x6ba02477
  34     }
  35 }
  36
  37 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  38 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
  39
  40 if {[using_jtag]} {
  41     jtag newtap $_CHIPNAME bs -irlen 5
  42 }
  43
  44 set _TARGETNAME $_CHIPNAME.cpu
  45 target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap -ap-num 1
  46
  47 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
  48
  49 flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
  50 flash bank $_CHIPNAME.otp   stm32l4x 0x0FF90000 0 0 0 $_TARGETNAME
  51
  52 # Common knowledges tells JTAG speed should be <= F_CPU/6.
  53 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
  54 # the safe side.
  55 #
  56 # Note that there is a pretty wide band where things are
  57 # more or less stable, see http://openocd.zylin.com/#/c/3366/
  58 adapter speed 500
  59
  60 adapter srst delay 100
  61 if {[using_jtag]} {
  62     jtag_ntrst_delay 100
  63 }
  64
  65 reset_config srst_nogate
  66
  67 if {![using_hla]} {
  68     # if srst is not fitted use SYSRESETREQ to
  69     # perform a soft reset
  70     cortex_m reset_config sysresetreq
  71 }
  72
  73 $_TARGETNAME configure -event reset-init {
  74     # CPU comes out of reset with HSION | HSIRDY.
  75     # Use HSI 16 MHz clock, compliant even with VOS == 2.
  76     # 1 WS compliant with VOS == 2 and 16 MHz.
  77     mmw 0x40022000 0x00000001 0x0000000E        ;# FLASH_ACR: Latency = 1
  78     mmw 0x56020C00 0x00000100 0x00000000        ;# RCC_CR |= HSION
  79     mmw 0x56020C1C 0x00000000 0x00000002        ;# RCC_CFGR1: SW=HSI16
  80     # Boost JTAG frequency
  81     adapter speed 4000
  82 }
  83
  84 $_TARGETNAME configure -event reset-start {
  85     # Reset clock is HSI (16 MHz)
  86     adapter speed 2000
  87 }
  88
  89 $_TARGETNAME configure -event examine-end {
  90     # Enable debug during low power modes (uses more power)
  91     # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
  92     mmw 0xE0042004 0x00000006 0
  93
  94     # Stop watchdog counters during halt
  95     # DBGMCU_APB1LFZR |= DBG_IWDG_STOP | DBG_WWDG_STOP
  96     mmw 0xE0042008 0x00001800 0
  97 }
  98
  99 tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
 100
 101 lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
 102 proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname} {
 103     targets $_targetname
 104 }
 105
 106 $_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME"