1 # script for stm32l4x family
4 # stm32l4 devices support both JTAG and SWD transports.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32l4x
17 # Work-area is a space in RAM used for flash programming
18 # Smallest current target has 64kB ram, use 32kB by default to avoid surprises
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0x8000
26 if { [info exists CPUTAPID] } {
27 set _CPUTAPID $CPUTAPID
30 # See STM Document RM0351
31 # Section 44.6.3 - corresponds to Cortex-M4 r0p1
32 set _CPUTAPID 0x4ba00477
34 set _CPUTAPID 0x2ba01477
38 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
41 jtag newtap $_CHIPNAME bs -irlen 5
44 set _TARGETNAME $_CHIPNAME.cpu
45 target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
47 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
49 set _FLASHNAME $_CHIPNAME.flash
50 flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
52 # Common knowledges tells JTAG speed should be <= F_CPU/6.
53 # F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
56 # Note that there is a pretty wide band where things are
57 # more or less stable, see http://openocd.zylin.com/#/c/3366/
60 adapter_nsrst_delay 100
65 reset_config srst_nogate
68 # if srst is not fitted use SYSRESETREQ to
69 # perform a soft reset
70 cortex_m reset_config sysresetreq
73 $_TARGETNAME configure -event reset-init {
74 # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
75 # Use MSI 24 MHz clock, compliant even with VOS == 2.
76 # 3 WS compliant with VOS == 2 and 24 MHz.
77 mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency)
78 mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL| MSI Range 10
79 # Boost JTAG frequency
83 $_TARGETNAME configure -event reset-start {
84 # Reset clock is MSI (4 MHz)
88 $_TARGETNAME configure -event examine-end {
89 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
90 mmw 0xE0042004 0x00000007 0
92 # Stop watchdog counters during halt
93 # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
94 mmw 0xE0042008 0x00001800 0
97 $_TARGETNAME configure -event trace-config {
98 # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
99 # change this value accordingly to configure trace pins
101 mmw 0xE0042004 0x00000020 0
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