1 if { [info exists CHIPNAME] } {
2 set _CHIPNAME $CHIPNAME
7 if { [info exists ENDIAN] } {
13 if { [info exists CPUTAPID] } {
14 set _CPUTAPID $CPUTAPID
16 set _CPUTAPID 0x30938053
19 # default working area is 16384
20 if { [info exists WORKAREASIZE] } {
21 set _WORKAREASIZE $WORKAREASIZE
23 set _WORKAREASIZE 0x4000
26 adapter_nsrst_delay 100
30 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
31 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
33 set _TARGETNAME $_CHIPNAME.cpu
34 target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
37 # At reset the pic32mx does not allow code execution from RAM
38 # we have to setup the BMX registers to allow this.
39 # One limitation is that we loose the first 2k of RAM.
42 global _PIC32MX_DATASIZE
44 set _PIC32MX_DATASIZE 0x800
45 set _PIC32MX_PROGSIZE [expr ($_WORKAREASIZE - $_PIC32MX_DATASIZE)]
47 $_TARGETNAME configure -work-area-phys 0xa0000800 -work-area-size $_PIC32MX_PROGSIZE -work-area-backup 0
48 $_TARGETNAME configure -event reset-init {
50 # from reset the pic32 cannot execute code in ram - enable ram execution
51 # minimum offset from start of ram is 2k
54 global _PIC32MX_DATASIZE
58 mww 0xbf882000 0x001f0040
59 # BMXDKPBA: 2k kernel data @ 0xa0000000
60 mww 0xbf882010 $_PIC32MX_DATASIZE
61 # BMXDUDBA: 14k kernel program @ 0xa0000800 - (BMXDUDBA - BMXDKPBA)
62 mww 0xbf882020 $_WORKAREASIZE
63 # BMXDUPBA: 0k user program - (BMXDUPBA - BMXDUDBA)
64 mww 0xbf882030 $_WORKAREASIZE
67 # Set system clock to 8Mhz if the default clock configuration is set
70 # SYSKEY register, make sure OSCCON is locked
72 # SYSKEY register, write unlock sequence
73 mww 0xbf80f230 0xaa996655
74 mww 0xbf80f230 0x556699aa
75 # OSCCON register + 4, clear OSCCON FRCDIV bits: 24, 25 and 26, divided by 1
76 mww 0xbf80f004 0x07000000
77 # SYSKEY register, relock OSCCON
81 set _FLASHNAME $_CHIPNAME.flash0
82 flash bank $_FLASHNAME pic32mx 0x1fc00000 0 0 0 $_TARGETNAME
83 # add virtual banks for kseg0 and kseg1
84 flash bank vbank0 virtual 0xbfc00000 0 0 0 $_TARGETNAME $_FLASHNAME
85 flash bank vbank1 virtual 0x9fc00000 0 0 0 $_TARGETNAME $_FLASHNAME
87 set _FLASHNAME $_CHIPNAME.flash1
88 flash bank $_FLASHNAME pic32mx 0x1d000000 0 0 0 $_TARGETNAME
89 # add virtual banks for kseg0 and kseg1
90 flash bank vbank2 virtual 0xbd000000 0 0 0 $_TARGETNAME $_FLASHNAME
91 flash bank vbank3 virtual 0x9d000000 0 0 0 $_TARGETNAME $_FLASHNAME
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