1 # NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator
3 if { [info exists CHIPNAME] } {
4 set _CHIPNAME $CHIPNAME
9 if { [info exists ENDIAN] } {
15 if { [info exists CPUTAPID ] } {
16 set _CPUTAPID $CPUTAPID
18 set _CPUTAPID 0x4ba00477
21 #delays on reset lines
25 # LPC2000 & LPC1700 -> SRST causes TRST
26 reset_config trst_and_srst srst_pulls_trst
28 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
30 set _TARGETNAME $_CHIPNAME.cpu
31 target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
33 # LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
34 $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
36 $_TARGETNAME configure -event reset-init {
37 # Force target into ARM state
39 #do not remap 0x0000-0x0020 to anything but the flash
44 # LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region).
45 # flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
47 set _FLASHNAME $_CHIPNAME.flash
48 flash bank $_FLASHNAME lpc2000 0x0 0x80000 0 0 $_TARGETNAME lpc1700 12000 calc_checksum
50 # 4MHz / 6 = 666kHz, so use 500
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