3 ######################################
4 # Target: Atmel AT91SAM9260
5 ######################################
7 if { [info exists CHIPNAME] } {
8 set _CHIPNAME $CHIPNAME
10 set _CHIPNAME at91sam9260
13 if { [info exists ENDIAN] } {
19 if { [info exists CPUTAPID ] } {
20 set _CPUTAPID $CPUTAPID
22 # force an error till we get a good number
23 set _CPUTAPID 0x0792603f
26 reset_config trst_and_srst
29 adapter_nsrst_delay 200
33 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
36 ######################
37 # Target configuration
38 ######################
40 set _TARGETNAME $_CHIPNAME.cpu
41 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
43 # Internal sram1 memory
44 $_TARGETNAME configure -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
47 $_TARGETNAME configure -event reset-start {
48 # at reset chip runs at 32khz
52 $_TARGETNAME configure -event reset-init {at91sam_init}
55 #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
56 set _FLASHNAME $_CHIPNAME.flash
57 flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 $_TARGETNAME
59 # Faster memory downloads. This is disabled automatically during
60 # reset init since all reset init sequences are too short for
62 arm7_9 dcc_downloads enable
63 arm7_9 fast_memory_access enable
65 proc at91sam_init { } {
66 mww 0xfffffd08 0xa5000501 # RSTC_MR : enable user reset
67 mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
69 mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
71 mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
73 mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198,656MHz
75 mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler
77 mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected
80 # Now run at anything fast... ie: 10mhz!
81 jtag_rclk 10000 # Increase JTAG Speed to 6 MHz
83 mww 0xffffec00 0x0a0a0a0a # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
84 mww 0xffffec04 0x0b0b0b0b # SMC_PULSE0
85 mww 0xffffec08 0x00160016 # SMC_CYCLE0
86 mww 0xffffec0c 0x00161003 # SMC_MODE0
88 mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
89 mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
91 mww 0xffffef1c 0x2 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
93 mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
94 #mww 0xffffea08 0x85227254 # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
96 mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
98 mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
100 mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
116 mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
118 mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
120 mww 0xffffea04 0x5d2 # SDRAMC_TR : Set refresh timer count to 15us
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