1 # SPDX-License-Identifier: GPL-2.0-or-later
2 # Cadence virtual debug interface
3 # RISCV Ibex core with Pulpissimo through JTAG
5 source [find interface/vdebug.cfg]
9 set _CPUTAPID 0x249511c3
11 # vdebug select transport
14 # JTAG reset config, frequency and reset delay
15 reset_config trst_and_srst
19 # BFM hierarchical path and input clk period
20 vdebug bfm_path tbench.u_vd_jtag_bfm 40ns
22 # DMA Memories to access backdoor (up to 4)
23 vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[0\].sram_i.mem_array 0x1c000000 0x8000
24 vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2_pri\[1\].sram_i.mem_array 0x1c008000 0x8000
25 vdebug mem_path tbench.soc_domain_i.pulp_soc_i.gen_mem_l2\[0\].sram_i.mem_array 0x1c010000 0x80000
27 # need to explicitly define riscv tap, autoprobing does not work for icapture != 0x01
28 jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x05 -irmask 0x1f -expected-id $_CPUTAPID
32 source [find target/vd_riscv.cfg]
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