tcl/board/vd_a75x4_jtag.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2 # Cadence virtual debug interface
   3 # Arm Cortex A53x2 through DAP
   4
   5 source [find interface/vdebug.cfg]
   6
   7 set CORES 4
   8 set CHIPNAME a75
   9 set ACCESSPORT 0x00040000
  10 set MEMSTART 0x00000000
  11 set MEMSIZE 0x1000000
  12 set DBGBASE {0x01010000 0x01110000 0x01210000 0x01310000}
  13 set CTIBASE {0x01020000 0x01120000 0x01220000 0x01320000}
  14 set CPUTAPID 0x4ba06477
  15
  16 # vdebug select transport
  17 transport select jtag
  18
  19 # JTAG reset config, frequency and reset delay
  20 reset_config trst_and_srst
  21 adapter speed 1500000
  22 adapter srst delay 5
  23
  24 # BFM hierarchical path and input clk period
  25 vdebug bfm_path tbench.u_vd_jtag_bfm 333ps
  26
  27 jtag newtap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $CPUTAPID
  28 jtag arp_init-reset
  29
  30 source [find target/vd_aarch64.cfg]