tcl/board/vd_a53x2_dap.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2 # Cadence virtual debug interface
   3 # Arm Cortex A53x2 through DAP
   4
   5 source [find interface/vdebug.cfg]
   6
   7 set CORES 2
   8 set CHIPNAME a53
   9 set ACCESSPORT 0
  10 set MEMSTART 0x00000000
  11 set MEMSIZE 0x1000000
  12 set DBGBASE {0x80810000 0x80910000}
  13 set CTIBASE {0x80820000 0x80920000}
  14
  15 # vdebug select transport
  16 transport select dapdirect_swd
  17
  18 # JTAG reset config, frequency and reset delay
  19 adapter speed 50000
  20 adapter srst delay 5
  21
  22 # BFM hierarchical path and input clk period
  23 vdebug bfm_path tbench.u_vd_swdp_bfm 10ns
  24
  25 # DMA Memories to access backdoor (up to 20)
  26 vdebug mem_path tbench.u_memory.mem_array $MEMSTART $MEMSIZE
  27
  28 swd newdap $CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
  29
  30 source [find target/vd_aarch64.cfg]