tcl/board/stm32f413h-disco.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # This is an STM32F413H discovery board with a single STM32F413ZHT6 chip.
   4 # http://www.st.com/en/evaluation-tools/32f413hdiscovery.html
   5
   6 #
   7 # Untested!!!
   8 #
   9
  10 # This is for using the onboard STLINK
  11 source [find interface/stlink.cfg]
  12
  13 transport select hla_swd
  14
  15 # increase working area to 128KB
  16 set WORKAREASIZE 0x20000
  17
  18 # enable stmqspi
  19 set QUADSPI 1
  20
  21 source [find target/stm32f4x.cfg]
  22
  23 # QUADSPI initialization
  24 proc qspi_init { } {
  25         global a
  26         mmw 0x40023830 0x000000FF 0                             ;# RCC_AHB1ENR |= GPIOAEN-GPIOHEN (enable clocks)
  27         mmw 0x40023838 0x00000002 0                             ;# RCC_AHB3ENR |= QSPIEN (enable clock)
  28         sleep 1                                                                 ;# Wait for clock startup
  29
  30         # PG06: BK1_NCS, PB02: CLK, PD13: BK1_IO3, PE02: BK1_IO2, PF09: BK1_IO1, PF08: BK1_IO0
  31
  32         # PB02:AF09:V, PD13:AF09:V, PE02:AF09:V, PF09:AF10:V, PF08:AF10:V, PG06:AF10:V
  33
  34         # Port B: PB02:AF09:V
  35         mmw 0x40020400 0x00000020 0x00000010    ;# MODER
  36         mmw 0x40020408 0x00000030 0x00000000    ;# OSPEEDR
  37         mmw 0x40020420 0x00000900 0x00000600    ;# AFRL
  38
  39         # Port D: PD13:AF09:V
  40         mmw 0x40020C00 0x08000000 0x04000000    ;# MODER
  41         mmw 0x40020C08 0x0C000000 0x00000000    ;# OSPEEDR
  42         mmw 0x40020C24 0x00900000 0x00600000    ;# AFRH
  43
  44         # Port E: PE02:AF09:V
  45         mmw 0x40021000 0x00000020 0x00000010    ;# MODER
  46         mmw 0x40021008 0x00000030 0x00000000    ;# OSPEEDR
  47         mmw 0x40021020 0x00000900 0x00000600    ;# AFRL
  48
  49         # Port F: PF09:AF10:V, PF08:AF10:V
  50         mmw 0x40021400 0x000A0000 0x00050000    ;# MODER
  51         mmw 0x40021408 0x000F0000 0x00000000    ;# OSPEEDR
  52         mmw 0x40021424 0x000000AA 0x00000055    ;# AFRH
  53
  54         # Port G: PG06:AF10:V
  55         mmw 0x40021800 0x00002000 0x00001000    ;# MODER
  56         mmw 0x40021808 0x00003000 0x00000000    ;# OSPEEDR
  57         mmw 0x40021820 0x0A000000 0x05000000    ;# AFRL
  58
  59         mww 0xA0001030 0x00001000                               ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
  60         mww 0xA0001000 0x03500008                               ;# QUADSPI_CR: PRESCALER=3, APMS=1, FTHRES=0, FSEL=0, DFM=0, SSHIFT=0, TCEN=1
  61         mww 0xA0001004 0x00170100                               ;# QUADSPI_DCR: FSIZE=0x17, CSHT=0x01, CKMODE=0
  62         mmw 0xA0001000 0x00000001 0                             ;# QUADSPI_CR: EN=1
  63
  64         # 1-line spi mode
  65         mww 0xA0001014 0x000003F5                               ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=RSTQIO
  66         sleep 1
  67
  68         # memory-mapped read mode with 3-byte addresses
  69         mww 0xA0001014 0x0D002503                               ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1, INSTR=READ
  70 }
  71
  72 $_TARGETNAME configure -event reset-init {
  73         mww 0x40023C00 0x00000003                               ;# 3 WS for 96 MHz HCLK
  74         sleep 1
  75         mww 0x40023804 0x24001808                               ;# 96 MHz: HSI, PLLM=8, PLLN=96, PLLP=2
  76         mww 0x40023808 0x00001000                               ;# APB1: /2, APB2: /1
  77         mmw 0x40023800 0x01000000 0x00000000    ;# PLL on
  78         sleep 1
  79         mmw 0x40023808 0x00000002 0x00000000    ;# switch to PLL
  80         sleep 1
  81
  82         adapter speed 4000
  83
  84         qspi_init
  85 }