1 # SPDX-License-Identifier: GPL-2.0-or-later
3 source [find target/lpc3250.cfg]
8 reset_config trst_and_srst separate
10 arm7_9 dcc_downloads enable
12 $_TARGETNAME configure -event gdb-attach { reset init }
14 $_TARGETNAME configure -event reset-start {
15 arm7_9 fast_memory_access disable
19 $_TARGETNAME configure -event reset-end {
21 arm7_9 fast_memory_access enable
24 $_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
26 # Bare-bones initialization of core clocks and SDRAM
27 proc phytec_lpc3250_init { } {
31 # PERIPHCLK = 13.325 MHz
35 mww 0x40004058 0x16250
46 # Init SDRAM with 133 MHz timings
47 mww 0x40028134 0x00FFFFFF
48 mww 0x4002802C 0x00000008
52 mww 0x40004068 0x1C000
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