tcl/board/glyn_tonga2.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #
   4 # Glyn Tonga2 SO-DIMM CPU module (Toshiba TMPA900CMXBG, ARM9)
   5 #
   6 # http://toshiba-mikrocontroller.de/sites/TMPA900CPUBOARDStarter.htm
   7 #
   8 # Hardware on the S0-DIMM module:
   9 #   - Toshiba TMPA900CMXBG (ARM9, ARM926EJ-S, max. 200MHz)
  10 #   - DDR SDRAM: Hynix H5MS5162DFR-J3M (64Mbyte, x16, 1.8V, 166/83MHz at CL3/2)
  11 #   - NAND flash: Samsung K9F2G08U0B-PIB0 (256M x 8 Bit, 3.3V)
  12 #   - Ethernet: SMSC LAN9221I-ABZJ (10/100Mbit, Non-PCI, 16 bit interface)
  13 #
  14
  15 source [find target/tmpa900.cfg]
  16
  17 ########################
  18 # Target configuration #
  19 ########################
  20
  21 # Initial JTAG speed should not exceed 1/6 of the initial CPU clock
  22 # frequency (24MHz). Be conservative and use 1/8 of the frequency.
  23 # (24MHz / 8 = 3MHz)
  24 adapter speed 3000
  25
  26 $_TARGETNAME configure -event reset-start {
  27         # Upon reset, set the JTAG frequency to 3MHz again, see above.
  28         echo "Setting JTAG speed to 3MHz until clocks are initialized."
  29         adapter speed 3000
  30
  31         # Halt the CPU.
  32         halt
  33
  34         # Disable faster memory access for now.
  35         arm7_9 fast_memory_access disable
  36 }
  37
  38 $_TARGETNAME configure -event reset-init {
  39         # Setup clocks, and initialize SRAM and DDR SDRAM.
  40         tonga2_init
  41
  42         # At this point the CPU is running at 192MHz, increase JTAG speed.
  43         # Tests showed that 15MHz works OK, higher speeds can cause problems,
  44         # though. Not sure if this is a CPU issue or JTAG adapter issue.
  45         echo "Increasing JTAG speed to 15MHz."
  46         adapter speed 15000
  47
  48         # Enable faster memory access.
  49         arm7_9 fast_memory_access enable
  50 }
  51
  52 proc tonga2_init { } {
  53         ######################
  54         # PLL initialization #
  55         ######################
  56
  57         # Clock overview (see datasheet chapter 3.5.2, page 57):
  58         #   - fs: Low-frequency oscillator
  59         #   - fOSCH: High-frequency oscillator (24MHz on this board)
  60         #   - fPLL = fOSCH * multiplier (where multiplier can be 6 or 8)
  61         #   - fFCLK = fPLL / gear (where gear can be 1/2/4/8)
  62         #   - fHCLK is always fFCLK/2. fPCLK is also fFCLK/2.
  63         #
  64         # We select multiplier = 8 and gear = 1, so
  65         #   fFCLK = fOSCH * 8 / 1 = 192MHz.
  66
  67         # SYSCR3 (System Control Register 3): Disable and configure PLL.
  68         #   - PLL operation control: off
  69         #   - PLL constant value setting 1: always 0, as per datasheet
  70         #   - PLL constant value setting 2: x8 (multiplier = 8)
  71         mww 0xf005000c 0x00000007
  72
  73         # SYSCR4 (System Control Register 4): Configure PLL.
  74         #   - PLL constant value setting 3: 140MHz or more
  75         #   - PLL constant value setting 4: always 1, as per datasheet
  76         #   - PLL constant value setting 5: 140MHz or more
  77         mww 0xf0050010 0x00000065
  78
  79         # SYSCR3 (System Control Register 3): Enable PLL.
  80         #   - PLL operation control: on
  81         #   - All other bits remain set as above.
  82         mww 0xf005000c 0x00000087
  83
  84         # Wait for PLL to stabilize.
  85         sleep 10
  86
  87         # SYSCR2 (System Control Register 2): Switch from fOSCH to fPLL.
  88         #   - Selection of the PLL output clock: fPLL
  89         mww 0xf0050008 0x00000002
  90
  91         # SYSCR1 (System Control Register 1):
  92         #   - Clock gear programming: fc/1 (i.e., gear = 1, don't divide).
  93         mww 0xf0050004 0x00000000
  94
  95         # CLKCR5 (Clock Control Register 5): Set bits 3 and 6. The datasheet
  96         # says the bits are reserved, but also recommends "Write as one".
  97         mww 0xf0050054 0x00000048
  98
  99
 100         ##############################################################
 101         # Dynamic Memory Controller (DMC) / DDR SDRAM initialization #
 102         ##############################################################
 103
 104         # PMC (Power Management Controller):
 105         # PMCDRV (External Port "Driverbility" control register):
 106         # Bits DRV_MEM0/DRV_MEM1 (memory relation port drive power):
 107         mww 0xf0020260 0x00000003       ;# Select 1.8V +/- 0.1V
 108
 109         # Setup DDR SDRAM timing parameters for our specific chip.
 110         mww 0xf4310014 0x00000004       ;# cas_latency = 2
 111         mww 0xf4310018 0x00000001       ;# t_dqss = 1
 112         mww 0xf431001c 0x00000002       ;# t_mrd = 2
 113         mww 0xf4310020 0x0000000a       ;# t_ras = 10
 114         mww 0xf4310024 0x0000000a       ;# t_rc = 10
 115         mww 0xf4310028 0x00000013       ;# t_rcd = 3, schedule_rcd = 2
 116         mww 0xf431002c 0x0000010a       ;# t_rfc = 10, schedule_rfc = 8
 117         mww 0xf4310030 0x00000013       ;# t_rp = 3, schedule_rp = 2
 118         mww 0xf4310034 0x00000002       ;# t_rrd = 2
 119         mww 0xf4310038 0x00000002       ;# t_wr = 2
 120         mww 0xf431003c 0x00000001       ;# t_wtr = 1
 121         mww 0xf4310040 0x0000000a       ;# t_xp = 10
 122         mww 0xf4310044 0x0000000c       ;# t_xsr = 12
 123         mww 0xf4310048 0x00000014       ;# t_esr = 20
 124
 125         # dmc_memory_cfg_5 (DMC Memory Configuration register):
 126         # Set memory configuration:
 127         # column_bits = 10, row_bits = 13, ap-bit = 10, power_down_prd = 0,
 128         # auto_power_down = disable, stop_mem_clock = disable, memory_burst = 4
 129         mww 0xf431000c 0x00010012
 130
 131         # dmc_user_config_5 (DMC user_config register):
 132         # Data bus width of DDR SDRAM: 16 bit
 133         mww 0xf4310304 0x00000058
 134
 135         # dmc_refresh_prd_5 (DMC Refresh Period register):
 136         # Auto refresh: every 2656 (0xa60) DMCSCLK periods.
 137         mww 0xf4310010 0x00000a60
 138
 139         # dmc_chip_0_cfg_5 (DMC chip_0_cfg registers):
 140         #   - SDRAM address structure: bank, row, column
 141         #   - address_match = 01000000 (start address [31:24])
 142         #   - address_mask  = 11111100 (start address [31:24] mask value)
 143         mww 0xf4310200 0x000140fc
 144
 145         # Initialize the DDR SDRAM chip.
 146         # dmc_direct_cmd_5 (DMC Direct Command register).
 147         # See datasheet chapter 3.10.5.1, page 268.
 148         mww 0xf4310008 0x000c0000       ;# RAM init: NOP
 149         mww 0xf4310008 0x00000000       ;# RAM init: Precharge all
 150         mww 0xf4310008 0x00040000       ;# RAM init: Autorefresh
 151         mww 0xf4310008 0x00040000       ;# RAM init: Autorefresh
 152         mww 0xf4310008 0x00080032       ;# RAM init: addr_13_to_0 = 0x32
 153         mww 0xf4310008 0x000c0000       ;# RAM init: NOP
 154         mww 0xf4310008 0x000a0000       ;# RAM init: bank_addr = bank 2
 155
 156         # dmc_id_<0-5>_cfg_5 (DMC id_<0-5>_cfg registers):
 157         # Set min./max. QoS values.
 158         #   - 0x5: Enable QoS, max. QoS = 1
 159         #   - 0xb: Enable QoS, min. QoS = 2
 160         mww 0xf4310100 0x00000005       ;# AHB0: CPU Data
 161         mww 0xf4310104 0x00000005       ;# AHB1: CPU Inst
 162         mww 0xf4310108 0x0000000b       ;# AHB2: LCDC
 163         mww 0xf431010c 0x00000005       ;# AHB3: LCDDA, USB
 164         mww 0xf4310110 0x00000005       ;# AHB4: DMA1
 165         mww 0xf4310114 0x00000005       ;# AHB5: DMA2
 166
 167         # dmc_memc_cmd_5 (DMC Memory Controller Command register):
 168         # Change DMC state to ready.
 169         mww 0xf4310004 0x00000000       ;# memc_cmd = "Go"
 170
 171         # EBI: SMC Timeout register
 172         mww 0xf00a0050 0x00000001       ;# smc_timeout = 1
 173
 174
 175         ########################################################
 176         # Static Memory Controller (SMC) / SRAM initialization #
 177         ########################################################
 178
 179         # smc_set_cycles_5 (SMC Set Cycles register):
 180         # tRC = 10, tWC = 10, tCEOE = 7, tWP = 5, tPC=2, tTR=2
 181         mww 0xf4311014 0x0004afaa
 182
 183         # smc_set_opmode_5 (SMC Set Opmode register):
 184         # Memory data bus width = 16 bits, async read mode, read burst
 185         # length = 1 beat, async write mode, write burst length = 1 beat,
 186         # byte enable (SMCBE0-1) timing = SMCCSn timing, memory burst boundary
 187         # split setting = burst can cross any address boundary
 188         mww 0xf4311018 0x00000001
 189
 190         # smc_direct_cmd_5 (SMC Direct Command register):
 191         # cmd_type = UpdateRegs, chip_select = CS1
 192         mww 0xf4311010 0x00c00000
 193
 194         echo "Clocks, SRAM, and DDR SDRAM are now initialized."
 195 }
 196
 197 #######################
 198 # Flash configuration #
 199 #######################
 200
 201 # TODO: Implement NAND support.