tcl/board/at91cap7a-stk-sdram.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4394
   4 #
   5 # use combined on interfaces or targets that can't set TRST/SRST separately
   6 reset_config trst_and_srst srst_pulls_trst
   7
   8 if { [info exists CHIPNAME] } {
   9    set  _CHIPNAME $CHIPNAME
  10 } else {
  11    set  _CHIPNAME cap7
  12 }
  13
  14 if { [info exists ENDIAN] } {
  15    set  _ENDIAN $ENDIAN
  16 } else {
  17    set  _ENDIAN little
  18 }
  19
  20 if { [info exists CPUTAPID] } {
  21    set _CPUTAPID $CPUTAPID
  22 } else {
  23    set _CPUTAPID 0x40700f0f
  24 }
  25
  26 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
  27
  28 set _TARGETNAME $_CHIPNAME.cpu
  29 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
  30
  31 $_TARGETNAME configure -event reset-start {
  32         # start off real slow when we're running off internal RC oscillator
  33         adapter speed 32
  34 }
  35
  36 proc peek32 {address} {
  37         return [read_memory $address 32 1]
  38 }
  39
  40 # Wait for an expression to be true with a timeout
  41 proc wait_state {expression} {
  42         for {set i 0} {$i < 1000} {set i [expr {$i + 1}]} {
  43                 if {[uplevel 1 $expression] == 0} {
  44                         return
  45                 }
  46         }
  47         return -code 1 "Timed out"
  48 }
  49
  50 # Use a global variable here to be able to tinker interactively with
  51 # post reset jtag frequency.
  52 global post_reset_khz
  53 # Danger!!!! Even 16MHz kinda works with this target, but
  54 # it needs to be as low as 2000kHz to be stable.
  55 set post_reset_khz 2000
  56
  57 $_TARGETNAME configure -event reset-init {
  58         echo "Configuring master clock"
  59         # disable watchdog
  60         mww 0xfffffd44 0xff008000
  61         # enable user reset
  62         mww 0xfffffd08 0xa5000001
  63         # Enable main oscillator
  64         mww 0xFFFFFc20  0x00000f01
  65         wait_state {expr {([peek32 0xFFFFFC68] & 0x1) == 0}}
  66
  67         # Set PLLA to 96MHz
  68         mww 0xFFFFFc28 0x20072801
  69         wait_state {expr {([peek32 0xFFFFFC68] & 0x2) == 0}}
  70
  71         # Select prescaler
  72         mww 0xFFFFFC30 0x00000004
  73         wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
  74
  75         # Select master clock to 48MHz
  76         mww 0xFFFFFC30 0x00000006
  77         wait_state {expr {([peek32 0xFFFFFC68] & 0x8) == 0}}
  78
  79         echo "Master clock ok."
  80
  81         # Now that we're up and running, crank up speed!
  82         global post_reset_khz ; adapter speed $post_reset_khz
  83
  84         echo "Configuring the SDRAM controller..."
  85
  86         # Configure EBI Chip select for SDRAM
  87         mww 0xFFFFEF30 0x00000102
  88
  89         # Enable clock on EBI PIOs
  90         mww 0xFFFFFC10 0x00000004
  91
  92         # Configure PIO for SDRAM
  93         mww 0xFFFFF470 0xFFFF0000
  94         mww 0xFFFFF474 0x00000000
  95         mww 0xFFFFF404 0xFFFF0000
  96
  97         # Configure SDRAMC CR
  98         mww 0xFFFFEA08 0xA63392F9
  99
 100         # NOP command
 101         mww 0xFFFFEA00 0x1
 102         mww 0x20000000 0
 103
 104         # Precharge All Banks command
 105         mww 0xFFFFEA00 0x2
 106         mww 0x20000000 0
 107
 108         # Set 1st CBR
 109         mww 0xFFFFEA00 0x00000004
 110         mww 0x20000010 0x00000001
 111
 112         # Set 2nd CBR
 113         mww 0xFFFFEA00 0x00000004
 114         mww 0x20000020 0x00000002
 115
 116         # Set 3rd CBR
 117         mww 0xFFFFEA00 0x00000004
 118         mww 0x20000030 0x00000003
 119
 120         # Set 4th CBR
 121         mww 0xFFFFEA00 0x00000004
 122         mww 0x20000040 0x00000004
 123
 124         # Set 5th CBR
 125         mww 0xFFFFEA00 0x00000004
 126         mww 0x20000050 0x00000005
 127
 128         # Set 6th CBR
 129         mww 0xFFFFEA00 0x00000004
 130         mww 0x20000060 0x00000006
 131
 132         # Set 7th CBR
 133         mww 0xFFFFEA00 0x00000004
 134         mww 0x20000070 0x00000007
 135
 136         # Set 8th CBR
 137         mww 0xFFFFEA00 0x00000004
 138         mww 0x20000080 0x00000008
 139
 140         # Set LMR operation
 141         mww 0xFFFFEA00 0x00000003
 142
 143         # Perform LMR burst=1, lat=2
 144         mww 0x20000020 0xCAFEDEDE
 145
 146         # Set Refresh Timer
 147         mww 0xFFFFEA04 0x00000203
 148
 149         # Set Normal mode
 150         mww 0xFFFFEA00 0x00000000
 151         mww 0x20000000 0x00000000
 152
 153         #remap internal memory at address 0x0
 154         mww 0xffffef00 0x3
 155
 156         echo "SDRAM configuration ok."
 157 }
 158
 159 $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
 160
 161 arm7_9 dcc_downloads enable
 162 arm7_9 fast_memory_access enable
 163
 164 #set _FLASHNAME $_CHIPNAME.flash
 165 #flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432