src/target/target/wi-9c.cfg

   1 ######################################
   2 # Target: DIGI ConnectCore Wi-9C
   3 ######################################
   4
   5 reset_config trst_and_srst
   6
   7 # What's a good fallback frequency for this board if RCLK is
   8 # not available??
   9 jtag_rclk 1000
  10
  11 #jtag_device <IR length> <IR capture> <IR mask> <IDCODE instruction>
  12 jtag_device 4 0x1 0xf 0xe
  13
  14 jtag_nsrst_delay 200
  15 jtag_ntrst_delay 0
  16
  17
  18 ######################
  19 # Target configuration
  20 ######################
  21
  22 target create target0 arm926ejs -endian big -chain-position 0 -variant arm926ejs
  23 [new_target_name] configure -event reset-init {
  24         mww 0x90600104 0x33313333
  25         mww 0xA0700000 0x00000001  # Enable the memory controller.
  26         mww 0xA0700024 0x00000006  # Set the refresh counter 6
  27         mww 0xA0700028 0x00000001  #
  28         mww 0xA0700030 0x00000001  # Set the precharge period
  29         mww 0xA0700034 0x00000004  # Active to precharge command period is 16 clock cycles
  30         mww 0xA070003C 0x00000001  # tAPR
  31         mww 0xA0700040 0x00000005  # tDAL
  32         mww 0xA0700044 0x00000001  # tWR
  33         mww 0xA0700048 0x00000006  # tRC 32 clock cycles
  34         mww 0xA070004C 0x00000006  # tRFC 32 clock cycles
  35         mww 0xA0700054 0x00000001  # tRRD
  36         mww 0xA0700058 0x00000001  # tMRD
  37         mww 0xA0700100 0x00004280  # Dynamic Config 0 (cs4)
  38         mww 0xA0700120 0x00004280  # Dynamic Config 1 (cs5)
  39         mww 0xA0700140 0x00004280  # Dynamic Config 2 (cs6)
  40         mww 0xA0700160 0x00004280  # Dynamic Config 3 (cs7)
  41         #
  42         mww 0xA0700104 0x00000203  # CAS latency is 2 at 100 MHz
  43         mww 0xA0700124 0x00000203  # CAS latency is 2 at 100 MHz
  44         mww 0xA0700144 0x00000203  # CAS latency is 2 at 100 MHz
  45         mww 0xA0700164 0x00000203  # CAS latency is 2 at 100 MHz
  46         #
  47         mww 0xA0700020 0x00000103  # issue SDRAM PALL command
  48         #
  49         mww 0xA0700024 0x00000001  # Set the refresh counter to be as small as possible
  50         #
  51         # Add some dummy writes to give the SDRAM time to settle, it needs two
  52         # AHB clock cycles, here we poke in the debugger flag, this lets
  53         # the software know that we are in the debugger
  54         mww 0xA0900000 0x00000002
  55         mww 0xA0900000 0x00000002
  56         mww 0xA0900000 0x00000002
  57         mww 0xA0900000 0x00000002
  58         mww 0xA0900000 0x00000002
  59         #
  60         mdw 0xA0900000
  61         mdw 0xA0900000
  62         mdw 0xA0900000
  63         mdw 0xA0900000
  64         mdw 0xA0900000
  65         #
  66         mww 0xA0700024 0x00000030 # Set the refresh counter to 30
  67         mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
  68         #
  69         # Next we perform a read of RAM.
  70         # mw = move word.
  71         mdw 0x00022000
  72         # mw 0x00022000:P, r3  # 22000 for cas2 latency, 32000 for cas 3
  73         #
  74         mww 0xA0700020 0x00000003   # issue SDRAM NORMAL command
  75         mww 0xA0700100 0x00084280   # Enable buffer access
  76         mww 0xA0700120 0x00084280   # Enable buffer access
  77         mww 0xA0700140 0x00084280   # Enable buffer access
  78         mww 0xA0700160 0x00084280   # Enable buffer access
  79
  80         #Set byte lane state (static mem 1)"
  81         mww 0xA0700220, 0x00000082
  82         #Flash Start
  83         mww 0xA09001F8, 0x50000000
  84         #Flash Mask Reg
  85         mww 0xA09001FC, 0xFF000001
  86         mww 0xA0700028, 0x00000001
  87
  88         #  RAMAddr = 0x00020000
  89         #  RAMSize = 0x00004000
  90
  91         # Set the processor mode
  92         reg cpsr 0xd3
  93 }
  94
  95 [new_target_name] configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
  96
  97 #####################
  98 # Flash configuration
  99 #####################
 100
 101 #M29DW323DB - not working
 102 #flash bank cfi <base> <size> <chip width> <bus width> <target#>
 103 flash bank cfi 0x50000000 0x0400000 2 2 0
 104
 105
 106