1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
25 #include <helper/command.h>
27 #include "nds32_aice.h"
28 #include "nds32_disassembler.h"
30 extern struct nds32_edm_operation nds32_edm_ops
[NDS32_EDM_OPERATION_MAX_NUM
];
31 extern uint32_t nds32_edm_ops_num
;
33 static const char *const NDS_MEMORY_ACCESS_NAME
[] = {
38 static const char *const NDS_MEMORY_SELECT_NAME
[] = {
45 COMMAND_HANDLER(handle_nds32_dssim_command
)
47 struct target
*target
= get_current_target(CMD_CTX
);
48 struct nds32
*nds32
= target_to_nds32(target
);
50 if (!is_nds32(nds32
)) {
51 command_print(CMD_CTX
, "current target isn't an Andes core");
56 if (strcmp(CMD_ARGV
[0], "on") == 0)
57 nds32
->step_isr_enable
= true;
58 if (strcmp(CMD_ARGV
[0], "off") == 0)
59 nds32
->step_isr_enable
= false;
62 command_print(CMD_CTX
, "%s: $INT_MASK.DSSIM: %d", target_name(target
),
63 nds32
->step_isr_enable
);
68 COMMAND_HANDLER(handle_nds32_memory_access_command
)
70 struct target
*target
= get_current_target(CMD_CTX
);
71 struct nds32
*nds32
= target_to_nds32(target
);
72 struct aice_port_s
*aice
= target_to_aice(target
);
73 struct nds32_memory
*memory
= &(nds32
->memory
);
75 if (!is_nds32(nds32
)) {
76 command_print(CMD_CTX
, "current target isn't an Andes core");
81 if (strcmp(CMD_ARGV
[0], "bus") == 0)
82 memory
->access_channel
= NDS_MEMORY_ACC_BUS
;
83 else if (strcmp(CMD_ARGV
[0], "cpu") == 0)
84 memory
->access_channel
= NDS_MEMORY_ACC_CPU
;
85 else /* default access channel is NDS_MEMORY_ACC_CPU */
86 memory
->access_channel
= NDS_MEMORY_ACC_CPU
;
88 LOG_DEBUG("memory access channel is changed to %s",
89 NDS_MEMORY_ACCESS_NAME
[memory
->access_channel
]);
91 aice_memory_access(aice
, memory
->access_channel
);
93 command_print(CMD_CTX
, "%s: memory access channel: %s",
95 NDS_MEMORY_ACCESS_NAME
[memory
->access_channel
]);
101 COMMAND_HANDLER(handle_nds32_memory_mode_command
)
103 struct target
*target
= get_current_target(CMD_CTX
);
104 struct nds32
*nds32
= target_to_nds32(target
);
105 struct aice_port_s
*aice
= target_to_aice(target
);
107 if (!is_nds32(nds32
)) {
108 command_print(CMD_CTX
, "current target isn't an Andes core");
114 if (nds32
->edm
.access_control
== false) {
115 command_print(CMD_CTX
, "%s does not support ACC_CTL. "
116 "Set memory mode to MEMORY", target_name(target
));
117 nds32
->memory
.mode
= NDS_MEMORY_SELECT_MEM
;
118 } else if (nds32
->edm
.direct_access_local_memory
== false) {
119 command_print(CMD_CTX
, "%s does not support direct access "
120 "local memory. Set memory mode to MEMORY",
121 target_name(target
));
122 nds32
->memory
.mode
= NDS_MEMORY_SELECT_MEM
;
125 aice_memory_mode(aice
, nds32
->memory
.mode
);
127 if (strcmp(CMD_ARGV
[0], "auto") == 0) {
128 nds32
->memory
.mode
= NDS_MEMORY_SELECT_AUTO
;
129 } else if (strcmp(CMD_ARGV
[0], "mem") == 0) {
130 nds32
->memory
.mode
= NDS_MEMORY_SELECT_MEM
;
131 } else if (strcmp(CMD_ARGV
[0], "ilm") == 0) {
132 if (nds32
->memory
.ilm_base
== 0)
133 command_print(CMD_CTX
, "%s does not support ILM",
134 target_name(target
));
136 nds32
->memory
.mode
= NDS_MEMORY_SELECT_ILM
;
137 } else if (strcmp(CMD_ARGV
[0], "dlm") == 0) {
138 if (nds32
->memory
.dlm_base
== 0)
139 command_print(CMD_CTX
, "%s does not support DLM",
140 target_name(target
));
142 nds32
->memory
.mode
= NDS_MEMORY_SELECT_DLM
;
146 aice_memory_mode(aice
, nds32
->memory
.mode
);
150 command_print(CMD_CTX
, "%s: memory mode: %s",
152 NDS_MEMORY_SELECT_NAME
[nds32
->memory
.mode
]);
157 COMMAND_HANDLER(handle_nds32_cache_command
)
159 struct target
*target
= get_current_target(CMD_CTX
);
160 struct nds32
*nds32
= target_to_nds32(target
);
161 struct aice_port_s
*aice
= target_to_aice(target
);
162 struct nds32_cache
*icache
= &(nds32
->memory
.icache
);
163 struct nds32_cache
*dcache
= &(nds32
->memory
.dcache
);
166 if (!is_nds32(nds32
)) {
167 command_print(CMD_CTX
, "current target isn't an Andes core");
173 if (strcmp(CMD_ARGV
[0], "invalidate") == 0) {
174 if ((dcache
->line_size
!= 0) && (dcache
->enable
== true)) {
176 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_WBALL
, 0);
177 if (result
!= ERROR_OK
) {
178 command_print(CMD_CTX
, "%s: Write back data cache...failed",
179 target_name(target
));
183 command_print(CMD_CTX
, "%s: Write back data cache...done",
184 target_name(target
));
187 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_INVALALL
, 0);
188 if (result
!= ERROR_OK
) {
189 command_print(CMD_CTX
, "%s: Invalidate data cache...failed",
190 target_name(target
));
194 command_print(CMD_CTX
, "%s: Invalidate data cache...done",
195 target_name(target
));
197 if (dcache
->line_size
== 0)
198 command_print(CMD_CTX
, "%s: No data cache",
199 target_name(target
));
201 command_print(CMD_CTX
, "%s: Data cache disabled",
202 target_name(target
));
205 if ((icache
->line_size
!= 0) && (icache
->enable
== true)) {
207 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1I_INVALALL
, 0);
208 if (result
!= ERROR_OK
) {
209 command_print(CMD_CTX
, "%s: Invalidate instruction cache...failed",
210 target_name(target
));
214 command_print(CMD_CTX
, "%s: Invalidate instruction cache...done",
215 target_name(target
));
217 if (icache
->line_size
== 0)
218 command_print(CMD_CTX
, "%s: No instruction cache",
219 target_name(target
));
221 command_print(CMD_CTX
, "%s: Instruction cache disabled",
222 target_name(target
));
225 command_print(CMD_CTX
, "No valid parameter");
231 COMMAND_HANDLER(handle_nds32_icache_command
)
233 struct target
*target
= get_current_target(CMD_CTX
);
234 struct nds32
*nds32
= target_to_nds32(target
);
235 struct aice_port_s
*aice
= target_to_aice(target
);
236 struct nds32_cache
*icache
= &(nds32
->memory
.icache
);
239 if (!is_nds32(nds32
)) {
240 command_print(CMD_CTX
, "current target isn't an Andes core");
246 if (icache
->line_size
== 0) {
247 command_print(CMD_CTX
, "%s: No instruction cache",
248 target_name(target
));
252 if (strcmp(CMD_ARGV
[0], "invalidate") == 0) {
253 if (icache
->enable
== true) {
255 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1I_INVALALL
, 0);
256 if (result
!= ERROR_OK
) {
257 command_print(CMD_CTX
, "%s: Invalidate instruction cache...failed",
258 target_name(target
));
262 command_print(CMD_CTX
, "%s: Invalidate instruction cache...done",
263 target_name(target
));
265 command_print(CMD_CTX
, "%s: Instruction cache disabled",
266 target_name(target
));
268 } else if (strcmp(CMD_ARGV
[0], "enable") == 0) {
270 nds32_get_mapped_reg(nds32
, IR8
, &value
);
271 nds32_set_mapped_reg(nds32
, IR8
, value
| 0x1);
272 } else if (strcmp(CMD_ARGV
[0], "disable") == 0) {
274 nds32_get_mapped_reg(nds32
, IR8
, &value
);
275 nds32_set_mapped_reg(nds32
, IR8
, value
& ~0x1);
276 } else if (strcmp(CMD_ARGV
[0], "dump") == 0) {
277 /* TODO: dump cache content */
279 command_print(CMD_CTX
, "%s: No valid parameter", target_name(target
));
286 COMMAND_HANDLER(handle_nds32_dcache_command
)
288 struct target
*target
= get_current_target(CMD_CTX
);
289 struct nds32
*nds32
= target_to_nds32(target
);
290 struct aice_port_s
*aice
= target_to_aice(target
);
291 struct nds32_cache
*dcache
= &(nds32
->memory
.dcache
);
294 if (!is_nds32(nds32
)) {
295 command_print(CMD_CTX
, "current target isn't an Andes core");
301 if (dcache
->line_size
== 0) {
302 command_print(CMD_CTX
, "%s: No data cache", target_name(target
));
306 if (strcmp(CMD_ARGV
[0], "invalidate") == 0) {
307 if (dcache
->enable
== true) {
309 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_WBALL
, 0);
310 if (result
!= ERROR_OK
) {
311 command_print(CMD_CTX
, "%s: Write back data cache...failed",
312 target_name(target
));
316 command_print(CMD_CTX
, "%s: Write back data cache...done",
317 target_name(target
));
320 result
= aice_cache_ctl(aice
, AICE_CACHE_CTL_L1D_INVALALL
, 0);
321 if (result
!= ERROR_OK
) {
322 command_print(CMD_CTX
, "%s: Invalidate data cache...failed",
323 target_name(target
));
327 command_print(CMD_CTX
, "%s: Invalidate data cache...done",
328 target_name(target
));
330 command_print(CMD_CTX
, "%s: Data cache disabled",
331 target_name(target
));
333 } else if (strcmp(CMD_ARGV
[0], "enable") == 0) {
335 nds32_get_mapped_reg(nds32
, IR8
, &value
);
336 nds32_set_mapped_reg(nds32
, IR8
, value
| 0x2);
337 } else if (strcmp(CMD_ARGV
[0], "disable") == 0) {
339 nds32_get_mapped_reg(nds32
, IR8
, &value
);
340 nds32_set_mapped_reg(nds32
, IR8
, value
& ~0x2);
341 } else if (strcmp(CMD_ARGV
[0], "dump") == 0) {
342 /* TODO: dump cache content */
344 command_print(CMD_CTX
, "%s: No valid parameter", target_name(target
));
351 COMMAND_HANDLER(handle_nds32_auto_break_command
)
353 struct target
*target
= get_current_target(CMD_CTX
);
354 struct nds32
*nds32
= target_to_nds32(target
);
356 if (!is_nds32(nds32
)) {
357 command_print(CMD_CTX
, "current target isn't an Andes core");
362 if (strcmp(CMD_ARGV
[0], "on") == 0)
363 nds32
->auto_convert_hw_bp
= true;
364 if (strcmp(CMD_ARGV
[0], "off") == 0)
365 nds32
->auto_convert_hw_bp
= false;
368 if (nds32
->auto_convert_hw_bp
)
369 command_print(CMD_CTX
, "%s: convert sw break to hw break on ROM: on",
370 target_name(target
));
372 command_print(CMD_CTX
, "%s: convert sw break to hw break on ROM: off",
373 target_name(target
));
378 COMMAND_HANDLER(handle_nds32_virtual_hosting_command
)
380 struct target
*target
= get_current_target(CMD_CTX
);
381 struct nds32
*nds32
= target_to_nds32(target
);
383 if (!is_nds32(nds32
)) {
384 command_print(CMD_CTX
, "current target isn't an Andes core");
389 if (strcmp(CMD_ARGV
[0], "on") == 0)
390 nds32
->virtual_hosting
= true;
391 if (strcmp(CMD_ARGV
[0], "off") == 0)
392 nds32
->virtual_hosting
= false;
395 if (nds32
->virtual_hosting
)
396 command_print(CMD_CTX
, "%s: virtual hosting: on", target_name(target
));
398 command_print(CMD_CTX
, "%s: virtual hosting: off", target_name(target
));
403 COMMAND_HANDLER(handle_nds32_global_stop_command
)
405 struct target
*target
= get_current_target(CMD_CTX
);
406 struct nds32
*nds32
= target_to_nds32(target
);
408 if (!is_nds32(nds32
)) {
409 command_print(CMD_CTX
, "current target isn't an Andes core");
414 if (strcmp(CMD_ARGV
[0], "on") == 0)
415 nds32
->global_stop
= true;
416 if (strcmp(CMD_ARGV
[0], "off") == 0)
417 nds32
->global_stop
= false;
420 if (nds32
->global_stop
)
421 LOG_INFO("%s: global stop: on", target_name(target
));
423 LOG_INFO("%s: global stop: off", target_name(target
));
428 COMMAND_HANDLER(handle_nds32_soft_reset_halt_command
)
430 struct target
*target
= get_current_target(CMD_CTX
);
431 struct nds32
*nds32
= target_to_nds32(target
);
433 if (!is_nds32(nds32
)) {
434 command_print(CMD_CTX
, "current target isn't an Andes core");
439 if (strcmp(CMD_ARGV
[0], "on") == 0)
440 nds32
->soft_reset_halt
= true;
441 if (strcmp(CMD_ARGV
[0], "off") == 0)
442 nds32
->soft_reset_halt
= false;
445 if (nds32
->soft_reset_halt
)
446 LOG_INFO("%s: soft-reset-halt: on", target_name(target
));
448 LOG_INFO("%s: soft-reset-halt: off", target_name(target
));
453 COMMAND_HANDLER(handle_nds32_boot_time_command
)
455 struct target
*target
= get_current_target(CMD_CTX
);
456 struct nds32
*nds32
= target_to_nds32(target
);
458 if (!is_nds32(nds32
)) {
459 command_print(CMD_CTX
, "current target isn't an Andes core");
464 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], nds32
->boot_time
);
469 COMMAND_HANDLER(handle_nds32_login_edm_passcode_command
)
471 struct target
*target
= get_current_target(CMD_CTX
);
472 struct nds32
*nds32
= target_to_nds32(target
);
474 if (!is_nds32(nds32
)) {
475 command_print(CMD_CTX
, "current target isn't an Andes core");
479 nds32
->edm_passcode
= strdup(CMD_ARGV
[0]);
484 COMMAND_HANDLER(handle_nds32_login_edm_operation_command
)
486 struct target
*target
= get_current_target(CMD_CTX
);
487 struct nds32
*nds32
= target_to_nds32(target
);
489 if (!is_nds32(nds32
)) {
490 command_print(CMD_CTX
, "current target isn't an Andes core");
496 uint32_t misc_reg_no
;
499 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], misc_reg_no
);
500 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], data
);
502 if (nds32_edm_ops_num
>= NDS32_EDM_OPERATION_MAX_NUM
)
505 /* Just save the operation. Execute it in nds32_login() */
506 nds32_edm_ops
[nds32_edm_ops_num
].reg_no
= misc_reg_no
;
507 nds32_edm_ops
[nds32_edm_ops_num
].value
= data
;
515 COMMAND_HANDLER(handle_nds32_reset_halt_as_init_command
)
517 struct target
*target
= get_current_target(CMD_CTX
);
518 struct nds32
*nds32
= target_to_nds32(target
);
520 if (!is_nds32(nds32
)) {
521 command_print(CMD_CTX
, "current target isn't an Andes core");
526 if (strcmp(CMD_ARGV
[0], "on") == 0)
527 nds32
->reset_halt_as_examine
= true;
528 if (strcmp(CMD_ARGV
[0], "off") == 0)
529 nds32
->reset_halt_as_examine
= false;
535 COMMAND_HANDLER(handle_nds32_keep_target_edm_ctl_command
)
537 struct target
*target
= get_current_target(CMD_CTX
);
538 struct nds32
*nds32
= target_to_nds32(target
);
540 if (!is_nds32(nds32
)) {
541 command_print(CMD_CTX
, "current target isn't an Andes core");
546 if (strcmp(CMD_ARGV
[0], "on") == 0)
547 nds32
->keep_target_edm_ctl
= true;
548 if (strcmp(CMD_ARGV
[0], "off") == 0)
549 nds32
->keep_target_edm_ctl
= false;
555 COMMAND_HANDLER(handle_nds32_decode_command
)
557 struct target
*target
= get_current_target(CMD_CTX
);
558 struct nds32
*nds32
= target_to_nds32(target
);
560 if (!is_nds32(nds32
)) {
561 command_print(CMD_CTX
, "current target isn't an Andes core");
572 struct nds32_instruction instruction
;
574 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], addr
);
575 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], insn_count
);
579 while (i
< insn_count
) {
580 if (ERROR_OK
!= nds32_read_opcode(nds32
, read_addr
, &opcode
))
582 if (ERROR_OK
!= nds32_evaluate_opcode(nds32
, opcode
,
583 read_addr
, &instruction
))
586 command_print(CMD_CTX
, "%s", instruction
.text
);
588 read_addr
+= instruction
.instruction_size
;
591 } else if (CMD_ARGC
== 1) {
595 struct nds32_instruction instruction
;
597 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], addr
);
599 if (ERROR_OK
!= nds32_read_opcode(nds32
, addr
, &opcode
))
601 if (ERROR_OK
!= nds32_evaluate_opcode(nds32
, opcode
, addr
, &instruction
))
604 command_print(CMD_CTX
, "%s", instruction
.text
);
611 COMMAND_HANDLER(handle_nds32_word_access_mem_command
)
613 struct target
*target
= get_current_target(CMD_CTX
);
614 struct nds32
*nds32
= target_to_nds32(target
);
616 if (!is_nds32(nds32
)) {
617 command_print(CMD_CTX
, "current target isn't an Andes core");
622 if (strcmp(CMD_ARGV
[0], "on") == 0)
623 nds32
->word_access_mem
= true;
624 if (strcmp(CMD_ARGV
[0], "off") == 0)
625 nds32
->word_access_mem
= false;
631 COMMAND_HANDLER(handle_nds32_query_target_command
)
633 struct target
*target
= get_current_target(CMD_CTX
);
634 struct nds32
*nds32
= target_to_nds32(target
);
636 if (!is_nds32(nds32
)) {
637 command_print(CMD_CTX
, "current target isn't an Andes core");
641 command_print(CMD_CTX
, "OCD");
646 COMMAND_HANDLER(handle_nds32_query_endian_command
)
648 struct target
*target
= get_current_target(CMD_CTX
);
649 struct nds32
*nds32
= target_to_nds32(target
);
651 if (!is_nds32(nds32
)) {
652 command_print(CMD_CTX
, "current target isn't an Andes core");
657 nds32_get_mapped_reg(nds32
, IR0
, &value_psw
);
659 if (value_psw
& 0x20)
660 command_print(CMD_CTX
, "%s: BE", target_name(target
));
662 command_print(CMD_CTX
, "%s: LE", target_name(target
));
667 COMMAND_HANDLER(handle_nds32_query_cpuid_command
)
669 struct target
*target
= get_current_target(CMD_CTX
);
670 struct nds32
*nds32
= target_to_nds32(target
);
672 if (!is_nds32(nds32
)) {
673 command_print(CMD_CTX
, "current target isn't an Andes core");
677 command_print(CMD_CTX
, "CPUID: %s", target_name(target
));
682 static int jim_nds32_bulk_write(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
684 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
687 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
690 Jim_SetResultFormatted(goi
.interp
,
691 "usage: %s <address> <count> <data>", cmd_name
);
697 e
= Jim_GetOpt_Wide(&goi
, &address
);
702 e
= Jim_GetOpt_Wide(&goi
, &count
);
706 uint32_t *data
= malloc(count
* sizeof(uint32_t));
711 for (i
= 0; i
< count
; i
++) {
713 e
= Jim_GetOpt_Wide(&goi
, &tmp
);
718 data
[i
] = (uint32_t)tmp
;
721 /* all args must be consumed */
727 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
730 result
= target_write_buffer(target
, address
, count
* 4, (const uint8_t *)data
);
737 static int jim_nds32_multi_write(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
739 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
742 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
745 Jim_SetResultFormatted(goi
.interp
,
746 "usage: %s # of pairs [<address> <data>]+", cmd_name
);
751 jim_wide num_of_pairs
;
752 e
= Jim_GetOpt_Wide(&goi
, &num_of_pairs
);
756 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
757 struct aice_port_s
*aice
= target_to_aice(target
);
763 aice_set_command_mode(aice
, AICE_COMMAND_MODE_PACK
);
764 for (i
= 0; i
< num_of_pairs
; i
++) {
766 e
= Jim_GetOpt_Wide(&goi
, &tmp
);
769 address
= (uint32_t)tmp
;
771 e
= Jim_GetOpt_Wide(&goi
, &tmp
);
774 data
= (uint32_t)tmp
;
776 result
= target_write_buffer(target
, address
, 4, (const uint8_t *)&data
);
777 if (result
!= ERROR_OK
)
780 aice_set_command_mode(aice
, AICE_COMMAND_MODE_NORMAL
);
782 /* all args must be consumed */
789 static int jim_nds32_bulk_read(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
791 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
794 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
797 Jim_SetResultFormatted(goi
.interp
,
798 "usage: %s <address> <count>", cmd_name
);
804 e
= Jim_GetOpt_Wide(&goi
, &address
);
809 e
= Jim_GetOpt_Wide(&goi
, &count
);
813 /* all args must be consumed */
817 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
818 uint32_t *data
= malloc(count
* sizeof(uint32_t));
820 result
= target_read_buffer(target
, address
, count
* 4, (uint8_t *)data
);
824 Jim_SetResult(interp
, Jim_NewEmptyStringObj(interp
));
825 for (i
= 0; i
< count
; i
++) {
826 sprintf(data_str
, "0x%08" PRIx32
" ", data
[i
]);
827 Jim_AppendStrings(interp
, Jim_GetResult(interp
), data_str
, NULL
);
835 static int jim_nds32_read_edm_sr(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
837 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
840 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
843 Jim_SetResultFormatted(goi
.interp
,
844 "usage: %s <edm_sr_name>", cmd_name
);
851 e
= Jim_GetOpt_String(&goi
, &edm_sr_name
, &edm_sr_name_len
);
855 /* all args must be consumed */
859 uint32_t edm_sr_number
;
860 uint32_t edm_sr_value
;
861 if (strncmp(edm_sr_name
, "edm_dtr", edm_sr_name_len
) == 0)
862 edm_sr_number
= NDS_EDM_SR_EDM_DTR
;
863 else if (strncmp(edm_sr_name
, "edmsw", edm_sr_name_len
) == 0)
864 edm_sr_number
= NDS_EDM_SR_EDMSW
;
868 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
869 struct aice_port_s
*aice
= target_to_aice(target
);
872 aice_read_debug_reg(aice
, edm_sr_number
, &edm_sr_value
);
874 sprintf(data_str
, "0x%08" PRIx32
, edm_sr_value
);
875 Jim_SetResult(interp
, Jim_NewEmptyStringObj(interp
));
876 Jim_AppendStrings(interp
, Jim_GetResult(interp
), data_str
, NULL
);
881 static int jim_nds32_write_edm_sr(Jim_Interp
*interp
, int argc
, Jim_Obj
* const *argv
)
883 const char *cmd_name
= Jim_GetString(argv
[0], NULL
);
886 Jim_GetOpt_Setup(&goi
, interp
, argc
- 1, argv
+ 1);
889 Jim_SetResultFormatted(goi
.interp
,
890 "usage: %s <edm_sr_name> <value>", cmd_name
);
897 e
= Jim_GetOpt_String(&goi
, &edm_sr_name
, &edm_sr_name_len
);
902 e
= Jim_GetOpt_Wide(&goi
, &value
);
906 /* all args must be consumed */
910 uint32_t edm_sr_number
;
911 if (strncmp(edm_sr_name
, "edm_dtr", edm_sr_name_len
) == 0)
912 edm_sr_number
= NDS_EDM_SR_EDM_DTR
;
916 struct target
*target
= Jim_CmdPrivData(goi
.interp
);
917 struct aice_port_s
*aice
= target_to_aice(target
);
919 aice_write_debug_reg(aice
, edm_sr_number
, value
);
924 static const struct command_registration nds32_query_command_handlers
[] = {
927 .handler
= handle_nds32_query_target_command
,
928 .mode
= COMMAND_EXEC
,
930 .help
= "reply 'OCD' for gdb to identify server-side is OpenOCD",
934 .handler
= handle_nds32_query_endian_command
,
935 .mode
= COMMAND_EXEC
,
937 .help
= "query target endian",
941 .handler
= handle_nds32_query_cpuid_command
,
942 .mode
= COMMAND_EXEC
,
944 .help
= "query CPU ID",
947 COMMAND_REGISTRATION_DONE
950 static const struct command_registration nds32_exec_command_handlers
[] = {
953 .handler
= handle_nds32_dssim_command
,
954 .mode
= COMMAND_EXEC
,
955 .usage
= "['on'|'off']",
956 .help
= "display/change $INT_MASK.DSSIM status",
959 .name
= "mem_access",
960 .handler
= handle_nds32_memory_access_command
,
961 .mode
= COMMAND_EXEC
,
962 .usage
= "['bus'|'cpu']",
963 .help
= "display/change memory access channel",
967 .handler
= handle_nds32_memory_mode_command
,
968 .mode
= COMMAND_EXEC
,
969 .usage
= "['auto'|'mem'|'ilm'|'dlm']",
970 .help
= "display/change memory mode",
974 .handler
= handle_nds32_cache_command
,
975 .mode
= COMMAND_EXEC
,
976 .usage
= "['invalidate']",
977 .help
= "cache control",
981 .handler
= handle_nds32_icache_command
,
982 .mode
= COMMAND_EXEC
,
983 .usage
= "['invalidate'|'enable'|'disable'|'dump']",
984 .help
= "icache control",
988 .handler
= handle_nds32_dcache_command
,
989 .mode
= COMMAND_EXEC
,
990 .usage
= "['invalidate'|'enable'|'disable'|'dump']",
991 .help
= "dcache control",
994 .name
= "auto_break",
995 .handler
= handle_nds32_auto_break_command
,
996 .mode
= COMMAND_EXEC
,
997 .usage
= "['on'|'off']",
998 .help
= "convert software breakpoints to hardware breakpoints if needed",
1001 .name
= "virtual_hosting",
1002 .handler
= handle_nds32_virtual_hosting_command
,
1003 .mode
= COMMAND_ANY
,
1004 .usage
= "['on'|'off']",
1005 .help
= "turn on/off virtual hosting",
1008 .name
= "global_stop",
1009 .handler
= handle_nds32_global_stop_command
,
1010 .mode
= COMMAND_ANY
,
1011 .usage
= "['on'|'off']",
1012 .help
= "turn on/off global stop. After turning on, every load/store" \
1013 "instructions will be stopped to check memory access.",
1016 .name
= "soft_reset_halt",
1017 .handler
= handle_nds32_soft_reset_halt_command
,
1018 .mode
= COMMAND_ANY
,
1019 .usage
= "['on'|'off']",
1020 .help
= "as issuing rest-halt, to use soft-reset-halt or not." \
1021 "the feature is for backward-compatible.",
1024 .name
= "boot_time",
1025 .handler
= handle_nds32_boot_time_command
,
1026 .mode
= COMMAND_CONFIG
,
1027 .usage
= "milliseconds",
1028 .help
= "set the period to wait after srst.",
1031 .name
= "login_edm_passcode",
1032 .handler
= handle_nds32_login_edm_passcode_command
,
1033 .mode
= COMMAND_CONFIG
,
1034 .usage
= "passcode",
1035 .help
= "set EDM passcode for secure MCU debugging.",
1038 .name
= "login_edm_operation",
1039 .handler
= handle_nds32_login_edm_operation_command
,
1040 .mode
= COMMAND_CONFIG
,
1041 .usage
= "login_edm_operation misc_reg_no value",
1042 .help
= "add EDM operations for secure MCU debugging.",
1045 .name
= "reset_halt_as_init",
1046 .handler
= handle_nds32_reset_halt_as_init_command
,
1047 .mode
= COMMAND_CONFIG
,
1048 .usage
= "['on'|'off']",
1049 .help
= "reset halt as openocd init.",
1052 .name
= "keep_target_edm_ctl",
1053 .handler
= handle_nds32_keep_target_edm_ctl_command
,
1054 .mode
= COMMAND_CONFIG
,
1055 .usage
= "['on'|'off']",
1056 .help
= "Backup/Restore target EDM_CTL register.",
1060 .handler
= handle_nds32_decode_command
,
1061 .mode
= COMMAND_EXEC
,
1062 .usage
= "address icount",
1063 .help
= "decode instruction.",
1066 .name
= "word_access_mem",
1067 .handler
= handle_nds32_word_access_mem_command
,
1068 .mode
= COMMAND_ANY
,
1069 .usage
= "['on'|'off']",
1070 .help
= "Always use word-aligned address to access memory.",
1073 .name
= "bulk_write",
1074 .jim_handler
= jim_nds32_bulk_write
,
1075 .mode
= COMMAND_EXEC
,
1076 .help
= "Write multiple 32-bit words to target memory",
1077 .usage
= "address count data",
1080 .name
= "multi_write",
1081 .jim_handler
= jim_nds32_multi_write
,
1082 .mode
= COMMAND_EXEC
,
1083 .help
= "Write multiple addresses/words to target memory",
1084 .usage
= "num_of_pairs [address data]+",
1087 .name
= "bulk_read",
1088 .jim_handler
= jim_nds32_bulk_read
,
1089 .mode
= COMMAND_EXEC
,
1090 .help
= "Read multiple 32-bit words from target memory",
1091 .usage
= "address count",
1094 .name
= "read_edmsr",
1095 .jim_handler
= jim_nds32_read_edm_sr
,
1096 .mode
= COMMAND_EXEC
,
1097 .help
= "Read EDM system register",
1098 .usage
= "['edmsw'|'edm_dtr']",
1101 .name
= "write_edmsr",
1102 .jim_handler
= jim_nds32_write_edm_sr
,
1103 .mode
= COMMAND_EXEC
,
1104 .help
= "Write EDM system register",
1105 .usage
= "['edm_dtr'] value",
1109 .mode
= COMMAND_EXEC
,
1110 .help
= "Andes query command group",
1112 .chain
= nds32_query_command_handlers
,
1115 COMMAND_REGISTRATION_DONE
1118 const struct command_registration nds32_command_handlers
[] = {
1121 .mode
= COMMAND_ANY
,
1122 .help
= "Andes command group",
1124 .chain
= nds32_exec_command_handlers
,
1126 COMMAND_REGISTRATION_DONE
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