1 /***************************************************************************
2 * Copyright (C) 2013 Andes Technology *
3 * Hsiangkai Wang <hkwang@andestech.com> *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
24 #include <jtag/jtag.h>
26 #include "target_type.h"
28 #include "breakpoints.h"
29 #include "nds32_reg.h"
30 #include "nds32_insn.h"
31 #include "nds32_edm.h"
33 #define NDS32_EDM_OPERATION_MAX_NUM 64
35 #define CHECK_RETVAL(action) \
37 int __retval = (action); \
38 if (__retval != ERROR_OK) { \
39 LOG_DEBUG("error while calling \"%s\"", \
47 * Holds the interface to Andes cores.
50 extern const char *nds32_debug_type_name
[11];
52 enum nds32_debug_reason
{
53 NDS32_DEBUG_BREAK
= 0,
55 NDS32_DEBUG_INST_BREAK
,
56 NDS32_DEBUG_DATA_ADDR_WATCHPOINT_PRECISE
,
57 NDS32_DEBUG_DATA_VALUE_WATCHPOINT_PRECISE
,
58 NDS32_DEBUG_DATA_VALUE_WATCHPOINT_IMPRECISE
,
59 NDS32_DEBUG_DEBUG_INTERRUPT
,
60 NDS32_DEBUG_HARDWARE_SINGLE_STEP
,
61 NDS32_DEBUG_DATA_ADDR_WATCHPOINT_NEXT_PRECISE
,
62 NDS32_DEBUG_DATA_VALUE_WATCHPOINT_NEXT_PRECISE
,
63 NDS32_DEBUG_LOAD_STORE_GLOBAL_STOP
,
66 #define NDS32_STRUCT_STAT_SIZE 60
67 #define NDS32_STRUCT_TIMEVAL_SIZE 8
69 enum nds32_syscall_id
{
70 NDS32_SYSCALL_UNDEFINED
= 0,
71 NDS32_SYSCALL_EXIT
= 1,
72 NDS32_SYSCALL_OPEN
= 2,
73 NDS32_SYSCALL_CLOSE
= 3,
74 NDS32_SYSCALL_READ
= 4,
75 NDS32_SYSCALL_WRITE
= 5,
76 NDS32_SYSCALL_LSEEK
= 6,
77 NDS32_SYSCALL_UNLINK
= 7,
78 NDS32_SYSCALL_RENAME
= 3001,
79 NDS32_SYSCALL_FSTAT
= 10,
80 NDS32_SYSCALL_STAT
= 15,
81 NDS32_SYSCALL_GETTIMEOFDAY
= 19,
82 NDS32_SYSCALL_ISATTY
= 3002,
83 NDS32_SYSCALL_SYSTEM
= 3003,
84 NDS32_SYSCALL_ERRNO
= 6001,
87 #define NDS32_COMMON_MAGIC (int)0xADE5ADE5
91 /** EDM_CFG.VER, indicate the EDM version */
94 /** The number of hardware breakpoints */
97 /** EDM_CFG.DALM, indicate if direct local memory access
98 * feature is supported or not */
99 bool direct_access_local_memory
;
101 /** Support ACC_CTL register */
105 bool support_max_stop
;
110 /** enable cache or not */
113 /** cache sets per way */
119 /** cache line size */
122 /** cache locking support */
126 struct nds32_memory
{
129 struct nds32_cache icache
;
132 struct nds32_cache dcache
;
134 /** On-chip instruction local memory base */
137 /** On-chip instruction local memory size */
140 /** ILM base register alignment version */
143 /** DLM is enabled or not */
146 /** DLM start address */
149 /** DLM end address */
152 /** On-chip data local memory base */
155 /** On-chip data local memory size */
158 /** DLM base register alignment version */
161 /** DLM is enabled or not */
164 /** DLM start address */
167 /** DLM end address */
170 /** Memory access method */
171 enum nds_memory_access access_channel
;
173 /** Memory access mode */
174 enum nds_memory_select mode
;
176 /** Address translation */
177 bool address_translation
;
180 struct nds32_cpu_version
{
181 bool performance_extension
;
182 bool _16bit_extension
;
183 bool performance_extension_2
;
184 bool cop_fpu_extension
;
185 bool string_extension
;
192 struct nds32_mmu_config
{
193 int memory_protection
;
194 int memory_protection_version
;
195 bool fully_associative_tlb
;
199 bool _8k_page_support
;
200 int extra_page_size_support
;
202 bool hardware_page_table_walker
;
209 int default_min_page_size
;
210 bool multiple_page_size_in_use
;
213 struct nds32_misc_config
{
215 bool local_memory_dma
;
216 bool performance_monitor
;
217 bool high_speed_memory_port
;
219 bool div_instruction
;
220 bool mac_instruction
;
223 bool reduce_register
;
225 bool interruption_level
;
226 int baseline_instruction
;
228 bool implement_dependant_register
;
229 bool implement_dependant_sr_encoding
;
237 * Represents a generic Andes core.
241 struct reg_cache
*core_cache
;
243 /** Handle for the debug module. */
244 struct nds32_edm edm
;
246 /** Memory information */
247 struct nds32_memory memory
;
250 struct nds32_cpu_version cpu_version
;
252 /** MMU configuration */
253 struct nds32_mmu_config mmu_config
;
255 /** Misc configuration */
256 struct nds32_misc_config misc_config
;
258 /** Retrieve all core registers, for display. */
259 int (*full_context
)(struct nds32
*nds32
);
261 /** Register mappings */
262 int (*register_map
)(struct nds32
*nds32
, int reg_no
);
264 /** Get debug exception virtual address */
265 int (*get_debug_reason
)(struct nds32
*nds32
, uint32_t *reason
);
267 /** Restore target registers may be modified in debug state */
268 int (*leave_debug_state
)(struct nds32
*nds32
, bool enable_watchpoint
);
270 /** Backup target registers may be modified in debug state */
271 int (*enter_debug_state
)(struct nds32
*nds32
, bool enable_watchpoint
);
273 /** Get address hit watchpoint */
274 int (*get_watched_address
)(struct nds32
*nds32
, uint32_t *address
, uint32_t reason
);
276 /** maximum interrupt level */
277 uint32_t max_interrupt_level
;
279 /** current interrupt level */
280 uint32_t current_interrupt_level
;
282 uint32_t watched_address
;
284 /** Flag reporting whether virtual hosting is active. */
285 bool virtual_hosting
;
287 /** Flag reporting whether global stop is active. */
290 /** Flag reporting whether to use soft-reset-halt or not as issuing reset-halt. */
291 bool soft_reset_halt
;
293 /** reset-halt as target examine */
294 bool reset_halt_as_examine
;
296 /** backup/restore target EDM_CTL value. As debugging target debug
297 * handler, it should be true. */
298 bool keep_target_edm_ctl
;
300 /** always use word-aligned address to access memory */
301 bool word_access_mem
;
303 /** EDM passcode for debugging secure MCU */
306 /** current privilege_level if using secure MCU. value 0 is the highest level. */
309 /** Period to wait after SRST. */
312 /** Flag to indicate HSS steps into ISR or not */
313 bool step_isr_enable
;
315 /** Flag to indicate register table is ready or not */
316 bool init_arch_info_after_halted
;
318 /** Flag to indicate audio-extension is enabled or not */
321 /** Flag to indicate fpu-extension is enabled or not */
324 /* Andes Core has mixed endian model. Instruction is always big-endian.
325 * Data may be big or little endian. Device registers may have different
326 * endian from data and instruction. */
327 /** Endian of data memory */
328 enum target_endianness data_endian
;
330 /** Endian of device registers */
331 enum target_endianness device_reg_endian
;
333 /** Flag to indicate if auto convert software breakpoints to
334 * hardware breakpoints or not in ROM */
335 bool auto_convert_hw_bp
;
337 /** Backpointer to the target. */
338 struct target
*target
;
347 struct target
*target
;
352 struct nds32_edm_operation
{
357 extern int nds32_config(struct nds32
*nds32
);
358 extern int nds32_init_arch_info(struct target
*target
, struct nds32
*nds32
);
359 extern int nds32_full_context(struct nds32
*nds32
);
360 extern int nds32_arch_state(struct target
*target
);
361 extern int nds32_add_software_breakpoint(struct target
*target
,
362 struct breakpoint
*breakpoint
);
363 extern int nds32_remove_software_breakpoint(struct target
*target
,
364 struct breakpoint
*breakpoint
);
366 extern int nds32_get_gdb_reg_list(struct target
*target
,
367 struct reg
**reg_list
[], int *reg_list_size
,
368 enum target_register_class reg_class
);
370 extern int nds32_write_buffer(struct target
*target
, uint32_t address
,
371 uint32_t size
, const uint8_t *buffer
);
372 extern int nds32_read_buffer(struct target
*target
, uint32_t address
,
373 uint32_t size
, uint8_t *buffer
);
374 extern int nds32_bulk_write_memory(struct target
*target
,
375 uint32_t address
, uint32_t count
, const uint8_t *buffer
);
376 extern int nds32_read_memory(struct target
*target
, uint32_t address
,
377 uint32_t size
, uint32_t count
, uint8_t *buffer
);
378 extern int nds32_write_memory(struct target
*target
, uint32_t address
,
379 uint32_t size
, uint32_t count
, const uint8_t *buffer
);
381 extern int nds32_init_register_table(struct nds32
*nds32
);
382 extern int nds32_init_memory_info(struct nds32
*nds32
);
383 extern int nds32_restore_context(struct target
*target
);
384 extern int nds32_get_mapped_reg(struct nds32
*nds32
, unsigned regnum
, uint32_t *value
);
385 extern int nds32_set_mapped_reg(struct nds32
*nds32
, unsigned regnum
, uint32_t value
);
387 extern int nds32_edm_config(struct nds32
*nds32
);
388 extern int nds32_cache_sync(struct target
*target
, uint32_t address
, uint32_t length
);
389 extern int nds32_mmu(struct target
*target
, int *enabled
);
390 extern int nds32_virtual_to_physical(struct target
*target
, uint32_t address
,
392 extern int nds32_read_phys_memory(struct target
*target
, uint32_t address
,
393 uint32_t size
, uint32_t count
, uint8_t *buffer
);
394 extern int nds32_write_phys_memory(struct target
*target
, uint32_t address
,
395 uint32_t size
, uint32_t count
, const uint8_t *buffer
);
396 extern uint32_t nds32_nextpc(struct nds32
*nds32
, int current
, uint32_t address
);
397 extern int nds32_examine_debug_reason(struct nds32
*nds32
);
398 extern int nds32_step(struct target
*target
, int current
,
399 uint32_t address
, int handle_breakpoints
);
400 extern int nds32_target_state(struct nds32
*nds32
, enum target_state
*state
);
401 extern int nds32_halt(struct target
*target
);
402 extern int nds32_poll(struct target
*target
);
403 extern int nds32_resume(struct target
*target
, int current
,
404 uint32_t address
, int handle_breakpoints
, int debug_execution
);
405 extern int nds32_assert_reset(struct target
*target
);
406 extern int nds32_init(struct nds32
*nds32
);
407 extern int nds32_reset_halt(struct nds32
*nds32
);
408 extern int nds32_login(struct nds32
*nds32
);
410 /** Convert target handle to generic Andes target state handle. */
411 static inline struct nds32
*target_to_nds32(struct target
*target
)
413 assert(target
!= NULL
);
414 return target
->arch_info
;
418 static inline struct aice_port_s
*target_to_aice(struct target
*target
)
420 assert(target
!= NULL
);
421 return target
->tap
->priv
;
424 static inline bool is_nds32(struct nds32
*nds32
)
426 assert(nds32
!= NULL
);
427 return nds32
->common_magic
== NDS32_COMMON_MAGIC
;
430 static inline bool nds32_reach_max_interrupt_level(struct nds32
*nds32
)
432 assert(nds32
!= NULL
);
433 return nds32
->max_interrupt_level
== nds32
->current_interrupt_level
;
436 #endif /* __NDS32_H__ */
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