1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * Copyright (C) 2011 by Drasko DRASKOVIC *
10 * drasko.draskovic@gmail.com *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
24 ***************************************************************************/
30 #include "breakpoints.h"
33 #include "mips32_dmaacc.h"
34 #include "target_type.h"
37 static void mips_m4k_enable_breakpoints(struct target
*target
);
38 static void mips_m4k_enable_watchpoints(struct target
*target
);
39 static int mips_m4k_set_breakpoint(struct target
*target
,
40 struct breakpoint
*breakpoint
);
41 static int mips_m4k_unset_breakpoint(struct target
*target
,
42 struct breakpoint
*breakpoint
);
43 static int mips_m4k_internal_restore(struct target
*target
, int current
,
44 target_addr_t address
, int handle_breakpoints
,
46 static int mips_m4k_halt(struct target
*target
);
47 static int mips_m4k_bulk_write_memory(struct target
*target
, target_addr_t address
,
48 uint32_t count
, const uint8_t *buffer
);
50 static int mips_m4k_examine_debug_reason(struct target
*target
)
52 struct mips32_common
*mips32
= target_to_mips32(target
);
53 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
54 uint32_t break_status
;
57 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
58 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
59 if (ejtag_info
->debug_caps
& EJTAG_DCR_IB
) {
60 /* get info about inst breakpoint support */
61 retval
= target_read_u32(target
,
62 ejtag_info
->ejtag_ibs_addr
, &break_status
);
63 if (retval
!= ERROR_OK
)
65 if (break_status
& 0x1f) {
66 /* we have halted on a breakpoint */
67 retval
= target_write_u32(target
,
68 ejtag_info
->ejtag_ibs_addr
, 0);
69 if (retval
!= ERROR_OK
)
71 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
75 if (ejtag_info
->debug_caps
& EJTAG_DCR_DB
) {
76 /* get info about data breakpoint support */
77 retval
= target_read_u32(target
,
78 ejtag_info
->ejtag_dbs_addr
, &break_status
);
79 if (retval
!= ERROR_OK
)
81 if (break_status
& 0x1f) {
82 /* we have halted on a breakpoint */
83 retval
= target_write_u32(target
,
84 ejtag_info
->ejtag_dbs_addr
, 0);
85 if (retval
!= ERROR_OK
)
87 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
95 static int mips_m4k_debug_entry(struct target
*target
)
97 struct mips32_common
*mips32
= target_to_mips32(target
);
98 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
100 mips32_save_context(target
);
102 /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
103 mips_ejtag_config_step(ejtag_info
, 0);
105 /* make sure break unit configured */
106 mips32_configure_break_unit(target
);
108 /* attempt to find halt reason */
109 mips_m4k_examine_debug_reason(target
);
111 mips32_read_config_regs(target
);
113 /* default to mips32 isa, it will be changed below if required */
114 mips32
->isa_mode
= MIPS32_ISA_MIPS32
;
116 /* other than mips32 only and isa bit set ? */
117 if (mips32
->isa_imp
&& buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1))
118 mips32
->isa_mode
= mips32
->isa_imp
== 2 ? MIPS32_ISA_MIPS16E
: MIPS32_ISA_MMIPS32
;
120 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
121 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32),
122 target_state_name(target
));
127 static struct target
*get_mips_m4k(struct target
*target
, int32_t coreid
)
129 struct target_list
*head
;
133 while (head
!= (struct target_list
*)NULL
) {
135 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
142 static int mips_m4k_halt_smp(struct target
*target
)
144 int retval
= ERROR_OK
;
145 struct target_list
*head
;
148 while (head
!= (struct target_list
*)NULL
) {
151 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
))
152 ret
= mips_m4k_halt(curr
);
154 if (ret
!= ERROR_OK
) {
155 LOG_ERROR("halt failed target->coreid: %" PRId32
, curr
->coreid
);
163 static int update_halt_gdb(struct target
*target
)
165 int retval
= ERROR_OK
;
166 if (target
->gdb_service
->core
[0] == -1) {
167 target
->gdb_service
->target
= target
;
168 target
->gdb_service
->core
[0] = target
->coreid
;
169 retval
= mips_m4k_halt_smp(target
);
174 static int mips_m4k_poll(struct target
*target
)
176 int retval
= ERROR_OK
;
177 struct mips32_common
*mips32
= target_to_mips32(target
);
178 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
179 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
180 enum target_state prev_target_state
= target
->state
;
182 /* toggle to another core is done by gdb as follow */
183 /* maint packet J core_id */
185 /* the next polling trigger an halt event sent to gdb */
186 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
187 (target
->gdb_service
) &&
188 (target
->gdb_service
->target
== NULL
)) {
189 target
->gdb_service
->target
=
190 get_mips_m4k(target
, target
->gdb_service
->core
[1]);
191 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
195 /* read ejtag control reg */
196 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
197 retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
198 if (retval
!= ERROR_OK
)
201 ejtag_info
->isa
= (ejtag_ctrl
& EJTAG_CTRL_DBGISA
) ? 1 : 0;
203 /* clear this bit before handling polling
204 * as after reset registers will read zero */
205 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
) {
206 /* we have detected a reset, clear flag
207 * otherwise ejtag will not work */
208 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
210 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
211 retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
212 if (retval
!= ERROR_OK
)
214 LOG_DEBUG("Reset Detected");
217 /* check for processor halted */
218 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
) {
219 if ((target
->state
!= TARGET_HALTED
)
220 && (target
->state
!= TARGET_DEBUG_RUNNING
)) {
221 if (target
->state
== TARGET_UNKNOWN
)
222 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
224 /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
225 * (maybe put on by HALT-ing the board in the previous session).
227 * Force enable debug entry for this session.
229 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
230 target
->state
= TARGET_HALTED
;
231 retval
= mips_m4k_debug_entry(target
);
232 if (retval
!= ERROR_OK
)
236 ((prev_target_state
== TARGET_RUNNING
)
237 || (prev_target_state
== TARGET_RESET
))) {
238 retval
= update_halt_gdb(target
);
239 if (retval
!= ERROR_OK
)
242 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
243 } else if (target
->state
== TARGET_DEBUG_RUNNING
) {
244 target
->state
= TARGET_HALTED
;
246 retval
= mips_m4k_debug_entry(target
);
247 if (retval
!= ERROR_OK
)
251 retval
= update_halt_gdb(target
);
252 if (retval
!= ERROR_OK
)
256 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
259 target
->state
= TARGET_RUNNING
;
261 /* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
266 static int mips_m4k_halt(struct target
*target
)
268 struct mips32_common
*mips32
= target_to_mips32(target
);
269 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
271 LOG_DEBUG("target->state: %s", target_state_name(target
));
273 if (target
->state
== TARGET_HALTED
) {
274 LOG_DEBUG("target was already halted");
278 if (target
->state
== TARGET_UNKNOWN
)
279 LOG_WARNING("target was in unknown state when halt was requested");
281 if (target
->state
== TARGET_RESET
) {
282 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
283 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
284 return ERROR_TARGET_FAILURE
;
286 /* we came here in a reset_halt or reset_init sequence
287 * debug entry was already prepared in mips_m4k_assert_reset()
289 target
->debug_reason
= DBG_REASON_DBGRQ
;
295 /* break processor */
296 mips_ejtag_enter_debug(ejtag_info
);
298 target
->debug_reason
= DBG_REASON_DBGRQ
;
303 static int mips_m4k_assert_reset(struct target
*target
)
305 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
306 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
308 /* TODO: apply hw reset signal in not examined state */
309 if (!(target_was_examined(target
))) {
310 LOG_WARNING("Reset is not asserted because the target is not examined.");
311 LOG_WARNING("Use a reset button or power cycle the target.");
312 return ERROR_TARGET_NOT_EXAMINED
;
315 LOG_DEBUG("target->state: %s",
316 target_state_name(target
));
318 enum reset_types jtag_reset_config
= jtag_get_reset_config();
320 /* some cores support connecting while srst is asserted
321 * use that mode is it has been configured */
323 bool srst_asserted
= false;
325 if (!(jtag_reset_config
& RESET_SRST_PULLS_TRST
) &&
326 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
327 jtag_add_reset(0, 1);
328 srst_asserted
= true;
332 /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
333 if (ejtag_info
->ejtag_version
!= EJTAG_VERSION_20
) {
334 if (target
->reset_halt
) {
335 /* use hardware to catch reset */
336 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
);
338 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
341 if (jtag_reset_config
& RESET_HAS_SRST
) {
342 /* here we should issue a srst only, but we may have to assert trst as well */
343 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
344 jtag_add_reset(1, 1);
345 else if (!srst_asserted
)
346 jtag_add_reset(0, 1);
348 if (mips_m4k
->is_pic32mx
) {
349 LOG_DEBUG("Using MTAP reset to reset processor...");
351 /* use microchip specific MTAP reset */
352 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_MTAP
);
353 mips_ejtag_set_instr(ejtag_info
, MTAP_COMMAND
);
355 mips_ejtag_drscan_8_out(ejtag_info
, MCHP_ASERT_RST
);
356 mips_ejtag_drscan_8_out(ejtag_info
, MCHP_DE_ASSERT_RST
);
357 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
359 /* use ejtag reset - not supported by all cores */
360 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
361 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
362 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
363 mips_ejtag_drscan_32_out(ejtag_info
, ejtag_ctrl
);
367 target
->state
= TARGET_RESET
;
368 jtag_add_sleep(50000);
370 register_cache_invalidate(mips_m4k
->mips32
.core_cache
);
372 if (target
->reset_halt
) {
373 int retval
= target_halt(target
);
374 if (retval
!= ERROR_OK
)
381 static int mips_m4k_deassert_reset(struct target
*target
)
383 LOG_DEBUG("target->state: %s", target_state_name(target
));
385 /* deassert reset lines */
386 jtag_add_reset(0, 0);
391 static int mips_m4k_single_step_core(struct target
*target
)
393 struct mips32_common
*mips32
= target_to_mips32(target
);
394 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
396 /* configure single step mode */
397 mips_ejtag_config_step(ejtag_info
, 1);
399 /* disable interrupts while stepping */
400 mips32_enable_interrupts(target
, 0);
402 /* exit debug mode */
403 mips_ejtag_exit_debug(ejtag_info
);
405 mips_m4k_debug_entry(target
);
410 static int mips_m4k_restore_smp(struct target
*target
, uint32_t address
, int handle_breakpoints
)
412 int retval
= ERROR_OK
;
413 struct target_list
*head
;
417 while (head
!= (struct target_list
*)NULL
) {
420 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)) {
421 /* resume current address , not in step mode */
422 ret
= mips_m4k_internal_restore(curr
, 1, address
,
423 handle_breakpoints
, 0);
425 if (ret
!= ERROR_OK
) {
426 LOG_ERROR("target->coreid :%" PRId32
" failed to resume at address :0x%" PRIx32
,
427 curr
->coreid
, address
);
436 static int mips_m4k_internal_restore(struct target
*target
, int current
,
437 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
439 struct mips32_common
*mips32
= target_to_mips32(target
);
440 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
441 struct breakpoint
*breakpoint
= NULL
;
444 if (target
->state
!= TARGET_HALTED
) {
445 LOG_WARNING("target not halted");
446 return ERROR_TARGET_NOT_HALTED
;
449 if (!debug_execution
) {
450 target_free_all_working_areas(target
);
451 mips_m4k_enable_breakpoints(target
);
452 mips_m4k_enable_watchpoints(target
);
455 /* current = 1: continue on current pc, otherwise continue at <address> */
457 mips_m4k_isa_filter(mips32
->isa_imp
, &address
);
458 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
459 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
460 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
463 if ((mips32
->isa_imp
> 1) && debug_execution
) /* if more than one isa supported */
464 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1, mips32
->isa_mode
);
469 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
471 mips32_restore_context(target
);
473 /* the front-end may request us not to handle breakpoints */
474 if (handle_breakpoints
) {
475 /* Single step past breakpoint at current address */
476 breakpoint
= breakpoint_find(target
, resume_pc
);
478 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT
"",
479 breakpoint
->address
);
480 mips_m4k_unset_breakpoint(target
, breakpoint
);
481 mips_m4k_single_step_core(target
);
482 mips_m4k_set_breakpoint(target
, breakpoint
);
486 /* enable interrupts if we are running */
487 mips32_enable_interrupts(target
, !debug_execution
);
489 /* exit debug mode */
490 mips_ejtag_exit_debug(ejtag_info
);
491 target
->debug_reason
= DBG_REASON_NOTHALTED
;
493 /* registers are now invalid */
494 register_cache_invalidate(mips32
->core_cache
);
496 if (!debug_execution
) {
497 target
->state
= TARGET_RUNNING
;
498 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
499 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
501 target
->state
= TARGET_DEBUG_RUNNING
;
502 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
503 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
509 static int mips_m4k_resume(struct target
*target
, int current
,
510 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
512 int retval
= ERROR_OK
;
514 /* dummy resume for smp toggle in order to reduce gdb impact */
515 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
516 /* simulate a start and halt of target */
517 target
->gdb_service
->target
= NULL
;
518 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
519 /* fake resume at next poll we play the target core[1], see poll*/
520 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
524 retval
= mips_m4k_internal_restore(target
, current
, address
,
528 if (retval
== ERROR_OK
&& target
->smp
) {
529 target
->gdb_service
->core
[0] = -1;
530 retval
= mips_m4k_restore_smp(target
, address
, handle_breakpoints
);
536 static int mips_m4k_step(struct target
*target
, int current
,
537 target_addr_t address
, int handle_breakpoints
)
539 /* get pointers to arch-specific information */
540 struct mips32_common
*mips32
= target_to_mips32(target
);
541 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
542 struct breakpoint
*breakpoint
= NULL
;
544 if (target
->state
!= TARGET_HALTED
) {
545 LOG_WARNING("target not halted");
546 return ERROR_TARGET_NOT_HALTED
;
549 /* current = 1: continue on current pc, otherwise continue at <address> */
551 mips_m4k_isa_filter(mips32
->isa_imp
, &address
);
552 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
553 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= 1;
554 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= 1;
557 /* the front-end may request us not to handle breakpoints */
558 if (handle_breakpoints
) {
559 breakpoint
= breakpoint_find(target
,
560 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
562 mips_m4k_unset_breakpoint(target
, breakpoint
);
565 /* restore context */
566 mips32_restore_context(target
);
568 /* configure single step mode */
569 mips_ejtag_config_step(ejtag_info
, 1);
571 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
573 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
575 /* disable interrupts while stepping */
576 mips32_enable_interrupts(target
, 0);
578 /* exit debug mode */
579 mips_ejtag_exit_debug(ejtag_info
);
581 /* registers are now invalid */
582 register_cache_invalidate(mips32
->core_cache
);
584 LOG_DEBUG("target stepped ");
585 mips_m4k_debug_entry(target
);
588 mips_m4k_set_breakpoint(target
, breakpoint
);
590 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
595 static void mips_m4k_enable_breakpoints(struct target
*target
)
597 struct breakpoint
*breakpoint
= target
->breakpoints
;
599 /* set any pending breakpoints */
601 if (breakpoint
->set
== 0)
602 mips_m4k_set_breakpoint(target
, breakpoint
);
603 breakpoint
= breakpoint
->next
;
607 static int mips_m4k_set_breakpoint(struct target
*target
,
608 struct breakpoint
*breakpoint
)
610 struct mips32_common
*mips32
= target_to_mips32(target
);
611 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
612 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
615 if (breakpoint
->set
) {
616 LOG_WARNING("breakpoint already set");
620 if (breakpoint
->type
== BKPT_HARD
) {
623 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
625 if (bp_num
>= mips32
->num_inst_bpoints
) {
626 LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32
")",
627 breakpoint
->unique_id
);
628 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
630 breakpoint
->set
= bp_num
+ 1;
631 comparator_list
[bp_num
].used
= 1;
632 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
634 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
635 * Warning: there is no IB ASID registers in 2.0.
636 * Do not set it! :) */
637 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
)
638 comparator_list
[bp_num
].bp_value
&= 0xFFFFFFFC;
640 target_write_u32(target
, comparator_list
[bp_num
].reg_address
,
641 comparator_list
[bp_num
].bp_value
);
642 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
643 ejtag_info
->ejtag_ibm_offs
, 0x00000000);
644 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
645 ejtag_info
->ejtag_ibc_offs
, 1);
646 LOG_DEBUG("bpid: %" PRIu32
", bp_num %i bp_value 0x%" PRIx32
"",
647 breakpoint
->unique_id
,
648 bp_num
, comparator_list
[bp_num
].bp_value
);
649 } else if (breakpoint
->type
== BKPT_SOFT
) {
650 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
651 if (breakpoint
->length
== 4) {
652 uint32_t verify
= 0xffffffff;
654 retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
655 breakpoint
->orig_instr
);
656 if (retval
!= ERROR_OK
)
658 retval
= target_write_u32(target
, breakpoint
->address
, MIPS32_SDBBP(ejtag_info
->isa
));
659 if (retval
!= ERROR_OK
)
662 retval
= target_read_u32(target
, breakpoint
->address
, &verify
);
663 if (retval
!= ERROR_OK
)
665 if (verify
!= MIPS32_SDBBP(ejtag_info
->isa
)) {
666 LOG_ERROR("Unable to set 32-bit breakpoint at address " TARGET_ADDR_FMT
667 " - check that memory is read/writable", breakpoint
->address
);
671 uint16_t verify
= 0xffff;
673 retval
= target_read_memory(target
, breakpoint
->address
, breakpoint
->length
, 1,
674 breakpoint
->orig_instr
);
675 if (retval
!= ERROR_OK
)
677 retval
= target_write_u16(target
, breakpoint
->address
, MIPS16_SDBBP(ejtag_info
->isa
));
678 if (retval
!= ERROR_OK
)
681 retval
= target_read_u16(target
, breakpoint
->address
, &verify
);
682 if (retval
!= ERROR_OK
)
684 if (verify
!= MIPS16_SDBBP(ejtag_info
->isa
)) {
685 LOG_ERROR("Unable to set 16-bit breakpoint at address " TARGET_ADDR_FMT
686 " - check that memory is read/writable", breakpoint
->address
);
691 breakpoint
->set
= 20; /* Any nice value but 0 */
697 static int mips_m4k_unset_breakpoint(struct target
*target
,
698 struct breakpoint
*breakpoint
)
700 /* get pointers to arch-specific information */
701 struct mips32_common
*mips32
= target_to_mips32(target
);
702 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
703 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
706 if (!breakpoint
->set
) {
707 LOG_WARNING("breakpoint not set");
711 if (breakpoint
->type
== BKPT_HARD
) {
712 int bp_num
= breakpoint
->set
- 1;
713 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
)) {
714 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32
")",
715 breakpoint
->unique_id
);
718 LOG_DEBUG("bpid: %" PRIu32
" - releasing hw: %d",
719 breakpoint
->unique_id
,
721 comparator_list
[bp_num
].used
= 0;
722 comparator_list
[bp_num
].bp_value
= 0;
723 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
724 ejtag_info
->ejtag_ibc_offs
, 0);
727 /* restore original instruction (kept in target endianness) */
728 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
729 if (breakpoint
->length
== 4) {
730 uint32_t current_instr
;
732 /* check that user program has not modified breakpoint instruction */
733 retval
= target_read_memory(target
, breakpoint
->address
, 4, 1,
734 (uint8_t *)¤t_instr
);
735 if (retval
!= ERROR_OK
)
739 * target_read_memory() gets us data in _target_ endianess.
740 * If we want to use this data on the host for comparisons with some macros
741 * we must first transform it to _host_ endianess using target_buffer_get_u32().
743 current_instr
= target_buffer_get_u32(target
, (uint8_t *)¤t_instr
);
745 if (current_instr
== MIPS32_SDBBP(ejtag_info
->isa
)) {
746 retval
= target_write_memory(target
, breakpoint
->address
, 4, 1,
747 breakpoint
->orig_instr
);
748 if (retval
!= ERROR_OK
)
752 uint16_t current_instr
;
754 /* check that user program has not modified breakpoint instruction */
755 retval
= target_read_memory(target
, breakpoint
->address
, 2, 1,
756 (uint8_t *)¤t_instr
);
757 if (retval
!= ERROR_OK
)
759 current_instr
= target_buffer_get_u16(target
, (uint8_t *)¤t_instr
);
760 if (current_instr
== MIPS16_SDBBP(ejtag_info
->isa
)) {
761 retval
= target_write_memory(target
, breakpoint
->address
, 2, 1,
762 breakpoint
->orig_instr
);
763 if (retval
!= ERROR_OK
)
773 static int mips_m4k_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
775 struct mips32_common
*mips32
= target_to_mips32(target
);
777 if (breakpoint
->type
== BKPT_HARD
) {
778 if (mips32
->num_inst_bpoints_avail
< 1) {
779 LOG_INFO("no hardware breakpoint available");
780 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
783 mips32
->num_inst_bpoints_avail
--;
786 return mips_m4k_set_breakpoint(target
, breakpoint
);
789 static int mips_m4k_remove_breakpoint(struct target
*target
,
790 struct breakpoint
*breakpoint
)
792 /* get pointers to arch-specific information */
793 struct mips32_common
*mips32
= target_to_mips32(target
);
795 if (target
->state
!= TARGET_HALTED
) {
796 LOG_WARNING("target not halted");
797 return ERROR_TARGET_NOT_HALTED
;
801 mips_m4k_unset_breakpoint(target
, breakpoint
);
803 if (breakpoint
->type
== BKPT_HARD
)
804 mips32
->num_inst_bpoints_avail
++;
809 static int mips_m4k_set_watchpoint(struct target
*target
,
810 struct watchpoint
*watchpoint
)
812 struct mips32_common
*mips32
= target_to_mips32(target
);
813 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
814 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
817 * watchpoint enabled, ignore all byte lanes in value register
818 * and exclude both load and store accesses from watchpoint
819 * condition evaluation
821 int enable
= EJTAG_DBCn_NOSB
| EJTAG_DBCn_NOLB
| EJTAG_DBCn_BE
|
822 (0xff << EJTAG_DBCn_BLM_SHIFT
);
824 if (watchpoint
->set
) {
825 LOG_WARNING("watchpoint already set");
829 while (comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
831 if (wp_num
>= mips32
->num_data_bpoints
) {
832 LOG_ERROR("Can not find free FP Comparator");
836 if (watchpoint
->length
!= 4) {
837 LOG_ERROR("Only watchpoints of length 4 are supported");
838 return ERROR_TARGET_UNALIGNED_ACCESS
;
841 if (watchpoint
->address
% 4) {
842 LOG_ERROR("Watchpoints address should be word aligned");
843 return ERROR_TARGET_UNALIGNED_ACCESS
;
846 switch (watchpoint
->rw
) {
848 enable
&= ~EJTAG_DBCn_NOLB
;
851 enable
&= ~EJTAG_DBCn_NOSB
;
854 enable
&= ~(EJTAG_DBCn_NOLB
| EJTAG_DBCn_NOSB
);
857 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
860 watchpoint
->set
= wp_num
+ 1;
861 comparator_list
[wp_num
].used
= 1;
862 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
864 /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
865 * There is as well no ASID register support. */
866 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
)
867 comparator_list
[wp_num
].bp_value
&= 0xFFFFFFF8;
869 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
870 ejtag_info
->ejtag_dbasid_offs
, 0x00000000);
872 target_write_u32(target
, comparator_list
[wp_num
].reg_address
,
873 comparator_list
[wp_num
].bp_value
);
874 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
875 ejtag_info
->ejtag_dbm_offs
, 0x00000000);
877 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
878 ejtag_info
->ejtag_dbc_offs
, enable
);
879 /* TODO: probably this value is ignored on 2.0 */
880 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
881 ejtag_info
->ejtag_dbv_offs
, 0);
882 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
887 static int mips_m4k_unset_watchpoint(struct target
*target
,
888 struct watchpoint
*watchpoint
)
890 /* get pointers to arch-specific information */
891 struct mips32_common
*mips32
= target_to_mips32(target
);
892 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
893 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
895 if (!watchpoint
->set
) {
896 LOG_WARNING("watchpoint not set");
900 int wp_num
= watchpoint
->set
- 1;
901 if ((wp_num
< 0) || (wp_num
>= mips32
->num_data_bpoints
)) {
902 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
905 comparator_list
[wp_num
].used
= 0;
906 comparator_list
[wp_num
].bp_value
= 0;
907 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
908 ejtag_info
->ejtag_dbc_offs
, 0);
914 static int mips_m4k_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
916 struct mips32_common
*mips32
= target_to_mips32(target
);
918 if (mips32
->num_data_bpoints_avail
< 1) {
919 LOG_INFO("no hardware watchpoints available");
920 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
923 mips32
->num_data_bpoints_avail
--;
925 mips_m4k_set_watchpoint(target
, watchpoint
);
929 static int mips_m4k_remove_watchpoint(struct target
*target
,
930 struct watchpoint
*watchpoint
)
932 /* get pointers to arch-specific information */
933 struct mips32_common
*mips32
= target_to_mips32(target
);
935 if (target
->state
!= TARGET_HALTED
) {
936 LOG_WARNING("target not halted");
937 return ERROR_TARGET_NOT_HALTED
;
941 mips_m4k_unset_watchpoint(target
, watchpoint
);
943 mips32
->num_data_bpoints_avail
++;
948 static void mips_m4k_enable_watchpoints(struct target
*target
)
950 struct watchpoint
*watchpoint
= target
->watchpoints
;
952 /* set any pending watchpoints */
954 if (watchpoint
->set
== 0)
955 mips_m4k_set_watchpoint(target
, watchpoint
);
956 watchpoint
= watchpoint
->next
;
960 static int mips_m4k_read_memory(struct target
*target
, target_addr_t address
,
961 uint32_t size
, uint32_t count
, uint8_t *buffer
)
963 struct mips32_common
*mips32
= target_to_mips32(target
);
964 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
966 LOG_DEBUG("address: " TARGET_ADDR_FMT
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
967 address
, size
, count
);
969 if (target
->state
!= TARGET_HALTED
) {
970 LOG_WARNING("target not halted");
971 return ERROR_TARGET_NOT_HALTED
;
974 /* sanitize arguments */
975 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
976 return ERROR_COMMAND_SYNTAX_ERROR
;
978 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
979 return ERROR_TARGET_UNALIGNED_ACCESS
;
981 /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
985 t
= malloc(count
* size
* sizeof(uint8_t));
987 LOG_ERROR("Out of memory");
993 /* if noDMA off, use DMAACC mode for memory read */
995 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
996 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, t
);
998 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, t
);
1000 /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
1001 /* endianness, but byte array should represent target endianness */
1002 if (ERROR_OK
== retval
) {
1005 target_buffer_set_u32_array(target
, buffer
, count
, t
);
1008 target_buffer_set_u16_array(target
, buffer
, count
, t
);
1013 if ((size
> 1) && (t
!= NULL
))
1019 static int mips_m4k_write_memory(struct target
*target
, target_addr_t address
,
1020 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1022 struct mips32_common
*mips32
= target_to_mips32(target
);
1023 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1025 LOG_DEBUG("address: " TARGET_ADDR_FMT
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
1026 address
, size
, count
);
1028 if (target
->state
!= TARGET_HALTED
) {
1029 LOG_WARNING("target not halted");
1030 return ERROR_TARGET_NOT_HALTED
;
1033 if (size
== 4 && count
> 32) {
1034 int retval
= mips_m4k_bulk_write_memory(target
, address
, count
, buffer
);
1035 if (retval
== ERROR_OK
)
1037 LOG_WARNING("Falling back to non-bulk write");
1040 /* sanitize arguments */
1041 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1042 return ERROR_COMMAND_SYNTAX_ERROR
;
1044 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1045 return ERROR_TARGET_UNALIGNED_ACCESS
;
1047 /** correct endianess if we have word or hword access */
1050 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1051 /* endianness, but byte array represents target endianness */
1052 t
= malloc(count
* size
* sizeof(uint8_t));
1054 LOG_ERROR("Out of memory");
1060 target_buffer_get_u32_array(target
, buffer
, count
, (uint32_t *)t
);
1063 target_buffer_get_u16_array(target
, buffer
, count
, (uint16_t *)t
);
1069 /* if noDMA off, use DMAACC mode for memory write */
1071 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
1072 retval
= mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, buffer
);
1074 retval
= mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, buffer
);
1079 if (ERROR_OK
!= retval
)
1085 static int mips_m4k_init_target(struct command_context
*cmd_ctx
,
1086 struct target
*target
)
1088 mips32_build_reg_cache(target
);
1093 static int mips_m4k_init_arch_info(struct target
*target
,
1094 struct mips_m4k_common
*mips_m4k
, struct jtag_tap
*tap
)
1096 struct mips32_common
*mips32
= &mips_m4k
->mips32
;
1098 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
1100 /* initialize mips4k specific info */
1101 mips32_init_arch_info(target
, mips32
, tap
);
1102 mips32
->arch_info
= mips_m4k
;
1107 static int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
)
1109 struct mips_m4k_common
*mips_m4k
= calloc(1, sizeof(struct mips_m4k_common
));
1111 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
1116 static int mips_m4k_examine(struct target
*target
)
1119 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1120 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1121 uint32_t idcode
= 0;
1123 if (!target_was_examined(target
)) {
1124 retval
= mips_ejtag_get_idcode(ejtag_info
, &idcode
);
1125 if (retval
!= ERROR_OK
)
1127 ejtag_info
->idcode
= idcode
;
1129 if (((idcode
>> 1) & 0x7FF) == 0x29) {
1130 /* we are using a pic32mx so select ejtag port
1131 * as it is not selected by default */
1132 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
1133 LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
1134 mips_m4k
->is_pic32mx
= true;
1138 /* init rest of ejtag interface */
1139 retval
= mips_ejtag_init(ejtag_info
);
1140 if (retval
!= ERROR_OK
)
1143 retval
= mips32_examine(target
);
1144 if (retval
!= ERROR_OK
)
1150 static int mips_m4k_bulk_write_memory(struct target
*target
, target_addr_t address
,
1151 uint32_t count
, const uint8_t *buffer
)
1153 struct mips32_common
*mips32
= target_to_mips32(target
);
1154 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1155 struct working_area
*fast_data_area
;
1159 LOG_DEBUG("address: " TARGET_ADDR_FMT
", count: 0x%8.8" PRIx32
"",
1162 /* check alignment */
1164 return ERROR_TARGET_UNALIGNED_ACCESS
;
1166 if (mips32
->fast_data_area
== NULL
) {
1167 /* Get memory for block write handler
1168 * we preserve this area between calls and gain a speed increase
1169 * of about 3kb/sec when writing flash
1170 * this will be released/nulled by the system when the target is resumed or reset */
1171 retval
= target_alloc_working_area(target
,
1172 MIPS32_FASTDATA_HANDLER_SIZE
,
1173 &mips32
->fast_data_area
);
1174 if (retval
!= ERROR_OK
) {
1175 LOG_ERROR("No working area available");
1179 /* reset fastadata state so the algo get reloaded */
1180 ejtag_info
->fast_access_save
= -1;
1183 fast_data_area
= mips32
->fast_data_area
;
1185 if (address
<= fast_data_area
->address
+ fast_data_area
->size
&&
1186 fast_data_area
->address
<= address
+ count
) {
1187 LOG_ERROR("fast_data (" TARGET_ADDR_FMT
") is within write area "
1188 "(" TARGET_ADDR_FMT
"-" TARGET_ADDR_FMT
").",
1189 fast_data_area
->address
, address
, address
+ count
);
1190 LOG_ERROR("Change work-area-phys or load_image address!");
1194 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1195 /* but byte array represents target endianness */
1197 t
= malloc(count
* sizeof(uint32_t));
1199 LOG_ERROR("Out of memory");
1203 target_buffer_get_u32_array(target
, buffer
, count
, t
);
1205 retval
= mips32_pracc_fastdata_xfer(ejtag_info
, mips32
->fast_data_area
, write_t
, address
,
1211 if (retval
!= ERROR_OK
)
1212 LOG_ERROR("Fastdata access Failed");
1217 static int mips_m4k_verify_pointer(struct command_context
*cmd_ctx
,
1218 struct mips_m4k_common
*mips_m4k
)
1220 if (mips_m4k
->common_magic
!= MIPSM4K_COMMON_MAGIC
) {
1221 command_print(cmd_ctx
, "target is not an MIPS_M4K");
1222 return ERROR_TARGET_INVALID
;
1227 COMMAND_HANDLER(mips_m4k_handle_cp0_command
)
1230 struct target
*target
= get_current_target(CMD_CTX
);
1231 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1232 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1234 retval
= mips_m4k_verify_pointer(CMD_CTX
, mips_m4k
);
1235 if (retval
!= ERROR_OK
)
1238 if (target
->state
!= TARGET_HALTED
) {
1239 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
1243 /* two or more argument, access a single register/select (write if third argument is given) */
1245 return ERROR_COMMAND_SYNTAX_ERROR
;
1247 uint32_t cp0_reg
, cp0_sel
;
1248 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], cp0_reg
);
1249 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], cp0_sel
);
1251 if (CMD_ARGC
== 2) {
1253 retval
= mips32_cp0_read(ejtag_info
, &value
, cp0_reg
, cp0_sel
);
1254 if (retval
!= ERROR_OK
) {
1255 command_print(CMD_CTX
,
1256 "couldn't access reg %" PRIi32
,
1260 command_print(CMD_CTX
, "cp0 reg %" PRIi32
", select %" PRIi32
": %8.8" PRIx32
,
1261 cp0_reg
, cp0_sel
, value
);
1263 } else if (CMD_ARGC
== 3) {
1265 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
1266 retval
= mips32_cp0_write(ejtag_info
, value
, cp0_reg
, cp0_sel
);
1267 if (retval
!= ERROR_OK
) {
1268 command_print(CMD_CTX
,
1269 "couldn't access cp0 reg %" PRIi32
", select %" PRIi32
,
1273 command_print(CMD_CTX
, "cp0 reg %" PRIi32
", select %" PRIi32
": %8.8" PRIx32
,
1274 cp0_reg
, cp0_sel
, value
);
1281 COMMAND_HANDLER(mips_m4k_handle_smp_off_command
)
1283 struct target
*target
= get_current_target(CMD_CTX
);
1284 /* check target is an smp target */
1285 struct target_list
*head
;
1286 struct target
*curr
;
1287 head
= target
->head
;
1289 if (head
!= (struct target_list
*)NULL
) {
1290 while (head
!= (struct target_list
*)NULL
) {
1291 curr
= head
->target
;
1295 /* fixes the target display to the debugger */
1296 target
->gdb_service
->target
= target
;
1301 COMMAND_HANDLER(mips_m4k_handle_smp_on_command
)
1303 struct target
*target
= get_current_target(CMD_CTX
);
1304 struct target_list
*head
;
1305 struct target
*curr
;
1306 head
= target
->head
;
1307 if (head
!= (struct target_list
*)NULL
) {
1309 while (head
!= (struct target_list
*)NULL
) {
1310 curr
= head
->target
;
1318 COMMAND_HANDLER(mips_m4k_handle_smp_gdb_command
)
1320 struct target
*target
= get_current_target(CMD_CTX
);
1321 int retval
= ERROR_OK
;
1322 struct target_list
*head
;
1323 head
= target
->head
;
1324 if (head
!= (struct target_list
*)NULL
) {
1325 if (CMD_ARGC
== 1) {
1327 COMMAND_PARSE_NUMBER(int, CMD_ARGV
[0], coreid
);
1328 if (ERROR_OK
!= retval
)
1330 target
->gdb_service
->core
[1] = coreid
;
1333 command_print(CMD_CTX
, "gdb coreid %" PRId32
" -> %" PRId32
, target
->gdb_service
->core
[0]
1334 , target
->gdb_service
->core
[1]);
1339 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command
)
1341 struct target
*target
= get_current_target(CMD_CTX
);
1342 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1343 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1346 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], ejtag_info
->scan_delay
);
1347 else if (CMD_ARGC
> 1)
1348 return ERROR_COMMAND_SYNTAX_ERROR
;
1350 command_print(CMD_CTX
, "scan delay: %d nsec", ejtag_info
->scan_delay
);
1351 if (ejtag_info
->scan_delay
>= MIPS32_SCAN_DELAY_LEGACY_MODE
) {
1352 ejtag_info
->mode
= 0;
1353 command_print(CMD_CTX
, "running in legacy mode");
1355 ejtag_info
->mode
= 1;
1356 command_print(CMD_CTX
, "running in fast queued mode");
1362 static const struct command_registration mips_m4k_exec_command_handlers
[] = {
1365 .handler
= mips_m4k_handle_cp0_command
,
1366 .mode
= COMMAND_EXEC
,
1367 .usage
= "regnum [value]",
1368 .help
= "display/modify cp0 register",
1372 .handler
= mips_m4k_handle_smp_off_command
,
1373 .mode
= COMMAND_EXEC
,
1374 .help
= "Stop smp handling",
1379 .handler
= mips_m4k_handle_smp_on_command
,
1380 .mode
= COMMAND_EXEC
,
1381 .help
= "Restart smp handling",
1386 .handler
= mips_m4k_handle_smp_gdb_command
,
1387 .mode
= COMMAND_EXEC
,
1388 .help
= "display/fix current core played to gdb",
1392 .name
= "scan_delay",
1393 .handler
= mips_m4k_handle_scan_delay_command
,
1394 .mode
= COMMAND_ANY
,
1395 .help
= "display/set scan delay in nano seconds",
1398 COMMAND_REGISTRATION_DONE
1401 const struct command_registration mips_m4k_command_handlers
[] = {
1403 .chain
= mips32_command_handlers
,
1407 .mode
= COMMAND_ANY
,
1408 .help
= "mips_m4k command group",
1410 .chain
= mips_m4k_exec_command_handlers
,
1412 COMMAND_REGISTRATION_DONE
1415 struct target_type mips_m4k_target
= {
1418 .poll
= mips_m4k_poll
,
1419 .arch_state
= mips32_arch_state
,
1421 .halt
= mips_m4k_halt
,
1422 .resume
= mips_m4k_resume
,
1423 .step
= mips_m4k_step
,
1425 .assert_reset
= mips_m4k_assert_reset
,
1426 .deassert_reset
= mips_m4k_deassert_reset
,
1428 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
1430 .read_memory
= mips_m4k_read_memory
,
1431 .write_memory
= mips_m4k_write_memory
,
1432 .checksum_memory
= mips32_checksum_memory
,
1433 .blank_check_memory
= mips32_blank_check_memory
,
1435 .run_algorithm
= mips32_run_algorithm
,
1437 .add_breakpoint
= mips_m4k_add_breakpoint
,
1438 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
1439 .add_watchpoint
= mips_m4k_add_watchpoint
,
1440 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
1442 .commands
= mips_m4k_command_handlers
,
1443 .target_create
= mips_m4k_target_create
,
1444 .init_target
= mips_m4k_init_target
,
1445 .examine
= mips_m4k_examine
,
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