1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * Copyright (C) 2011 by Drasko DRASKOVIC *
10 * drasko.draskovic@gmail.com *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
24 ***************************************************************************/
30 #include "breakpoints.h"
33 #include "mips32_dmaacc.h"
34 #include "target_type.h"
38 static void mips_m4k_enable_breakpoints(struct target
*target
);
39 static void mips_m4k_enable_watchpoints(struct target
*target
);
40 static int mips_m4k_set_breakpoint(struct target
*target
,
41 struct breakpoint
*breakpoint
);
42 static int mips_m4k_unset_breakpoint(struct target
*target
,
43 struct breakpoint
*breakpoint
);
44 static int mips_m4k_internal_restore(struct target
*target
, int current
,
45 target_addr_t address
, int handle_breakpoints
,
47 static int mips_m4k_halt(struct target
*target
);
48 static int mips_m4k_bulk_write_memory(struct target
*target
, target_addr_t address
,
49 uint32_t count
, const uint8_t *buffer
);
51 static int mips_m4k_examine_debug_reason(struct target
*target
)
53 struct mips32_common
*mips32
= target_to_mips32(target
);
54 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
55 uint32_t break_status
;
58 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
59 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
60 if (ejtag_info
->debug_caps
& EJTAG_DCR_IB
) {
61 /* get info about inst breakpoint support */
62 retval
= target_read_u32(target
,
63 ejtag_info
->ejtag_ibs_addr
, &break_status
);
64 if (retval
!= ERROR_OK
)
66 if (break_status
& 0x1f) {
67 /* we have halted on a breakpoint */
68 retval
= target_write_u32(target
,
69 ejtag_info
->ejtag_ibs_addr
, 0);
70 if (retval
!= ERROR_OK
)
72 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
76 if (ejtag_info
->debug_caps
& EJTAG_DCR_DB
) {
77 /* get info about data breakpoint support */
78 retval
= target_read_u32(target
,
79 ejtag_info
->ejtag_dbs_addr
, &break_status
);
80 if (retval
!= ERROR_OK
)
82 if (break_status
& 0x1f) {
83 /* we have halted on a breakpoint */
84 retval
= target_write_u32(target
,
85 ejtag_info
->ejtag_dbs_addr
, 0);
86 if (retval
!= ERROR_OK
)
88 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
96 static int mips_m4k_debug_entry(struct target
*target
)
98 struct mips32_common
*mips32
= target_to_mips32(target
);
99 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
101 mips32_save_context(target
);
103 /* make sure stepping disabled, SSt bit in CP0 debug register cleared */
104 mips_ejtag_config_step(ejtag_info
, 0);
106 /* make sure break unit configured */
107 mips32_configure_break_unit(target
);
109 /* attempt to find halt reason */
110 mips_m4k_examine_debug_reason(target
);
112 mips32_read_config_regs(target
);
114 /* default to mips32 isa, it will be changed below if required */
115 mips32
->isa_mode
= MIPS32_ISA_MIPS32
;
117 /* other than mips32 only and isa bit set ? */
118 if (mips32
->isa_imp
&& buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1))
119 mips32
->isa_mode
= mips32
->isa_imp
== 2 ? MIPS32_ISA_MIPS16E
: MIPS32_ISA_MMIPS32
;
121 LOG_DEBUG("entered debug state at PC 0x%" PRIx32
", target->state: %s",
122 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32),
123 target_state_name(target
));
128 static struct target
*get_mips_m4k(struct target
*target
, int32_t coreid
)
130 struct target_list
*head
;
134 while (head
!= (struct target_list
*)NULL
) {
136 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
143 static int mips_m4k_halt_smp(struct target
*target
)
145 int retval
= ERROR_OK
;
146 struct target_list
*head
;
149 while (head
!= (struct target_list
*)NULL
) {
152 if ((curr
!= target
) && (curr
->state
!= TARGET_HALTED
))
153 ret
= mips_m4k_halt(curr
);
155 if (ret
!= ERROR_OK
) {
156 LOG_ERROR("halt failed target->coreid: %" PRId32
, curr
->coreid
);
164 static int update_halt_gdb(struct target
*target
)
166 int retval
= ERROR_OK
;
167 if (target
->gdb_service
->core
[0] == -1) {
168 target
->gdb_service
->target
= target
;
169 target
->gdb_service
->core
[0] = target
->coreid
;
170 retval
= mips_m4k_halt_smp(target
);
175 static int mips_m4k_poll(struct target
*target
)
177 int retval
= ERROR_OK
;
178 struct mips32_common
*mips32
= target_to_mips32(target
);
179 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
180 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
181 enum target_state prev_target_state
= target
->state
;
183 /* toggle to another core is done by gdb as follow */
184 /* maint packet J core_id */
186 /* the next polling trigger an halt event sent to gdb */
187 if ((target
->state
== TARGET_HALTED
) && (target
->smp
) &&
188 (target
->gdb_service
) &&
189 (!target
->gdb_service
->target
)) {
190 target
->gdb_service
->target
=
191 get_mips_m4k(target
, target
->gdb_service
->core
[1]);
192 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
196 /* read ejtag control reg */
197 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
198 retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
199 if (retval
!= ERROR_OK
)
202 ejtag_info
->isa
= (ejtag_ctrl
& EJTAG_CTRL_DBGISA
) ? 1 : 0;
204 /* clear this bit before handling polling
205 * as after reset registers will read zero */
206 if (ejtag_ctrl
& EJTAG_CTRL_ROCC
) {
207 /* we have detected a reset, clear flag
208 * otherwise ejtag will not work */
209 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_ROCC
;
211 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
212 retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
213 if (retval
!= ERROR_OK
)
215 LOG_DEBUG("Reset Detected");
218 /* check for processor halted */
219 if (ejtag_ctrl
& EJTAG_CTRL_BRKST
) {
220 if ((target
->state
!= TARGET_HALTED
)
221 && (target
->state
!= TARGET_DEBUG_RUNNING
)) {
222 if (target
->state
== TARGET_UNKNOWN
)
223 LOG_DEBUG("EJTAG_CTRL_BRKST already set during server startup.");
225 /* OpenOCD was was probably started on the board with EJTAG_CTRL_BRKST already set
226 * (maybe put on by HALT-ing the board in the previous session).
228 * Force enable debug entry for this session.
230 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
231 target
->state
= TARGET_HALTED
;
232 retval
= mips_m4k_debug_entry(target
);
233 if (retval
!= ERROR_OK
)
237 ((prev_target_state
== TARGET_RUNNING
)
238 || (prev_target_state
== TARGET_RESET
))) {
239 retval
= update_halt_gdb(target
);
240 if (retval
!= ERROR_OK
)
243 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
244 } else if (target
->state
== TARGET_DEBUG_RUNNING
) {
245 target
->state
= TARGET_HALTED
;
247 retval
= mips_m4k_debug_entry(target
);
248 if (retval
!= ERROR_OK
)
252 retval
= update_halt_gdb(target
);
253 if (retval
!= ERROR_OK
)
257 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
260 target
->state
= TARGET_RUNNING
;
262 /* LOG_DEBUG("ctrl = 0x%08X", ejtag_ctrl); */
267 static int mips_m4k_halt(struct target
*target
)
269 struct mips32_common
*mips32
= target_to_mips32(target
);
270 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
272 LOG_DEBUG("target->state: %s", target_state_name(target
));
274 if (target
->state
== TARGET_HALTED
) {
275 LOG_DEBUG("target was already halted");
279 if (target
->state
== TARGET_UNKNOWN
)
280 LOG_WARNING("target was in unknown state when halt was requested");
282 if (target
->state
== TARGET_RESET
) {
283 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
284 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
285 return ERROR_TARGET_FAILURE
;
287 /* we came here in a reset_halt or reset_init sequence
288 * debug entry was already prepared in mips_m4k_assert_reset()
290 target
->debug_reason
= DBG_REASON_DBGRQ
;
296 /* break processor */
297 mips_ejtag_enter_debug(ejtag_info
);
299 target
->debug_reason
= DBG_REASON_DBGRQ
;
304 static int mips_m4k_assert_reset(struct target
*target
)
306 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
307 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
309 /* TODO: apply hw reset signal in not examined state */
310 if (!(target_was_examined(target
))) {
311 LOG_WARNING("Reset is not asserted because the target is not examined.");
312 LOG_WARNING("Use a reset button or power cycle the target.");
313 return ERROR_TARGET_NOT_EXAMINED
;
316 LOG_DEBUG("target->state: %s",
317 target_state_name(target
));
319 enum reset_types jtag_reset_config
= jtag_get_reset_config();
321 /* some cores support connecting while srst is asserted
322 * use that mode is it has been configured */
324 bool srst_asserted
= false;
326 if (!(jtag_reset_config
& RESET_SRST_PULLS_TRST
) &&
327 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
328 jtag_add_reset(0, 1);
329 srst_asserted
= true;
333 /* EJTAG before v2.5/2.6 does not support EJTAGBOOT or NORMALBOOT */
334 if (ejtag_info
->ejtag_version
!= EJTAG_VERSION_20
) {
335 if (target
->reset_halt
) {
336 /* use hardware to catch reset */
337 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_EJTAGBOOT
);
339 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_NORMALBOOT
);
342 if (jtag_reset_config
& RESET_HAS_SRST
) {
343 /* here we should issue a srst only, but we may have to assert trst as well */
344 if (jtag_reset_config
& RESET_SRST_PULLS_TRST
)
345 jtag_add_reset(1, 1);
346 else if (!srst_asserted
)
347 jtag_add_reset(0, 1);
348 } else if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
349 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
351 if (mips_m4k
->is_pic32mx
) {
352 LOG_DEBUG("Using MTAP reset to reset processor...");
354 /* use microchip specific MTAP reset */
355 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_MTAP
);
356 mips_ejtag_set_instr(ejtag_info
, MTAP_COMMAND
);
358 mips_ejtag_drscan_8_out(ejtag_info
, MCHP_ASERT_RST
);
359 mips_ejtag_drscan_8_out(ejtag_info
, MCHP_DE_ASSERT_RST
);
360 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
362 /* use ejtag reset - not supported by all cores */
363 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
| EJTAG_CTRL_PRRST
| EJTAG_CTRL_PERRST
;
364 LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
365 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
366 mips_ejtag_drscan_32_out(ejtag_info
, ejtag_ctrl
);
370 target
->state
= TARGET_RESET
;
371 jtag_add_sleep(50000);
373 register_cache_invalidate(mips_m4k
->mips32
.core_cache
);
375 if (target
->reset_halt
) {
376 int retval
= target_halt(target
);
377 if (retval
!= ERROR_OK
)
384 static int mips_m4k_deassert_reset(struct target
*target
)
386 LOG_DEBUG("target->state: %s", target_state_name(target
));
388 /* deassert reset lines */
389 jtag_add_reset(0, 0);
394 static int mips_m4k_single_step_core(struct target
*target
)
396 struct mips32_common
*mips32
= target_to_mips32(target
);
397 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
399 /* configure single step mode */
400 mips_ejtag_config_step(ejtag_info
, 1);
402 /* disable interrupts while stepping */
403 mips32_enable_interrupts(target
, 0);
405 /* exit debug mode */
406 mips_ejtag_exit_debug(ejtag_info
);
408 mips_m4k_debug_entry(target
);
413 static int mips_m4k_restore_smp(struct target
*target
, uint32_t address
, int handle_breakpoints
)
415 int retval
= ERROR_OK
;
416 struct target_list
*head
;
420 while (head
!= (struct target_list
*)NULL
) {
423 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
)) {
424 /* resume current address , not in step mode */
425 ret
= mips_m4k_internal_restore(curr
, 1, address
,
426 handle_breakpoints
, 0);
428 if (ret
!= ERROR_OK
) {
429 LOG_ERROR("target->coreid :%" PRId32
" failed to resume at address :0x%" PRIx32
,
430 curr
->coreid
, address
);
439 static int mips_m4k_internal_restore(struct target
*target
, int current
,
440 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
442 struct mips32_common
*mips32
= target_to_mips32(target
);
443 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
444 struct breakpoint
*breakpoint
= NULL
;
447 if (target
->state
!= TARGET_HALTED
) {
448 LOG_WARNING("target not halted");
449 return ERROR_TARGET_NOT_HALTED
;
452 if (!debug_execution
) {
453 target_free_all_working_areas(target
);
454 mips_m4k_enable_breakpoints(target
);
455 mips_m4k_enable_watchpoints(target
);
458 /* current = 1: continue on current pc, otherwise continue at <address> */
460 mips_m4k_isa_filter(mips32
->isa_imp
, &address
);
461 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
462 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= true;
463 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= true;
466 if ((mips32
->isa_imp
> 1) && debug_execution
) /* if more than one isa supported */
467 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 1, mips32
->isa_mode
);
472 resume_pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
474 mips32_restore_context(target
);
476 /* the front-end may request us not to handle breakpoints */
477 if (handle_breakpoints
) {
478 /* Single step past breakpoint at current address */
479 breakpoint
= breakpoint_find(target
, resume_pc
);
481 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT
"",
482 breakpoint
->address
);
483 mips_m4k_unset_breakpoint(target
, breakpoint
);
484 mips_m4k_single_step_core(target
);
485 mips_m4k_set_breakpoint(target
, breakpoint
);
489 /* enable interrupts if we are running */
490 mips32_enable_interrupts(target
, !debug_execution
);
492 /* exit debug mode */
493 mips_ejtag_exit_debug(ejtag_info
);
494 target
->debug_reason
= DBG_REASON_NOTHALTED
;
496 /* registers are now invalid */
497 register_cache_invalidate(mips32
->core_cache
);
499 if (!debug_execution
) {
500 target
->state
= TARGET_RUNNING
;
501 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
502 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
504 target
->state
= TARGET_DEBUG_RUNNING
;
505 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
506 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
512 static int mips_m4k_resume(struct target
*target
, int current
,
513 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
515 int retval
= ERROR_OK
;
517 /* dummy resume for smp toggle in order to reduce gdb impact */
518 if ((target
->smp
) && (target
->gdb_service
->core
[1] != -1)) {
519 /* simulate a start and halt of target */
520 target
->gdb_service
->target
= NULL
;
521 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
522 /* fake resume at next poll we play the target core[1], see poll*/
523 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
527 retval
= mips_m4k_internal_restore(target
, current
, address
,
531 if (retval
== ERROR_OK
&& target
->smp
) {
532 target
->gdb_service
->core
[0] = -1;
533 retval
= mips_m4k_restore_smp(target
, address
, handle_breakpoints
);
539 static int mips_m4k_step(struct target
*target
, int current
,
540 target_addr_t address
, int handle_breakpoints
)
542 /* get pointers to arch-specific information */
543 struct mips32_common
*mips32
= target_to_mips32(target
);
544 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
545 struct breakpoint
*breakpoint
= NULL
;
547 if (target
->state
!= TARGET_HALTED
) {
548 LOG_WARNING("target not halted");
549 return ERROR_TARGET_NOT_HALTED
;
552 /* current = 1: continue on current pc, otherwise continue at <address> */
554 mips_m4k_isa_filter(mips32
->isa_imp
, &address
);
555 buf_set_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32, address
);
556 mips32
->core_cache
->reg_list
[MIPS32_PC
].dirty
= true;
557 mips32
->core_cache
->reg_list
[MIPS32_PC
].valid
= true;
560 /* the front-end may request us not to handle breakpoints */
561 if (handle_breakpoints
) {
562 breakpoint
= breakpoint_find(target
,
563 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
565 mips_m4k_unset_breakpoint(target
, breakpoint
);
568 /* restore context */
569 mips32_restore_context(target
);
571 /* configure single step mode */
572 mips_ejtag_config_step(ejtag_info
, 1);
574 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
576 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
578 /* disable interrupts while stepping */
579 mips32_enable_interrupts(target
, 0);
581 /* exit debug mode */
582 mips_ejtag_exit_debug(ejtag_info
);
584 /* registers are now invalid */
585 register_cache_invalidate(mips32
->core_cache
);
587 LOG_DEBUG("target stepped ");
588 mips_m4k_debug_entry(target
);
591 mips_m4k_set_breakpoint(target
, breakpoint
);
593 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
598 static void mips_m4k_enable_breakpoints(struct target
*target
)
600 struct breakpoint
*breakpoint
= target
->breakpoints
;
602 /* set any pending breakpoints */
604 if (breakpoint
->set
== 0)
605 mips_m4k_set_breakpoint(target
, breakpoint
);
606 breakpoint
= breakpoint
->next
;
610 static int mips_m4k_set_breakpoint(struct target
*target
,
611 struct breakpoint
*breakpoint
)
613 struct mips32_common
*mips32
= target_to_mips32(target
);
614 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
615 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
618 if (breakpoint
->set
) {
619 LOG_WARNING("breakpoint already set");
623 if (breakpoint
->type
== BKPT_HARD
) {
626 while (comparator_list
[bp_num
].used
&& (bp_num
< mips32
->num_inst_bpoints
))
628 if (bp_num
>= mips32
->num_inst_bpoints
) {
629 LOG_ERROR("Can not find free FP Comparator(bpid: %" PRIu32
")",
630 breakpoint
->unique_id
);
631 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
633 breakpoint
->set
= bp_num
+ 1;
634 comparator_list
[bp_num
].used
= 1;
635 comparator_list
[bp_num
].bp_value
= breakpoint
->address
;
637 if (breakpoint
->length
!= 4) /* make sure isa bit set */
638 comparator_list
[bp_num
].bp_value
|= 1;
639 else /* make sure isa bit cleared */
640 comparator_list
[bp_num
].bp_value
&= ~1;
642 /* EJTAG 2.0 uses 30bit IBA. First 2 bits are reserved.
643 * Warning: there is no IB ASID registers in 2.0.
644 * Do not set it! :) */
645 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
)
646 comparator_list
[bp_num
].bp_value
&= 0xFFFFFFFC;
648 target_write_u32(target
, comparator_list
[bp_num
].reg_address
,
649 comparator_list
[bp_num
].bp_value
);
650 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
651 ejtag_info
->ejtag_ibm_offs
, 0x00000000);
652 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
653 ejtag_info
->ejtag_ibc_offs
, 1);
654 LOG_DEBUG("bpid: %" PRIu32
", bp_num %i bp_value 0x%" PRIx32
"",
655 breakpoint
->unique_id
,
656 bp_num
, comparator_list
[bp_num
].bp_value
);
657 } else if (breakpoint
->type
== BKPT_SOFT
) {
658 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
660 uint32_t isa_req
= breakpoint
->length
& 1; /* micro mips request bit */
661 uint32_t bplength
= breakpoint
->length
& ~1; /* drop micro mips request bit for length */
662 uint32_t bpaddr
= breakpoint
->address
& ~1; /* drop isa bit from address, if set */
665 uint32_t verify
= 0xffffffff;
666 uint32_t sdbbp32_instr
= MIPS32_SDBBP(isa_req
);
667 if (ejtag_info
->endianness
&& isa_req
)
668 sdbbp32_instr
= SWAP16(sdbbp32_instr
);
670 if ((breakpoint
->address
& 3) == 0) { /* word aligned */
672 retval
= target_read_memory(target
, bpaddr
, bplength
, 1, breakpoint
->orig_instr
);
673 if (retval
!= ERROR_OK
)
676 retval
= target_write_u32(target
, bpaddr
, sdbbp32_instr
);
677 if (retval
!= ERROR_OK
)
680 retval
= target_read_u32(target
, bpaddr
, &verify
);
681 if (retval
!= ERROR_OK
)
684 if (verify
!= sdbbp32_instr
)
687 } else { /* 16 bit aligned */
688 retval
= target_read_memory(target
, bpaddr
, 2, 2, breakpoint
->orig_instr
);
689 if (retval
!= ERROR_OK
)
692 uint8_t sdbbp_buf
[4];
693 target_buffer_set_u32(target
, sdbbp_buf
, sdbbp32_instr
);
695 retval
= target_write_memory(target
, bpaddr
, 2, 2, sdbbp_buf
);
696 if (retval
!= ERROR_OK
)
699 retval
= target_read_memory(target
, bpaddr
, 2, 2, sdbbp_buf
);
700 if (retval
!= ERROR_OK
)
703 if (target_buffer_get_u32(target
, sdbbp_buf
) != sdbbp32_instr
)
708 LOG_ERROR("Unable to set 32bit breakpoint at address %08" TARGET_PRIxADDR
709 " - check that memory is read/writable", breakpoint
->address
);
714 uint16_t verify
= 0xffff;
716 retval
= target_read_memory(target
, bpaddr
, bplength
, 1, breakpoint
->orig_instr
);
717 if (retval
!= ERROR_OK
)
720 retval
= target_write_u16(target
, bpaddr
, MIPS16_SDBBP(isa_req
));
721 if (retval
!= ERROR_OK
)
724 retval
= target_read_u16(target
, bpaddr
, &verify
);
725 if (retval
!= ERROR_OK
)
728 if (verify
!= MIPS16_SDBBP(isa_req
)) {
729 LOG_ERROR("Unable to set 16bit breakpoint at address %08" TARGET_PRIxADDR
730 " - check that memory is read/writable", breakpoint
->address
);
735 breakpoint
->set
= 20; /* Any nice value but 0 */
741 static int mips_m4k_unset_breakpoint(struct target
*target
,
742 struct breakpoint
*breakpoint
)
744 /* get pointers to arch-specific information */
745 struct mips32_common
*mips32
= target_to_mips32(target
);
746 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
747 struct mips32_comparator
*comparator_list
= mips32
->inst_break_list
;
750 if (!breakpoint
->set
) {
751 LOG_WARNING("breakpoint not set");
755 if (breakpoint
->type
== BKPT_HARD
) {
756 int bp_num
= breakpoint
->set
- 1;
757 if ((bp_num
< 0) || (bp_num
>= mips32
->num_inst_bpoints
)) {
758 LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32
")",
759 breakpoint
->unique_id
);
762 LOG_DEBUG("bpid: %" PRIu32
" - releasing hw: %d",
763 breakpoint
->unique_id
,
765 comparator_list
[bp_num
].used
= 0;
766 comparator_list
[bp_num
].bp_value
= 0;
767 target_write_u32(target
, comparator_list
[bp_num
].reg_address
+
768 ejtag_info
->ejtag_ibc_offs
, 0);
771 /* restore original instruction (kept in target endianness) */
772 uint32_t isa_req
= breakpoint
->length
& 1;
773 uint32_t bplength
= breakpoint
->length
& ~1;
774 uint8_t current_instr
[4];
775 LOG_DEBUG("bpid: %" PRIu32
, breakpoint
->unique_id
);
777 uint32_t sdbbp32_instr
= MIPS32_SDBBP(isa_req
);
778 if (ejtag_info
->endianness
&& isa_req
)
779 sdbbp32_instr
= SWAP16(sdbbp32_instr
);
781 if ((breakpoint
->address
& 3) == 0) { /* 32bit aligned */
782 /* check that user program has not modified breakpoint instruction */
783 retval
= target_read_memory(target
, breakpoint
->address
, 4, 1, current_instr
);
784 if (retval
!= ERROR_OK
)
787 * target_read_memory() gets us data in _target_ endianness.
788 * If we want to use this data on the host for comparisons with some macros
789 * we must first transform it to _host_ endianness using target_buffer_get_u16().
791 if (sdbbp32_instr
== target_buffer_get_u32(target
, current_instr
)) {
792 retval
= target_write_memory(target
, breakpoint
->address
, 4, 1,
793 breakpoint
->orig_instr
);
794 if (retval
!= ERROR_OK
)
797 } else { /* 16bit aligned */
798 retval
= target_read_memory(target
, breakpoint
->address
, 2, 2, current_instr
);
799 if (retval
!= ERROR_OK
)
802 if (sdbbp32_instr
== target_buffer_get_u32(target
, current_instr
)) {
803 retval
= target_write_memory(target
, breakpoint
->address
, 2, 2,
804 breakpoint
->orig_instr
);
805 if (retval
!= ERROR_OK
)
810 /* check that user program has not modified breakpoint instruction */
811 retval
= target_read_memory(target
, breakpoint
->address
, 2, 1, current_instr
);
812 if (retval
!= ERROR_OK
)
815 if (target_buffer_get_u16(target
, current_instr
) == MIPS16_SDBBP(isa_req
)) {
816 retval
= target_write_memory(target
, breakpoint
->address
, 2, 1,
817 breakpoint
->orig_instr
);
818 if (retval
!= ERROR_OK
)
829 static int mips_m4k_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
831 struct mips32_common
*mips32
= target_to_mips32(target
);
833 if ((breakpoint
->length
> 5 || breakpoint
->length
< 2) || /* out of range */
834 (breakpoint
->length
== 4 && (breakpoint
->address
& 2)) || /* mips32 unaligned */
835 (mips32
->isa_imp
== MIPS32_ONLY
&& breakpoint
->length
!= 4) || /* misp32 specific */
836 ((mips32
->isa_imp
& 1) != (breakpoint
->length
& 1))) /* isa not implemented */
837 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
839 if (breakpoint
->type
== BKPT_HARD
) {
840 if (mips32
->num_inst_bpoints_avail
< 1) {
841 LOG_INFO("no hardware breakpoint available");
842 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
845 mips32
->num_inst_bpoints_avail
--;
848 return mips_m4k_set_breakpoint(target
, breakpoint
);
851 static int mips_m4k_remove_breakpoint(struct target
*target
,
852 struct breakpoint
*breakpoint
)
854 /* get pointers to arch-specific information */
855 struct mips32_common
*mips32
= target_to_mips32(target
);
857 if (target
->state
!= TARGET_HALTED
) {
858 LOG_WARNING("target not halted");
859 return ERROR_TARGET_NOT_HALTED
;
863 mips_m4k_unset_breakpoint(target
, breakpoint
);
865 if (breakpoint
->type
== BKPT_HARD
)
866 mips32
->num_inst_bpoints_avail
++;
871 static int mips_m4k_set_watchpoint(struct target
*target
,
872 struct watchpoint
*watchpoint
)
874 struct mips32_common
*mips32
= target_to_mips32(target
);
875 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
876 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
879 * watchpoint enabled, ignore all byte lanes in value register
880 * and exclude both load and store accesses from watchpoint
881 * condition evaluation
883 int enable
= EJTAG_DBCN_NOSB
| EJTAG_DBCN_NOLB
| EJTAG_DBCN_BE
|
884 (0xff << EJTAG_DBCN_BLM_SHIFT
);
886 if (watchpoint
->set
) {
887 LOG_WARNING("watchpoint already set");
891 while (comparator_list
[wp_num
].used
&& (wp_num
< mips32
->num_data_bpoints
))
893 if (wp_num
>= mips32
->num_data_bpoints
) {
894 LOG_ERROR("Can not find free FP Comparator");
898 if (watchpoint
->length
!= 4) {
899 LOG_ERROR("Only watchpoints of length 4 are supported");
900 return ERROR_TARGET_UNALIGNED_ACCESS
;
903 if (watchpoint
->address
% 4) {
904 LOG_ERROR("Watchpoints address should be word aligned");
905 return ERROR_TARGET_UNALIGNED_ACCESS
;
908 switch (watchpoint
->rw
) {
910 enable
&= ~EJTAG_DBCN_NOLB
;
913 enable
&= ~EJTAG_DBCN_NOSB
;
916 enable
&= ~(EJTAG_DBCN_NOLB
| EJTAG_DBCN_NOSB
);
919 LOG_ERROR("BUG: watchpoint->rw neither read, write nor access");
922 watchpoint
->set
= wp_num
+ 1;
923 comparator_list
[wp_num
].used
= 1;
924 comparator_list
[wp_num
].bp_value
= watchpoint
->address
;
926 /* EJTAG 2.0 uses 29bit DBA. First 3 bits are reserved.
927 * There is as well no ASID register support. */
928 if (ejtag_info
->ejtag_version
== EJTAG_VERSION_20
)
929 comparator_list
[wp_num
].bp_value
&= 0xFFFFFFF8;
931 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
932 ejtag_info
->ejtag_dbasid_offs
, 0x00000000);
934 target_write_u32(target
, comparator_list
[wp_num
].reg_address
,
935 comparator_list
[wp_num
].bp_value
);
936 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
937 ejtag_info
->ejtag_dbm_offs
, 0x00000000);
939 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
940 ejtag_info
->ejtag_dbc_offs
, enable
);
941 /* TODO: probably this value is ignored on 2.0 */
942 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
943 ejtag_info
->ejtag_dbv_offs
, 0);
944 LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32
"", wp_num
, comparator_list
[wp_num
].bp_value
);
949 static int mips_m4k_unset_watchpoint(struct target
*target
,
950 struct watchpoint
*watchpoint
)
952 /* get pointers to arch-specific information */
953 struct mips32_common
*mips32
= target_to_mips32(target
);
954 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
955 struct mips32_comparator
*comparator_list
= mips32
->data_break_list
;
957 if (!watchpoint
->set
) {
958 LOG_WARNING("watchpoint not set");
962 int wp_num
= watchpoint
->set
- 1;
963 if ((wp_num
< 0) || (wp_num
>= mips32
->num_data_bpoints
)) {
964 LOG_DEBUG("Invalid FP Comparator number in watchpoint");
967 comparator_list
[wp_num
].used
= 0;
968 comparator_list
[wp_num
].bp_value
= 0;
969 target_write_u32(target
, comparator_list
[wp_num
].reg_address
+
970 ejtag_info
->ejtag_dbc_offs
, 0);
976 static int mips_m4k_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
978 struct mips32_common
*mips32
= target_to_mips32(target
);
980 if (mips32
->num_data_bpoints_avail
< 1) {
981 LOG_INFO("no hardware watchpoints available");
982 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
985 mips32
->num_data_bpoints_avail
--;
987 mips_m4k_set_watchpoint(target
, watchpoint
);
991 static int mips_m4k_remove_watchpoint(struct target
*target
,
992 struct watchpoint
*watchpoint
)
994 /* get pointers to arch-specific information */
995 struct mips32_common
*mips32
= target_to_mips32(target
);
997 if (target
->state
!= TARGET_HALTED
) {
998 LOG_WARNING("target not halted");
999 return ERROR_TARGET_NOT_HALTED
;
1002 if (watchpoint
->set
)
1003 mips_m4k_unset_watchpoint(target
, watchpoint
);
1005 mips32
->num_data_bpoints_avail
++;
1010 static void mips_m4k_enable_watchpoints(struct target
*target
)
1012 struct watchpoint
*watchpoint
= target
->watchpoints
;
1014 /* set any pending watchpoints */
1015 while (watchpoint
) {
1016 if (watchpoint
->set
== 0)
1017 mips_m4k_set_watchpoint(target
, watchpoint
);
1018 watchpoint
= watchpoint
->next
;
1022 static int mips_m4k_read_memory(struct target
*target
, target_addr_t address
,
1023 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1025 struct mips32_common
*mips32
= target_to_mips32(target
);
1026 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1028 LOG_DEBUG("address: " TARGET_ADDR_FMT
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
1029 address
, size
, count
);
1031 if (target
->state
!= TARGET_HALTED
) {
1032 LOG_WARNING("target not halted");
1033 return ERROR_TARGET_NOT_HALTED
;
1036 /* sanitize arguments */
1037 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1038 return ERROR_COMMAND_SYNTAX_ERROR
;
1040 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1041 return ERROR_TARGET_UNALIGNED_ACCESS
;
1043 /* since we don't know if buffer is aligned, we allocate new mem that is always aligned */
1047 t
= malloc(count
* size
* sizeof(uint8_t));
1049 LOG_ERROR("Out of memory");
1055 /* if noDMA off, use DMAACC mode for memory read */
1057 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
1058 retval
= mips32_pracc_read_mem(ejtag_info
, address
, size
, count
, t
);
1060 retval
= mips32_dmaacc_read_mem(ejtag_info
, address
, size
, count
, t
);
1062 /* mips32_..._read_mem with size 4/2 returns uint32_t/uint16_t in host */
1063 /* endianness, but byte array should represent target endianness */
1064 if (retval
== ERROR_OK
) {
1067 target_buffer_set_u32_array(target
, buffer
, count
, t
);
1070 target_buffer_set_u16_array(target
, buffer
, count
, t
);
1081 static int mips_m4k_write_memory(struct target
*target
, target_addr_t address
,
1082 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1084 struct mips32_common
*mips32
= target_to_mips32(target
);
1085 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1087 LOG_DEBUG("address: " TARGET_ADDR_FMT
", size: 0x%8.8" PRIx32
", count: 0x%8.8" PRIx32
"",
1088 address
, size
, count
);
1090 if (target
->state
!= TARGET_HALTED
) {
1091 LOG_WARNING("target not halted");
1092 return ERROR_TARGET_NOT_HALTED
;
1095 if (size
== 4 && count
> 32) {
1096 int retval
= mips_m4k_bulk_write_memory(target
, address
, count
, buffer
);
1097 if (retval
== ERROR_OK
)
1099 LOG_WARNING("Falling back to non-bulk write");
1102 /* sanitize arguments */
1103 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
1104 return ERROR_COMMAND_SYNTAX_ERROR
;
1106 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1107 return ERROR_TARGET_UNALIGNED_ACCESS
;
1109 /** correct endianness if we have word or hword access */
1112 /* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
1113 /* endianness, but byte array represents target endianness */
1114 t
= malloc(count
* size
* sizeof(uint8_t));
1116 LOG_ERROR("Out of memory");
1122 target_buffer_get_u32_array(target
, buffer
, count
, (uint32_t *)t
);
1125 target_buffer_get_u16_array(target
, buffer
, count
, (uint16_t *)t
);
1131 /* if noDMA off, use DMAACC mode for memory write */
1133 if (ejtag_info
->impcode
& EJTAG_IMP_NODMA
)
1134 retval
= mips32_pracc_write_mem(ejtag_info
, address
, size
, count
, buffer
);
1136 retval
= mips32_dmaacc_write_mem(ejtag_info
, address
, size
, count
, buffer
);
1140 if (retval
!= ERROR_OK
)
1146 static int mips_m4k_init_target(struct command_context
*cmd_ctx
,
1147 struct target
*target
)
1149 mips32_build_reg_cache(target
);
1154 static int mips_m4k_init_arch_info(struct target
*target
,
1155 struct mips_m4k_common
*mips_m4k
, struct jtag_tap
*tap
)
1157 struct mips32_common
*mips32
= &mips_m4k
->mips32
;
1159 mips_m4k
->common_magic
= MIPSM4K_COMMON_MAGIC
;
1161 /* initialize mips4k specific info */
1162 mips32_init_arch_info(target
, mips32
, tap
);
1163 mips32
->arch_info
= mips_m4k
;
1168 static int mips_m4k_target_create(struct target
*target
, Jim_Interp
*interp
)
1170 struct mips_m4k_common
*mips_m4k
= calloc(1, sizeof(struct mips_m4k_common
));
1172 mips_m4k_init_arch_info(target
, mips_m4k
, target
->tap
);
1177 static int mips_m4k_examine(struct target
*target
)
1179 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1180 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1182 if (!target_was_examined(target
)) {
1183 int retval
= mips_ejtag_get_idcode(ejtag_info
);
1184 if (retval
!= ERROR_OK
) {
1185 LOG_ERROR("idcode read failed");
1188 if (((ejtag_info
->idcode
>> 1) & 0x7FF) == 0x29) {
1189 /* we are using a pic32mx so select ejtag port
1190 * as it is not selected by default */
1191 mips_ejtag_set_instr(ejtag_info
, MTAP_SW_ETAP
);
1192 LOG_DEBUG("PIC32 Detected - using EJTAG Interface");
1193 mips_m4k
->is_pic32mx
= true;
1197 /* init rest of ejtag interface */
1198 int retval
= mips_ejtag_init(ejtag_info
);
1199 if (retval
!= ERROR_OK
)
1202 return mips32_examine(target
);
1205 static int mips_m4k_bulk_write_memory(struct target
*target
, target_addr_t address
,
1206 uint32_t count
, const uint8_t *buffer
)
1208 struct mips32_common
*mips32
= target_to_mips32(target
);
1209 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
1210 struct working_area
*fast_data_area
;
1214 LOG_DEBUG("address: " TARGET_ADDR_FMT
", count: 0x%8.8" PRIx32
"",
1217 /* check alignment */
1219 return ERROR_TARGET_UNALIGNED_ACCESS
;
1221 if (!mips32
->fast_data_area
) {
1222 /* Get memory for block write handler
1223 * we preserve this area between calls and gain a speed increase
1224 * of about 3kb/sec when writing flash
1225 * this will be released/nulled by the system when the target is resumed or reset */
1226 retval
= target_alloc_working_area(target
,
1227 MIPS32_FASTDATA_HANDLER_SIZE
,
1228 &mips32
->fast_data_area
);
1229 if (retval
!= ERROR_OK
) {
1230 LOG_ERROR("No working area available");
1234 /* reset fastadata state so the algo get reloaded */
1235 ejtag_info
->fast_access_save
= -1;
1238 fast_data_area
= mips32
->fast_data_area
;
1240 if (address
<= fast_data_area
->address
+ fast_data_area
->size
&&
1241 fast_data_area
->address
<= address
+ count
) {
1242 LOG_ERROR("fast_data (" TARGET_ADDR_FMT
") is within write area "
1243 "(" TARGET_ADDR_FMT
"-" TARGET_ADDR_FMT
").",
1244 fast_data_area
->address
, address
, address
+ count
);
1245 LOG_ERROR("Change work-area-phys or load_image address!");
1249 /* mips32_pracc_fastdata_xfer requires uint32_t in host endianness, */
1250 /* but byte array represents target endianness */
1252 t
= malloc(count
* sizeof(uint32_t));
1254 LOG_ERROR("Out of memory");
1258 target_buffer_get_u32_array(target
, buffer
, count
, t
);
1260 retval
= mips32_pracc_fastdata_xfer(ejtag_info
, mips32
->fast_data_area
, write_t
, address
,
1265 if (retval
!= ERROR_OK
)
1266 LOG_ERROR("Fastdata access Failed");
1271 static int mips_m4k_verify_pointer(struct command_invocation
*cmd
,
1272 struct mips_m4k_common
*mips_m4k
)
1274 if (mips_m4k
->common_magic
!= MIPSM4K_COMMON_MAGIC
) {
1275 command_print(cmd
, "target is not an MIPS_M4K");
1276 return ERROR_TARGET_INVALID
;
1281 COMMAND_HANDLER(mips_m4k_handle_cp0_command
)
1284 struct target
*target
= get_current_target(CMD_CTX
);
1285 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1286 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1288 retval
= mips_m4k_verify_pointer(CMD
, mips_m4k
);
1289 if (retval
!= ERROR_OK
)
1292 if (target
->state
!= TARGET_HALTED
) {
1293 command_print(CMD
, "target must be stopped for \"%s\" command", CMD_NAME
);
1297 /* two or more argument, access a single register/select (write if third argument is given) */
1299 return ERROR_COMMAND_SYNTAX_ERROR
;
1301 uint32_t cp0_reg
, cp0_sel
;
1302 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], cp0_reg
);
1303 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], cp0_sel
);
1305 if (CMD_ARGC
== 2) {
1307 retval
= mips32_cp0_read(ejtag_info
, &value
, cp0_reg
, cp0_sel
);
1308 if (retval
!= ERROR_OK
) {
1310 "couldn't access reg %" PRIu32
,
1314 command_print(CMD
, "cp0 reg %" PRIu32
", select %" PRIu32
": %8.8" PRIx32
,
1315 cp0_reg
, cp0_sel
, value
);
1317 } else if (CMD_ARGC
== 3) {
1319 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
1320 retval
= mips32_cp0_write(ejtag_info
, value
, cp0_reg
, cp0_sel
);
1321 if (retval
!= ERROR_OK
) {
1323 "couldn't access cp0 reg %" PRIu32
", select %" PRIu32
,
1327 command_print(CMD
, "cp0 reg %" PRIu32
", select %" PRIu32
": %8.8" PRIx32
,
1328 cp0_reg
, cp0_sel
, value
);
1335 COMMAND_HANDLER(mips_m4k_handle_scan_delay_command
)
1337 struct target
*target
= get_current_target(CMD_CTX
);
1338 struct mips_m4k_common
*mips_m4k
= target_to_m4k(target
);
1339 struct mips_ejtag
*ejtag_info
= &mips_m4k
->mips32
.ejtag_info
;
1342 COMMAND_PARSE_NUMBER(uint
, CMD_ARGV
[0], ejtag_info
->scan_delay
);
1343 else if (CMD_ARGC
> 1)
1344 return ERROR_COMMAND_SYNTAX_ERROR
;
1346 command_print(CMD
, "scan delay: %d nsec", ejtag_info
->scan_delay
);
1347 if (ejtag_info
->scan_delay
>= MIPS32_SCAN_DELAY_LEGACY_MODE
) {
1348 ejtag_info
->mode
= 0;
1349 command_print(CMD
, "running in legacy mode");
1351 ejtag_info
->mode
= 1;
1352 command_print(CMD
, "running in fast queued mode");
1358 static const struct command_registration mips_m4k_exec_command_handlers
[] = {
1361 .handler
= mips_m4k_handle_cp0_command
,
1362 .mode
= COMMAND_EXEC
,
1363 .usage
= "regnum [value]",
1364 .help
= "display/modify cp0 register",
1367 .name
= "scan_delay",
1368 .handler
= mips_m4k_handle_scan_delay_command
,
1369 .mode
= COMMAND_ANY
,
1370 .help
= "display/set scan delay in nano seconds",
1374 .chain
= smp_command_handlers
,
1376 COMMAND_REGISTRATION_DONE
1379 const struct command_registration mips_m4k_command_handlers
[] = {
1381 .chain
= mips32_command_handlers
,
1385 .mode
= COMMAND_ANY
,
1386 .help
= "mips_m4k command group",
1388 .chain
= mips_m4k_exec_command_handlers
,
1390 COMMAND_REGISTRATION_DONE
1393 struct target_type mips_m4k_target
= {
1396 .poll
= mips_m4k_poll
,
1397 .arch_state
= mips32_arch_state
,
1399 .halt
= mips_m4k_halt
,
1400 .resume
= mips_m4k_resume
,
1401 .step
= mips_m4k_step
,
1403 .assert_reset
= mips_m4k_assert_reset
,
1404 .deassert_reset
= mips_m4k_deassert_reset
,
1406 .get_gdb_reg_list
= mips32_get_gdb_reg_list
,
1408 .read_memory
= mips_m4k_read_memory
,
1409 .write_memory
= mips_m4k_write_memory
,
1410 .checksum_memory
= mips32_checksum_memory
,
1411 .blank_check_memory
= mips32_blank_check_memory
,
1413 .run_algorithm
= mips32_run_algorithm
,
1415 .add_breakpoint
= mips_m4k_add_breakpoint
,
1416 .remove_breakpoint
= mips_m4k_remove_breakpoint
,
1417 .add_watchpoint
= mips_m4k_add_watchpoint
,
1418 .remove_watchpoint
= mips_m4k_remove_watchpoint
,
1420 .commands
= mips_m4k_command_handlers
,
1421 .target_create
= mips_m4k_target_create
,
1422 .init_target
= mips_m4k_init_target
,
1423 .examine
= mips_m4k_examine
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)