1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2009 by David N. Claffey <dnclaffey@gmail.com> *
9 * Copyright (C) 2011 by Drasko DRASKOVIC *
10 * drasko.draskovic@gmail.com *
12 * This program is free software; you can redistribute it and/or modify *
13 * it under the terms of the GNU General Public License as published by *
14 * the Free Software Foundation; either version 2 of the License, or *
15 * (at your option) any later version. *
17 * This program is distributed in the hope that it will be useful, *
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
20 * GNU General Public License for more details. *
22 * You should have received a copy of the GNU General Public License *
23 * along with this program; if not, write to the *
24 * Free Software Foundation, Inc., *
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
26 ***************************************************************************/
29 * This version has optimized assembly routines for 32 bit operations:
32 * - write array of words
34 * One thing to be aware of is that the MIPS32 cpu will execute the
35 * instruction after a branch instruction (one delay slot).
42 * The LW $1, ($2 +100) instruction is also executed. If this is
43 * not wanted a NOP can be inserted:
50 * or the code can be changed to:
56 * The original code contained NOPs. I have removed these and moved
59 * These changes result in a 35% speed increase when programming an
62 * More improvement could be gained if the registers do no need
63 * to be preserved but in that case the routines should be aware
64 * OpenOCD is used as a flash programmer or as a debug tool.
73 #include <helper/time_support.h>
76 #include "mips32_pracc.h"
78 struct mips32_pracc_context
{
79 uint32_t *local_oparam
;
85 struct mips_ejtag
*ejtag_info
;
88 static int wait_for_pracc_rw(struct mips_ejtag
*ejtag_info
, uint32_t *ctrl
)
91 long long then
= timeval_ms();
93 /* wait for the PrAcc to become "1" */
94 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
97 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
;
98 int retval
= mips_ejtag_drscan_32(ejtag_info
, &ejtag_ctrl
);
99 if (retval
!= ERROR_OK
)
102 if (ejtag_ctrl
& EJTAG_CTRL_PRACC
)
105 int timeout
= timeval_ms() - then
;
106 if (timeout
> 1000) {
107 LOG_DEBUG("DEBUGMODULE: No memory access in progress!");
108 return ERROR_JTAG_DEVICE_ERROR
;
116 static int mips32_pracc_exec_read(struct mips32_pracc_context
*ctx
, uint32_t address
)
120 if ((address
>= MIPS32_PRACC_TEXT
)
121 && (address
< MIPS32_PRACC_TEXT
+ ctx
->code_len
* 4)) {
122 int offset
= (address
- MIPS32_PRACC_TEXT
) / 4;
123 code
= ctx
->code
[offset
];
124 } else if (address
>= 0xFF200000) {
125 /* CPU keeps reading at the end of execution.
126 * If we after 0xF0000000 address range, we can use
127 * one shot jump instruction.
128 * Since this instruction is limited to
129 * 26bit, we need to do some magic to fit it to our needs. */
130 LOG_DEBUG("Reading unexpected address. Jump to 0xFF200200\n");
131 code
= MIPS32_J((0x0FFFFFFF & 0xFF200200) >> 2);
133 LOG_ERROR("Error reading unexpected address 0x%8.8" PRIx32
"", address
);
134 return ERROR_JTAG_DEVICE_ERROR
;
137 struct mips_ejtag
*ejtag_info
= ctx
->ejtag_info
;
139 /* Send the data out */
140 mips_ejtag_set_instr(ctx
->ejtag_info
, EJTAG_INST_DATA
);
141 mips_ejtag_drscan_32_out(ctx
->ejtag_info
, code
);
143 /* Clear the access pending bit (let the processor eat!) */
144 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_PRACC
;
145 mips_ejtag_set_instr(ctx
->ejtag_info
, EJTAG_INST_CONTROL
);
146 mips_ejtag_drscan_32_out(ctx
->ejtag_info
, ejtag_ctrl
);
148 return jtag_execute_queue();
151 static int mips32_pracc_exec_write(struct mips32_pracc_context
*ctx
, uint32_t address
)
153 uint32_t ejtag_ctrl
, data
;
154 struct mips_ejtag
*ejtag_info
= ctx
->ejtag_info
;
156 mips_ejtag_set_instr(ctx
->ejtag_info
, EJTAG_INST_DATA
);
157 int retval
= mips_ejtag_drscan_32(ctx
->ejtag_info
, &data
);
158 if (retval
!= ERROR_OK
)
161 /* Clear access pending bit */
162 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_PRACC
;
163 mips_ejtag_set_instr(ctx
->ejtag_info
, EJTAG_INST_CONTROL
);
164 mips_ejtag_drscan_32_out(ctx
->ejtag_info
, ejtag_ctrl
);
166 retval
= jtag_execute_queue();
167 if (retval
!= ERROR_OK
)
170 if ((address
>= MIPS32_PRACC_PARAM_OUT
)
171 && (address
< MIPS32_PRACC_PARAM_OUT
+ ctx
->num_oparam
* 4)) {
172 int offset
= (address
- MIPS32_PRACC_PARAM_OUT
) / 4;
173 ctx
->local_oparam
[offset
] = data
;
175 LOG_ERROR("Error writing unexpected address 0x%8.8" PRIx32
"", address
);
176 return ERROR_JTAG_DEVICE_ERROR
;
182 int mips32_pracc_exec(struct mips_ejtag
*ejtag_info
, int code_len
, const uint32_t *code
,
183 int num_param_out
, uint32_t *param_out
, int cycle
)
185 struct mips32_pracc_context ctx
;
186 ctx
.local_oparam
= param_out
;
187 ctx
.num_oparam
= num_param_out
;
189 ctx
.code_len
= code_len
;
190 ctx
.ejtag_info
= ejtag_info
;
195 int retval
= wait_for_pracc_rw(ejtag_info
, &ejtag_ctrl
);
196 if (retval
!= ERROR_OK
)
199 uint32_t address
= 0;
200 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ADDRESS
);
201 retval
= mips_ejtag_drscan_32(ejtag_info
, &address
);
202 if (retval
!= ERROR_OK
)
205 /* Check for read or write */
206 if (ejtag_ctrl
& EJTAG_CTRL_PRNW
) {
207 retval
= mips32_pracc_exec_write(&ctx
, address
);
208 if (retval
!= ERROR_OK
)
211 /* Check to see if its reading at the debug vector. The first pass through
212 * the module is always read at the vector, so the first one we allow. When
213 * the second read from the vector occurs we are done and just exit. */
214 if ((address
== MIPS32_PRACC_TEXT
) && (pass
++))
217 retval
= mips32_pracc_exec_read(&ctx
, address
);
218 if (retval
!= ERROR_OK
)
229 inline void pracc_queue_init(struct pracc_queue_info
*ctx
)
231 ctx
->retval
= ERROR_OK
;
233 ctx
->store_count
= 0;
235 ctx
->pracc_list
= malloc(2 * ctx
->max_code
* sizeof(uint32_t));
236 if (ctx
->pracc_list
== NULL
) {
237 LOG_ERROR("Out of memory");
238 ctx
->retval
= ERROR_FAIL
;
242 inline void pracc_add(struct pracc_queue_info
*ctx
, uint32_t addr
, uint32_t instr
)
244 ctx
->pracc_list
[ctx
->max_code
+ ctx
->code_count
] = addr
;
245 ctx
->pracc_list
[ctx
->code_count
++] = instr
;
250 inline void pracc_queue_free(struct pracc_queue_info
*ctx
)
252 if (ctx
->code_count
> ctx
->max_code
) /* Only for internal check, will be erased */
253 LOG_ERROR("Internal error, code count: %d > max code: %d", ctx
->code_count
, ctx
->max_code
);
254 if (ctx
->pracc_list
!= NULL
)
255 free(ctx
->pracc_list
);
258 int mips32_pracc_queue_exec(struct mips_ejtag
*ejtag_info
, struct pracc_queue_info
*ctx
, uint32_t *buf
)
260 if (ejtag_info
->mode
== 0)
261 return mips32_pracc_exec(ejtag_info
, ctx
->code_count
, ctx
->pracc_list
,
262 ctx
->store_count
, buf
, ctx
->code_count
- 1);
272 } *scan_in
= malloc(sizeof(union scan_in
) * (ctx
->code_count
+ ctx
->store_count
));
273 if (scan_in
== NULL
) {
274 LOG_ERROR("Out of memory");
278 unsigned num_clocks
=
279 ((uint64_t)(ejtag_info
->scan_delay
) * jtag_get_speed_khz() + 500000) / 1000000;
281 uint32_t ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_PRACC
;
282 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ALL
);
285 for (int i
= 0; i
!= 2 * ctx
->code_count
; i
++) {
287 if (i
& 1u) { /* Check store address from previous instruction, if not the first */
288 if (i
< 2 || 0 == ctx
->pracc_list
[ctx
->max_code
+ (i
/ 2) - 1])
291 data
= ctx
->pracc_list
[i
/ 2];
293 jtag_add_clocks(num_clocks
);
294 mips_ejtag_add_scan_96(ejtag_info
, ejtag_ctrl
, data
, scan_in
[scan_count
++].scan_96
);
297 int retval
= jtag_execute_queue(); /* execute queued scans */
298 if (retval
!= ERROR_OK
)
301 uint32_t fetch_addr
= MIPS32_PRACC_TEXT
; /* start address */
303 for (int i
= 0; i
!= 2 * ctx
->code_count
; i
++) { /* verify every pracc access */
304 uint32_t store_addr
= 0;
305 if (i
& 1u) { /* Read store addres from previous instruction, if not the first */
306 store_addr
= ctx
->pracc_list
[ctx
->max_code
+ (i
/ 2) - 1];
307 if (i
< 2 || 0 == store_addr
)
311 ejtag_ctrl
= buf_get_u32(scan_in
[scan_count
].scan_32
.ctrl
, 0, 32);
312 if (!(ejtag_ctrl
& EJTAG_CTRL_PRACC
)) {
313 LOG_ERROR("Error: access not pending count: %d", scan_count
);
318 uint32_t addr
= buf_get_u32(scan_in
[scan_count
].scan_32
.addr
, 0, 32);
320 if (store_addr
!= 0) {
321 if (!(ejtag_ctrl
& EJTAG_CTRL_PRNW
)) {
322 LOG_ERROR("Not a store/write access, count: %d", scan_count
);
326 if (addr
!= store_addr
) {
327 LOG_ERROR("Store address mismatch, read: %" PRIx32
" expected: %" PRIx32
" count: %d",
328 addr
, store_addr
, scan_count
);
332 int buf_index
= (addr
- MIPS32_PRACC_PARAM_OUT
) / 4;
333 buf
[buf_index
] = buf_get_u32(scan_in
[scan_count
].scan_32
.data
, 0, 32);
336 if (ejtag_ctrl
& EJTAG_CTRL_PRNW
) {
337 LOG_ERROR("Not a fetch/read access, count: %d", scan_count
);
341 if (addr
!= fetch_addr
) {
342 LOG_ERROR("Fetch addr mismatch, read: %" PRIx32
" expected: %" PRIx32
" count: %d",
343 addr
, fetch_addr
, scan_count
);
356 int mips32_pracc_read_u32(struct mips_ejtag
*ejtag_info
, uint32_t addr
, uint32_t *buf
)
358 struct pracc_queue_info ctx
= {.max_code
= 8};
359 pracc_queue_init(&ctx
);
360 if (ctx
.retval
!= ERROR_OK
)
363 pracc_add(&ctx
, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR
)); /* $15 = MIPS32_PRACC_BASE_ADDR */
364 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16((addr
+ 0x8000)))); /* load $8 with modified upper address */
365 pracc_add(&ctx
, 0, MIPS32_LW(8, LOWER16(addr
), 8)); /* lw $8, LOWER16(addr)($8) */
366 pracc_add(&ctx
, MIPS32_PRACC_PARAM_OUT
,
367 MIPS32_SW(8, PRACC_OUT_OFFSET
, 15)); /* sw $8,PRACC_OUT_OFFSET($15) */
368 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(ejtag_info
->reg8
))); /* restore upper 16 of $8 */
369 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info
->reg8
))); /* restore lower 16 of $8 */
370 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
371 pracc_add(&ctx
, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
373 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, buf
);
375 pracc_queue_free(&ctx
);
379 int mips32_pracc_read_mem(struct mips_ejtag
*ejtag_info
, uint32_t addr
, int size
, int count
, void *buf
)
381 if (count
== 1 && size
== 4)
382 return mips32_pracc_read_u32(ejtag_info
, addr
, (uint32_t *)buf
);
384 uint32_t *data
= NULL
;
385 struct pracc_queue_info ctx
= {.max_code
= 256 * 3 + 8 + 1}; /* alloc memory for the worst case */
386 pracc_queue_init(&ctx
);
387 if (ctx
.retval
!= ERROR_OK
)
391 data
= malloc(256 * sizeof(uint32_t));
393 LOG_ERROR("Out of memory");
398 uint32_t *buf32
= buf
;
399 uint16_t *buf16
= buf
;
405 int this_round_count
= (count
> 256) ? 256 : count
;
406 uint32_t last_upper_base_addr
= UPPER16((addr
+ 0x8000));
408 pracc_add(&ctx
, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR
)); /* $15 = MIPS32_PRACC_BASE_ADDR */
409 pracc_add(&ctx
, 0, MIPS32_LUI(9, last_upper_base_addr
)); /* load the upper memory address in $9 */
411 for (int i
= 0; i
!= this_round_count
; i
++) { /* Main code loop */
412 uint32_t upper_base_addr
= UPPER16((addr
+ 0x8000));
413 if (last_upper_base_addr
!= upper_base_addr
) { /* if needed, change upper address in $9 */
414 pracc_add(&ctx
, 0, MIPS32_LUI(9, upper_base_addr
));
415 last_upper_base_addr
= upper_base_addr
;
419 pracc_add(&ctx
, 0, MIPS32_LW(8, LOWER16(addr
), 9)); /* load from memory to $8 */
421 pracc_add(&ctx
, 0, MIPS32_LHU(8, LOWER16(addr
), 9));
423 pracc_add(&ctx
, 0, MIPS32_LBU(8, LOWER16(addr
), 9));
425 pracc_add(&ctx
, MIPS32_PRACC_PARAM_OUT
+ i
* 4,
426 MIPS32_SW(8, PRACC_OUT_OFFSET
+ i
* 4, 15)); /* store $8 at param out */
429 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(ejtag_info
->reg8
))); /* restore upper 16 bits of reg 8 */
430 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info
->reg8
))); /* restore lower 16 bits of reg 8 */
431 pracc_add(&ctx
, 0, MIPS32_LUI(9, UPPER16(ejtag_info
->reg9
))); /* restore upper 16 bits of reg 9 */
432 pracc_add(&ctx
, 0, MIPS32_ORI(9, 9, LOWER16(ejtag_info
->reg9
))); /* restore lower 16 bits of reg 9 */
434 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
435 pracc_add(&ctx
, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
438 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, buf32
);
439 if (ctx
.retval
!= ERROR_OK
)
441 buf32
+= this_round_count
;
443 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, data
);
444 if (ctx
.retval
!= ERROR_OK
)
447 uint32_t *data_p
= data
;
448 for (int i
= 0; i
!= this_round_count
; i
++) {
450 *buf16
++ = *data_p
++;
455 count
-= this_round_count
;
458 pracc_queue_free(&ctx
);
464 int mips32_cp0_read(struct mips_ejtag
*ejtag_info
, uint32_t *val
, uint32_t cp0_reg
, uint32_t cp0_sel
)
466 struct pracc_queue_info ctx
= {.max_code
= 7};
467 pracc_queue_init(&ctx
);
468 if (ctx
.retval
!= ERROR_OK
)
471 pracc_add(&ctx
, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR
)); /* $15 = MIPS32_PRACC_BASE_ADDR */
472 pracc_add(&ctx
, 0, MIPS32_MFC0(8, 0, 0) | (cp0_reg
<< 11) | cp0_sel
); /* move COP0 [cp0_reg select] to $8 */
473 pracc_add(&ctx
, MIPS32_PRACC_PARAM_OUT
,
474 MIPS32_SW(8, PRACC_OUT_OFFSET
, 15)); /* store $8 to pracc_out */
475 pracc_add(&ctx
, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
476 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(ejtag_info
->reg8
))); /* restore upper 16 bits of $8 */
477 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
478 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info
->reg8
))); /* restore lower 16 bits of $8 */
480 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, val
);
482 pracc_queue_free(&ctx
);
486 * Note that our input parametes cp0_reg and cp0_sel
487 * are numbers (not gprs) which make part of mfc0 instruction opcode.
489 * These are not fix, but can be different for each mips32_cp0_read() function call,
490 * and that is why we must insert them directly into opcode,
491 * i.e. we can not pass it on EJTAG microprogram stack (via param_in),
492 * and put them into the gprs later from MIPS32_PRACC_STACK
493 * because mfc0 do not use gpr as a parameter for the cp0_reg and select part,
494 * but plain (immediate) number.
496 * MIPS32_MTC0 is implemented via MIPS32_R_INST macro.
497 * In order to insert our parameters, we must change rd and funct fields.
499 * code[2] |= (cp0_reg << 11) | cp0_sel; change rd and funct of MIPS32_R_INST macro
503 int mips32_cp0_write(struct mips_ejtag
*ejtag_info
, uint32_t val
, uint32_t cp0_reg
, uint32_t cp0_sel
)
505 struct pracc_queue_info ctx
= {.max_code
= 6};
506 pracc_queue_init(&ctx
);
507 if (ctx
.retval
!= ERROR_OK
)
510 pracc_add(&ctx
, 0, MIPS32_LUI(15, UPPER16(val
))); /* Load val to $15 */
511 pracc_add(&ctx
, 0, MIPS32_ORI(15, 15, LOWER16(val
)));
513 pracc_add(&ctx
, 0, MIPS32_MTC0(15, 0, 0) | (cp0_reg
<< 11) | cp0_sel
); /* write cp0 reg / sel */
515 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
516 pracc_add(&ctx
, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
518 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
);
520 pracc_queue_free(&ctx
);
524 * Note that MIPS32_MTC0 macro is implemented via MIPS32_R_INST macro.
525 * In order to insert our parameters, we must change rd and funct fields.
526 * code[3] |= (cp0_reg << 11) | cp0_sel; change rd and funct fields of MIPS32_R_INST macro
531 * \b mips32_pracc_sync_cache
533 * Synchronize Caches to Make Instruction Writes Effective
534 * (ref. doc. MIPS32 Architecture For Programmers Volume II: The MIPS32 Instruction Set,
535 * Document Number: MD00086, Revision 2.00, June 9, 2003)
537 * When the instruction stream is written, the SYNCI instruction should be used
538 * in conjunction with other instructions to make the newly-written instructions effective.
541 * A program that loads another program into memory is actually writing the D- side cache.
542 * The instructions it has loaded can't be executed until they reach the I-cache.
544 * After the instructions have been written, the loader should arrange
545 * to write back any containing D-cache line and invalidate any locations
546 * already in the I-cache.
548 * If the cache coherency attribute (CCA) is set to zero, it's a write through cache, there is no need
551 * In the latest MIPS32/64 CPUs, MIPS provides the synci instruction,
552 * which does the whole job for a cache-line-sized chunk of the memory you just loaded:
553 * That is, it arranges a D-cache write-back (if CCA = 3) and an I-cache invalidate.
555 * The line size is obtained with the rdhwr SYNCI_Step in release 2 or from cp0 config 1 register in release 1.
557 static int mips32_pracc_synchronize_cache(struct mips_ejtag
*ejtag_info
,
558 uint32_t start_addr
, uint32_t end_addr
, int cached
, int rel
)
560 struct pracc_queue_info ctx
= {.max_code
= 256 * 2 + 5};
561 pracc_queue_init(&ctx
);
562 if (ctx
.retval
!= ERROR_OK
)
564 /** Find cache line size in bytes */
566 if (rel
) { /* Release 2 (rel = 1) */
567 pracc_add(&ctx
, 0, MIPS32_LUI(15, PRACC_UPPER_BASE_ADDR
)); /* $15 = MIPS32_PRACC_BASE_ADDR */
569 pracc_add(&ctx
, 0, MIPS32_RDHWR(8, MIPS32_SYNCI_STEP
)); /* load synci_step value to $8 */
571 pracc_add(&ctx
, MIPS32_PRACC_PARAM_OUT
,
572 MIPS32_SW(8, PRACC_OUT_OFFSET
, 15)); /* store $8 to pracc_out */
574 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(ejtag_info
->reg8
))); /* restore upper 16 bits of $8 */
575 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info
->reg8
))); /* restore lower 16 bits of $8 */
576 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
577 pracc_add(&ctx
, 0, MIPS32_MFC0(15, 31, 0)); /* move COP0 DeSave to $15 */
579 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, &clsiz
);
580 if (ctx
.retval
!= ERROR_OK
)
583 } else { /* Release 1 (rel = 0) */
585 ctx
.retval
= mips32_cp0_read(ejtag_info
, &conf
, 16, 1);
586 if (ctx
.retval
!= ERROR_OK
)
589 uint32_t dl
= (conf
& MIPS32_CONFIG1_DL_MASK
) >> MIPS32_CONFIG1_DL_SHIFT
;
591 /* dl encoding : dl=1 => 4 bytes, dl=2 => 8 bytes, etc... max dl=6 => 128 bytes cache line size */
598 goto exit
; /* Nothing to do */
600 /* make sure clsiz is power of 2 */
601 if (clsiz
& (clsiz
- 1)) {
602 LOG_DEBUG("clsiz must be power of 2");
603 ctx
.retval
= ERROR_FAIL
;
607 /* make sure start_addr and end_addr have the same offset inside de cache line */
608 start_addr
|= clsiz
- 1;
609 end_addr
|= clsiz
- 1;
613 uint32_t last_upper_base_addr
= UPPER16((start_addr
+ 0x8000));
615 pracc_add(&ctx
, 0, MIPS32_LUI(15, last_upper_base_addr
)); /* load upper memory base address to $15 */
617 while (start_addr
<= end_addr
) { /* main loop */
618 uint32_t upper_base_addr
= UPPER16((start_addr
+ 0x8000));
619 if (last_upper_base_addr
!= upper_base_addr
) { /* if needed, change upper address in $15 */
620 pracc_add(&ctx
, 0, MIPS32_LUI(15, upper_base_addr
));
621 last_upper_base_addr
= upper_base_addr
;
624 pracc_add(&ctx
, 0, MIPS32_SYNCI(LOWER16(start_addr
), 15)); /* synci instruction, offset($15) */
628 pracc_add(&ctx
, 0, MIPS32_CACHE(MIPS32_CACHE_D_HIT_WRITEBACK
,
629 LOWER16(start_addr
), 15)); /* cache Hit_Writeback_D, offset($15) */
631 pracc_add(&ctx
, 0, MIPS32_CACHE(MIPS32_CACHE_I_HIT_INVALIDATE
,
632 LOWER16(start_addr
), 15)); /* cache Hit_Invalidate_I, offset($15) */
636 if (count
== 256 && start_addr
<= end_addr
) { /* more ?, then execute code list */
637 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
638 pracc_add(&ctx
, 0, MIPS32_NOP
); /* nop in delay slot */
640 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
);
641 if (ctx
.retval
!= ERROR_OK
)
648 pracc_add(&ctx
, 0, MIPS32_SYNC
);
649 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
650 pracc_add(&ctx
, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave*/
652 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
);
654 pracc_queue_free(&ctx
);
658 static int mips32_pracc_write_mem_generic(struct mips_ejtag
*ejtag_info
,
659 uint32_t addr
, int size
, int count
, const void *buf
)
661 struct pracc_queue_info ctx
= {.max_code
= 128 * 3 + 5 + 1}; /* alloc memory for the worst case */
662 pracc_queue_init(&ctx
);
663 if (ctx
.retval
!= ERROR_OK
)
666 const uint32_t *buf32
= buf
;
667 const uint16_t *buf16
= buf
;
668 const uint8_t *buf8
= buf
;
673 int this_round_count
= (count
> 128) ? 128 : count
;
674 uint32_t last_upper_base_addr
= UPPER16((addr
+ 0x8000));
676 pracc_add(&ctx
, 0, MIPS32_LUI(15, last_upper_base_addr
)); /* load $15 with memory base address */
678 for (int i
= 0; i
!= this_round_count
; i
++) {
679 uint32_t upper_base_addr
= UPPER16((addr
+ 0x8000));
680 if (last_upper_base_addr
!= upper_base_addr
) {
681 pracc_add(&ctx
, 0, MIPS32_LUI(15, upper_base_addr
)); /* if needed, change upper address in $15*/
682 last_upper_base_addr
= upper_base_addr
;
685 if (size
== 4) { /* for word writes check if one half word is 0 and load it accordingly */
686 if (LOWER16(*buf32
) == 0)
687 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(*buf32
))); /* load only upper value */
688 else if (UPPER16(*buf32
) == 0)
689 pracc_add(&ctx
, 0, MIPS32_ORI(8, 0, LOWER16(*buf32
))); /* load only lower */
691 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(*buf32
))); /* load upper and lower */
692 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, LOWER16(*buf32
)));
694 pracc_add(&ctx
, 0, MIPS32_SW(8, LOWER16(addr
), 15)); /* store word to memory */
697 } else if (size
== 2) {
698 pracc_add(&ctx
, 0, MIPS32_ORI(8, 0, *buf16
)); /* load lower value */
699 pracc_add(&ctx
, 0, MIPS32_SH(8, LOWER16(addr
), 15)); /* store half word to memory */
703 pracc_add(&ctx
, 0, MIPS32_ORI(8, 0, *buf8
)); /* load lower value */
704 pracc_add(&ctx
, 0, MIPS32_SB(8, LOWER16(addr
), 15)); /* store byte to memory */
710 pracc_add(&ctx
, 0, MIPS32_LUI(8, UPPER16(ejtag_info
->reg8
))); /* restore upper 16 bits of reg 8 */
711 pracc_add(&ctx
, 0, MIPS32_ORI(8, 8, LOWER16(ejtag_info
->reg8
))); /* restore lower 16 bits of reg 8 */
713 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
714 pracc_add(&ctx
, 0, MIPS32_MFC0(15, 31, 0)); /* restore $15 from DeSave */
716 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
);
717 if (ctx
.retval
!= ERROR_OK
)
719 count
-= this_round_count
;
722 pracc_queue_free(&ctx
);
726 int mips32_pracc_write_mem(struct mips_ejtag
*ejtag_info
, uint32_t addr
, int size
, int count
, const void *buf
)
728 int retval
= mips32_pracc_write_mem_generic(ejtag_info
, addr
, size
, count
, buf
);
729 if (retval
!= ERROR_OK
)
733 * If we are in the cacheable region and cache is activated,
734 * we must clean D$ (if Cache Coherency Attribute is set to 3) + invalidate I$ after we did the write,
735 * so that changes do not continue to live only in D$ (if CCA = 3), but to be
736 * replicated in I$ also (maybe we wrote the istructions)
741 if ((KSEGX(addr
) == KSEG1
) || ((addr
>= 0xff200000) && (addr
<= 0xff3fffff)))
742 return retval
; /*Nothing to do*/
744 mips32_cp0_read(ejtag_info
, &conf
, 16, 0);
746 switch (KSEGX(addr
)) {
748 cached
= (conf
& MIPS32_CONFIG0_KU_MASK
) >> MIPS32_CONFIG0_KU_SHIFT
;
751 cached
= (conf
& MIPS32_CONFIG0_K0_MASK
) >> MIPS32_CONFIG0_K0_SHIFT
;
755 cached
= (conf
& MIPS32_CONFIG0_K23_MASK
) >> MIPS32_CONFIG0_K23_SHIFT
;
763 * Check cachablitiy bits coherency algorithm
764 * is the region cacheable or uncached.
765 * If cacheable we have to synchronize the cache
767 if (cached
== 3 || cached
== 0) { /* Write back cache or write through cache */
768 uint32_t start_addr
= addr
;
769 uint32_t end_addr
= addr
+ count
* size
;
770 uint32_t rel
= (conf
& MIPS32_CONFIG0_AR_MASK
) >> MIPS32_CONFIG0_AR_SHIFT
;
772 LOG_DEBUG("Unknown release in cache code");
775 retval
= mips32_pracc_synchronize_cache(ejtag_info
, start_addr
, end_addr
, cached
, rel
);
781 int mips32_pracc_write_regs(struct mips_ejtag
*ejtag_info
, uint32_t *regs
)
783 static const uint32_t cp0_write_code
[] = {
784 MIPS32_MTC0(1, 12, 0), /* move $1 to status */
785 MIPS32_MTLO(1), /* move $1 to lo */
786 MIPS32_MTHI(1), /* move $1 to hi */
787 MIPS32_MTC0(1, 8, 0), /* move $1 to badvaddr */
788 MIPS32_MTC0(1, 13, 0), /* move $1 to cause*/
789 MIPS32_MTC0(1, 24, 0), /* move $1 to depc (pc) */
792 struct pracc_queue_info ctx
= {.max_code
= 37 * 2 + 7 + 1};
793 pracc_queue_init(&ctx
);
794 if (ctx
.retval
!= ERROR_OK
)
797 /* load registers 2 to 31 with lui and ori instructions, check if some instructions can be saved */
798 for (int i
= 2; i
< 32; i
++) {
799 if (LOWER16((regs
[i
])) == 0) /* if lower half word is 0, lui instruction only */
800 pracc_add(&ctx
, 0, MIPS32_LUI(i
, UPPER16((regs
[i
]))));
801 else if (UPPER16((regs
[i
])) == 0) /* if upper half word is 0, ori with $0 only*/
802 pracc_add(&ctx
, 0, MIPS32_ORI(i
, 0, LOWER16((regs
[i
]))));
803 else { /* default, load with lui and ori instructions */
804 pracc_add(&ctx
, 0, MIPS32_LUI(i
, UPPER16((regs
[i
]))));
805 pracc_add(&ctx
, 0, MIPS32_ORI(i
, i
, LOWER16((regs
[i
]))));
809 for (int i
= 0; i
!= 6; i
++) {
810 pracc_add(&ctx
, 0, MIPS32_LUI(1, UPPER16((regs
[i
+ 32])))); /* load CPO value in $1, with lui and ori */
811 pracc_add(&ctx
, 0, MIPS32_ORI(1, 1, LOWER16((regs
[i
+ 32]))));
812 pracc_add(&ctx
, 0, cp0_write_code
[i
]); /* write value from $1 to CPO register */
814 pracc_add(&ctx
, 0, MIPS32_MTC0(15, 31, 0)); /* load $15 in DeSave */
815 pracc_add(&ctx
, 0, MIPS32_LUI(1, UPPER16((regs
[1])))); /* load upper half word in $1 */
816 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
817 pracc_add(&ctx
, 0, MIPS32_ORI(1, 1, LOWER16((regs
[1])))); /* load lower half word in $1 */
819 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, NULL
);
821 ejtag_info
->reg8
= regs
[8];
822 ejtag_info
->reg9
= regs
[9];
824 pracc_queue_free(&ctx
);
828 int mips32_pracc_read_regs(struct mips_ejtag
*ejtag_info
, uint32_t *regs
)
830 static int cp0_read_code
[] = {
831 MIPS32_MFC0(8, 12, 0), /* move status to $8 */
832 MIPS32_MFLO(8), /* move lo to $8 */
833 MIPS32_MFHI(8), /* move hi to $8 */
834 MIPS32_MFC0(8, 8, 0), /* move badvaddr to $8 */
835 MIPS32_MFC0(8, 13, 0), /* move cause to $8 */
836 MIPS32_MFC0(8, 24, 0), /* move depc (pc) to $8 */
839 struct pracc_queue_info ctx
= {.max_code
= 49};
840 pracc_queue_init(&ctx
);
841 if (ctx
.retval
!= ERROR_OK
)
844 pracc_add(&ctx
, 0, MIPS32_MTC0(1, 31, 0)); /* move $1 to COP0 DeSave */
845 pracc_add(&ctx
, 0, MIPS32_LUI(1, PRACC_UPPER_BASE_ADDR
)); /* $1 = MIP32_PRACC_BASE_ADDR */
847 for (int i
= 2; i
!= 32; i
++) /* store GPR's 2 to 31 */
848 pracc_add(&ctx
, MIPS32_PRACC_PARAM_OUT
+ (i
* 4),
849 MIPS32_SW(i
, PRACC_OUT_OFFSET
+ (i
* 4), 1));
851 for (int i
= 0; i
!= 6; i
++) {
852 pracc_add(&ctx
, 0, cp0_read_code
[i
]); /* load COP0 needed registers to $8 */
853 pracc_add(&ctx
, MIPS32_PRACC_PARAM_OUT
+ (i
+ 32) * 4, /* store $8 at PARAM OUT */
854 MIPS32_SW(8, PRACC_OUT_OFFSET
+ (i
+ 32) * 4, 1));
856 pracc_add(&ctx
, 0, MIPS32_MFC0(8, 31, 0)); /* move DeSave to $8, reg1 value */
857 pracc_add(&ctx
, MIPS32_PRACC_PARAM_OUT
+ 4, /* store reg1 value from $8 to param out */
858 MIPS32_SW(8, PRACC_OUT_OFFSET
+ 4, 1));
860 pracc_add(&ctx
, 0, MIPS32_MFC0(1, 31, 0)); /* move COP0 DeSave to $1, restore reg1 */
861 pracc_add(&ctx
, 0, MIPS32_B(NEG16(ctx
.code_count
+ 1))); /* jump to start */
862 pracc_add(&ctx
, 0, MIPS32_MTC0(15, 31, 0)); /* load $15 in DeSave */
864 if (ejtag_info
->mode
== 0)
865 ctx
.store_count
++; /* Needed by legacy code, due to offset from reg0 */
867 ctx
.retval
= mips32_pracc_queue_exec(ejtag_info
, &ctx
, regs
);
869 ejtag_info
->reg8
= regs
[8]; /* reg8 is saved but not restored, next called function should restore it */
870 ejtag_info
->reg9
= regs
[9];
872 pracc_queue_free(&ctx
);
876 /* fastdata upload/download requires an initialized working area
877 * to load the download code; it should not be called otherwise
878 * fetch order from the fastdata area
883 int mips32_pracc_fastdata_xfer(struct mips_ejtag
*ejtag_info
, struct working_area
*source
,
884 int write_t
, uint32_t addr
, int count
, uint32_t *buf
)
886 uint32_t handler_code
[] = {
887 /* caution when editing, table is modified below */
888 /* r15 points to the start of this code */
889 MIPS32_SW(8, MIPS32_FASTDATA_HANDLER_SIZE
- 4, 15),
890 MIPS32_SW(9, MIPS32_FASTDATA_HANDLER_SIZE
- 8, 15),
891 MIPS32_SW(10, MIPS32_FASTDATA_HANDLER_SIZE
- 12, 15),
892 MIPS32_SW(11, MIPS32_FASTDATA_HANDLER_SIZE
- 16, 15),
893 /* start of fastdata area in t0 */
894 MIPS32_LUI(8, UPPER16(MIPS32_PRACC_FASTDATA_AREA
)),
895 MIPS32_ORI(8, 8, LOWER16(MIPS32_PRACC_FASTDATA_AREA
)),
896 MIPS32_LW(9, 0, 8), /* start addr in t1 */
897 MIPS32_LW(10, 0, 8), /* end addr to t2 */
899 /* 8 */ MIPS32_LW(11, 0, 0), /* lw t3,[t8 | r9] */
900 /* 9 */ MIPS32_SW(11, 0, 0), /* sw t3,[r9 | r8] */
901 MIPS32_BNE(10, 9, NEG16(3)), /* bne $t2,t1,loop */
902 MIPS32_ADDI(9, 9, 4), /* addi t1,t1,4 */
904 MIPS32_LW(8, MIPS32_FASTDATA_HANDLER_SIZE
- 4, 15),
905 MIPS32_LW(9, MIPS32_FASTDATA_HANDLER_SIZE
- 8, 15),
906 MIPS32_LW(10, MIPS32_FASTDATA_HANDLER_SIZE
- 12, 15),
907 MIPS32_LW(11, MIPS32_FASTDATA_HANDLER_SIZE
- 16, 15),
909 MIPS32_LUI(15, UPPER16(MIPS32_PRACC_TEXT
)),
910 MIPS32_ORI(15, 15, LOWER16(MIPS32_PRACC_TEXT
)),
911 MIPS32_JR(15), /* jr start */
912 MIPS32_MFC0(15, 31, 0), /* move COP0 DeSave to $15 */
915 uint32_t jmp_code
[] = {
916 /* 0 */ MIPS32_LUI(15, 0), /* addr of working area added below */
917 /* 1 */ MIPS32_ORI(15, 15, 0), /* addr of working area added below */
918 MIPS32_JR(15), /* jump to ram program */
923 uint32_t val
, ejtag_ctrl
, address
;
925 if (source
->size
< MIPS32_FASTDATA_HANDLER_SIZE
)
926 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
929 handler_code
[8] = MIPS32_LW(11, 0, 8); /* load data from probe at fastdata area */
930 handler_code
[9] = MIPS32_SW(11, 0, 9); /* store data to RAM @ r9 */
932 handler_code
[8] = MIPS32_LW(11, 0, 9); /* load data from RAM @ r9 */
933 handler_code
[9] = MIPS32_SW(11, 0, 8); /* store data to probe at fastdata area */
936 /* write program into RAM */
937 if (write_t
!= ejtag_info
->fast_access_save
) {
938 mips32_pracc_write_mem(ejtag_info
, source
->address
, 4, ARRAY_SIZE(handler_code
), handler_code
);
939 /* save previous operation to speed to any consecutive read/writes */
940 ejtag_info
->fast_access_save
= write_t
;
943 LOG_DEBUG("%s using 0x%.8" PRIx32
" for write handler", __func__
, source
->address
);
945 jmp_code
[0] |= UPPER16(source
->address
);
946 jmp_code
[1] |= LOWER16(source
->address
);
948 for (i
= 0; i
< (int) ARRAY_SIZE(jmp_code
); i
++) {
949 retval
= wait_for_pracc_rw(ejtag_info
, &ejtag_ctrl
);
950 if (retval
!= ERROR_OK
)
953 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_DATA
);
954 mips_ejtag_drscan_32_out(ejtag_info
, jmp_code
[i
]);
956 /* Clear the access pending bit (let the processor eat!) */
957 ejtag_ctrl
= ejtag_info
->ejtag_ctrl
& ~EJTAG_CTRL_PRACC
;
958 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_CONTROL
);
959 mips_ejtag_drscan_32_out(ejtag_info
, ejtag_ctrl
);
962 /* wait PrAcc pending bit for FASTDATA write */
963 retval
= wait_for_pracc_rw(ejtag_info
, &ejtag_ctrl
);
964 if (retval
!= ERROR_OK
)
967 /* next fetch to dmseg should be in FASTDATA_AREA, check */
969 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ADDRESS
);
970 retval
= mips_ejtag_drscan_32(ejtag_info
, &address
);
971 if (retval
!= ERROR_OK
)
974 if (address
!= MIPS32_PRACC_FASTDATA_AREA
)
977 /* Send the load start address */
979 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_FASTDATA
);
980 mips_ejtag_fastdata_scan(ejtag_info
, 1, &val
);
982 retval
= wait_for_pracc_rw(ejtag_info
, &ejtag_ctrl
);
983 if (retval
!= ERROR_OK
)
986 /* Send the load end address */
987 val
= addr
+ (count
- 1) * 4;
988 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_FASTDATA
);
989 mips_ejtag_fastdata_scan(ejtag_info
, 1, &val
);
991 unsigned num_clocks
= 0; /* like in legacy code */
992 if (ejtag_info
->mode
!= 0)
993 num_clocks
= ((uint64_t)(ejtag_info
->scan_delay
) * jtag_get_speed_khz() + 500000) / 1000000;
995 for (i
= 0; i
< count
; i
++) {
996 jtag_add_clocks(num_clocks
);
997 retval
= mips_ejtag_fastdata_scan(ejtag_info
, write_t
, buf
++);
998 if (retval
!= ERROR_OK
)
1002 retval
= jtag_execute_queue();
1003 if (retval
!= ERROR_OK
) {
1004 LOG_ERROR("fastdata load failed");
1008 retval
= wait_for_pracc_rw(ejtag_info
, &ejtag_ctrl
);
1009 if (retval
!= ERROR_OK
)
1013 mips_ejtag_set_instr(ejtag_info
, EJTAG_INST_ADDRESS
);
1014 retval
= mips_ejtag_drscan_32(ejtag_info
, &address
);
1015 if (retval
!= ERROR_OK
)
1018 if (address
!= MIPS32_PRACC_TEXT
)
1019 LOG_ERROR("mini program did not return to start");
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