1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
5 * Copyright (C) 2008 by David T.L. Wong *
7 * Copyright (C) 2007,2008 Øyvind Harboe *
8 * oyvind.harboe@zylin.com *
10 * Copyright (C) 2011 by Drasko DRASKOVIC *
11 * drasko.draskovic@gmail.com *
13 * This program is free software; you can redistribute it and/or modify *
14 * it under the terms of the GNU General Public License as published by *
15 * the Free Software Foundation; either version 2 of the License, or *
16 * (at your option) any later version. *
18 * This program is distributed in the hope that it will be useful, *
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
21 * GNU General Public License for more details. *
23 * You should have received a copy of the GNU General Public License *
24 * along with this program; if not, write to the *
25 * Free Software Foundation, Inc., *
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
27 ***************************************************************************/
34 #include "breakpoints.h"
35 #include "algorithm.h"
38 static char *mips32_core_reg_list
[] = {
39 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
40 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
41 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
42 "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra",
43 "status", "lo", "hi", "badvaddr", "cause", "pc"
46 static const char *mips_isa_strings
[] = {
50 static struct mips32_core_reg mips32_core_reg_list_arch_info
[MIPS32NUMCOREREGS
] = {
92 /* number of mips dummy fp regs fp0 - fp31 + fsr and fir
93 * we also add 18 unknown registers to handle gdb requests */
95 #define MIPS32NUMFPREGS (34 + 18)
97 static uint8_t mips32_gdb_dummy_fp_value
[] = {0, 0, 0, 0};
99 static struct reg mips32_gdb_dummy_fp_reg
= {
100 .name
= "GDB dummy floating-point register",
101 .value
= mips32_gdb_dummy_fp_value
,
108 static int mips32_get_core_reg(struct reg
*reg
)
111 struct mips32_core_reg
*mips32_reg
= reg
->arch_info
;
112 struct target
*target
= mips32_reg
->target
;
113 struct mips32_common
*mips32_target
= target_to_mips32(target
);
115 if (target
->state
!= TARGET_HALTED
)
116 return ERROR_TARGET_NOT_HALTED
;
118 retval
= mips32_target
->read_core_reg(target
, mips32_reg
->num
);
123 static int mips32_set_core_reg(struct reg
*reg
, uint8_t *buf
)
125 struct mips32_core_reg
*mips32_reg
= reg
->arch_info
;
126 struct target
*target
= mips32_reg
->target
;
127 uint32_t value
= buf_get_u32(buf
, 0, 32);
129 if (target
->state
!= TARGET_HALTED
)
130 return ERROR_TARGET_NOT_HALTED
;
132 buf_set_u32(reg
->value
, 0, 32, value
);
139 static int mips32_read_core_reg(struct target
*target
, int num
)
143 /* get pointers to arch-specific information */
144 struct mips32_common
*mips32
= target_to_mips32(target
);
146 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
147 return ERROR_COMMAND_SYNTAX_ERROR
;
149 reg_value
= mips32
->core_regs
[num
];
150 buf_set_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
151 mips32
->core_cache
->reg_list
[num
].valid
= 1;
152 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
157 static int mips32_write_core_reg(struct target
*target
, int num
)
161 /* get pointers to arch-specific information */
162 struct mips32_common
*mips32
= target_to_mips32(target
);
164 if ((num
< 0) || (num
>= MIPS32NUMCOREREGS
))
165 return ERROR_COMMAND_SYNTAX_ERROR
;
167 reg_value
= buf_get_u32(mips32
->core_cache
->reg_list
[num
].value
, 0, 32);
168 mips32
->core_regs
[num
] = reg_value
;
169 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", num
, reg_value
);
170 mips32
->core_cache
->reg_list
[num
].valid
= 1;
171 mips32
->core_cache
->reg_list
[num
].dirty
= 0;
176 int mips32_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[], int *reg_list_size
)
178 /* get pointers to arch-specific information */
179 struct mips32_common
*mips32
= target_to_mips32(target
);
182 /* include floating point registers */
183 *reg_list_size
= MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
;
184 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
186 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++)
187 (*reg_list
)[i
] = &mips32
->core_cache
->reg_list
[i
];
189 /* add dummy floating points regs */
190 for (i
= MIPS32NUMCOREREGS
; i
< (MIPS32NUMCOREREGS
+ MIPS32NUMFPREGS
); i
++)
191 (*reg_list
)[i
] = &mips32_gdb_dummy_fp_reg
;
196 int mips32_save_context(struct target
*target
)
200 /* get pointers to arch-specific information */
201 struct mips32_common
*mips32
= target_to_mips32(target
);
202 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
204 /* read core registers */
205 mips32_pracc_read_regs(ejtag_info
, mips32
->core_regs
);
207 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++) {
208 if (!mips32
->core_cache
->reg_list
[i
].valid
)
209 mips32
->read_core_reg(target
, i
);
215 int mips32_restore_context(struct target
*target
)
219 /* get pointers to arch-specific information */
220 struct mips32_common
*mips32
= target_to_mips32(target
);
221 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
223 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++) {
224 if (mips32
->core_cache
->reg_list
[i
].dirty
)
225 mips32
->write_core_reg(target
, i
);
228 /* write core regs */
229 mips32_pracc_write_regs(ejtag_info
, mips32
->core_regs
);
234 int mips32_arch_state(struct target
*target
)
236 struct mips32_common
*mips32
= target_to_mips32(target
);
238 LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32
"",
239 mips_isa_strings
[mips32
->isa_mode
],
240 debug_reason_name(target
),
241 buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32));
246 static const struct reg_arch_type mips32_reg_type
= {
247 .get
= mips32_get_core_reg
,
248 .set
= mips32_set_core_reg
,
251 struct reg_cache
*mips32_build_reg_cache(struct target
*target
)
253 /* get pointers to arch-specific information */
254 struct mips32_common
*mips32
= target_to_mips32(target
);
256 int num_regs
= MIPS32NUMCOREREGS
;
257 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
258 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
259 struct reg
*reg_list
= malloc(sizeof(struct reg
) * num_regs
);
260 struct mips32_core_reg
*arch_info
= malloc(sizeof(struct mips32_core_reg
) * num_regs
);
263 register_init_dummy(&mips32_gdb_dummy_fp_reg
);
265 /* Build the process context cache */
266 cache
->name
= "mips32 registers";
268 cache
->reg_list
= reg_list
;
269 cache
->num_regs
= num_regs
;
271 mips32
->core_cache
= cache
;
273 for (i
= 0; i
< num_regs
; i
++) {
274 arch_info
[i
] = mips32_core_reg_list_arch_info
[i
];
275 arch_info
[i
].target
= target
;
276 arch_info
[i
].mips32_common
= mips32
;
277 reg_list
[i
].name
= mips32_core_reg_list
[i
];
278 reg_list
[i
].size
= 32;
279 reg_list
[i
].value
= calloc(1, 4);
280 reg_list
[i
].dirty
= 0;
281 reg_list
[i
].valid
= 0;
282 reg_list
[i
].type
= &mips32_reg_type
;
283 reg_list
[i
].arch_info
= &arch_info
[i
];
289 int mips32_init_arch_info(struct target
*target
, struct mips32_common
*mips32
, struct jtag_tap
*tap
)
291 target
->arch_info
= mips32
;
292 mips32
->common_magic
= MIPS32_COMMON_MAGIC
;
293 mips32
->fast_data_area
= NULL
;
295 /* has breakpoint/watchpint unit been scanned */
296 mips32
->bp_scanned
= 0;
297 mips32
->data_break_list
= NULL
;
299 mips32
->ejtag_info
.tap
= tap
;
300 mips32
->read_core_reg
= mips32_read_core_reg
;
301 mips32
->write_core_reg
= mips32_write_core_reg
;
303 mips32
->ejtag_info
.scan_delay
= 2000000; /* Initial default value */
304 mips32
->ejtag_info
.mode
= 0; /* Initial default value */
309 /* run to exit point. return error if exit point was not reached. */
310 static int mips32_run_and_wait(struct target
*target
, uint32_t entry_point
,
311 int timeout_ms
, uint32_t exit_point
, struct mips32_common
*mips32
)
315 /* This code relies on the target specific resume() and poll()->debug_entry()
316 * sequence to write register values to the processor and the read them back */
317 retval
= target_resume(target
, 0, entry_point
, 0, 1);
318 if (retval
!= ERROR_OK
)
321 retval
= target_wait_state(target
, TARGET_HALTED
, timeout_ms
);
322 /* If the target fails to halt due to the breakpoint, force a halt */
323 if (retval
!= ERROR_OK
|| target
->state
!= TARGET_HALTED
) {
324 retval
= target_halt(target
);
325 if (retval
!= ERROR_OK
)
327 retval
= target_wait_state(target
, TARGET_HALTED
, 500);
328 if (retval
!= ERROR_OK
)
330 return ERROR_TARGET_TIMEOUT
;
333 pc
= buf_get_u32(mips32
->core_cache
->reg_list
[MIPS32_PC
].value
, 0, 32);
334 if (exit_point
&& (pc
!= exit_point
)) {
335 LOG_DEBUG("failed algorithm halted at 0x%" PRIx32
" ", pc
);
336 return ERROR_TARGET_TIMEOUT
;
342 int mips32_run_algorithm(struct target
*target
, int num_mem_params
,
343 struct mem_param
*mem_params
, int num_reg_params
,
344 struct reg_param
*reg_params
, uint32_t entry_point
,
345 uint32_t exit_point
, int timeout_ms
, void *arch_info
)
347 struct mips32_common
*mips32
= target_to_mips32(target
);
348 struct mips32_algorithm
*mips32_algorithm_info
= arch_info
;
349 enum mips32_isa_mode isa_mode
= mips32
->isa_mode
;
351 uint32_t context
[MIPS32NUMCOREREGS
];
353 int retval
= ERROR_OK
;
355 LOG_DEBUG("Running algorithm");
357 /* NOTE: mips32_run_algorithm requires that each algorithm uses a software breakpoint
358 * at the exit point */
360 if (mips32
->common_magic
!= MIPS32_COMMON_MAGIC
) {
361 LOG_ERROR("current target isn't a MIPS32 target");
362 return ERROR_TARGET_INVALID
;
365 if (target
->state
!= TARGET_HALTED
) {
366 LOG_WARNING("target not halted");
367 return ERROR_TARGET_NOT_HALTED
;
370 /* refresh core register cache */
371 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++) {
372 if (!mips32
->core_cache
->reg_list
[i
].valid
)
373 mips32
->read_core_reg(target
, i
);
374 context
[i
] = buf_get_u32(mips32
->core_cache
->reg_list
[i
].value
, 0, 32);
377 for (i
= 0; i
< num_mem_params
; i
++) {
378 retval
= target_write_buffer(target
, mem_params
[i
].address
,
379 mem_params
[i
].size
, mem_params
[i
].value
);
380 if (retval
!= ERROR_OK
)
384 for (i
= 0; i
< num_reg_params
; i
++) {
385 struct reg
*reg
= register_get_by_name(mips32
->core_cache
, reg_params
[i
].reg_name
, 0);
388 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
389 return ERROR_COMMAND_SYNTAX_ERROR
;
392 if (reg
->size
!= reg_params
[i
].size
) {
393 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
394 reg_params
[i
].reg_name
);
395 return ERROR_COMMAND_SYNTAX_ERROR
;
398 mips32_set_core_reg(reg
, reg_params
[i
].value
);
401 mips32
->isa_mode
= mips32_algorithm_info
->isa_mode
;
403 retval
= mips32_run_and_wait(target
, entry_point
, timeout_ms
, exit_point
, mips32
);
405 if (retval
!= ERROR_OK
)
408 for (i
= 0; i
< num_mem_params
; i
++) {
409 if (mem_params
[i
].direction
!= PARAM_OUT
) {
410 retval
= target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
,
411 mem_params
[i
].value
);
412 if (retval
!= ERROR_OK
)
417 for (i
= 0; i
< num_reg_params
; i
++) {
418 if (reg_params
[i
].direction
!= PARAM_OUT
) {
419 struct reg
*reg
= register_get_by_name(mips32
->core_cache
, reg_params
[i
].reg_name
, 0);
421 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
422 return ERROR_COMMAND_SYNTAX_ERROR
;
425 if (reg
->size
!= reg_params
[i
].size
) {
426 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
427 reg_params
[i
].reg_name
);
428 return ERROR_COMMAND_SYNTAX_ERROR
;
431 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
435 /* restore everything we saved before */
436 for (i
= 0; i
< MIPS32NUMCOREREGS
; i
++) {
438 regvalue
= buf_get_u32(mips32
->core_cache
->reg_list
[i
].value
, 0, 32);
439 if (regvalue
!= context
[i
]) {
440 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
,
441 mips32
->core_cache
->reg_list
[i
].name
, context
[i
]);
442 buf_set_u32(mips32
->core_cache
->reg_list
[i
].value
,
444 mips32
->core_cache
->reg_list
[i
].valid
= 1;
445 mips32
->core_cache
->reg_list
[i
].dirty
= 1;
449 mips32
->isa_mode
= isa_mode
;
454 int mips32_examine(struct target
*target
)
456 struct mips32_common
*mips32
= target_to_mips32(target
);
458 if (!target_was_examined(target
)) {
459 target_set_examined(target
);
461 /* we will configure later */
462 mips32
->bp_scanned
= 0;
463 mips32
->num_inst_bpoints
= 0;
464 mips32
->num_data_bpoints
= 0;
465 mips32
->num_inst_bpoints_avail
= 0;
466 mips32
->num_data_bpoints_avail
= 0;
472 int mips32_configure_break_unit(struct target
*target
)
474 /* get pointers to arch-specific information */
475 struct mips32_common
*mips32
= target_to_mips32(target
);
477 uint32_t dcr
, bpinfo
;
480 if (mips32
->bp_scanned
)
483 /* get info about breakpoint support */
484 retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
);
485 if (retval
!= ERROR_OK
)
488 if (dcr
& EJTAG_DCR_IB
) {
489 /* get number of inst breakpoints */
490 retval
= target_read_u32(target
, EJTAG_IBS
, &bpinfo
);
491 if (retval
!= ERROR_OK
)
494 mips32
->num_inst_bpoints
= (bpinfo
>> 24) & 0x0F;
495 mips32
->num_inst_bpoints_avail
= mips32
->num_inst_bpoints
;
496 mips32
->inst_break_list
= calloc(mips32
->num_inst_bpoints
, sizeof(struct mips32_comparator
));
497 for (i
= 0; i
< mips32
->num_inst_bpoints
; i
++)
498 mips32
->inst_break_list
[i
].reg_address
= EJTAG_IBA1
+ (0x100 * i
);
501 retval
= target_write_u32(target
, EJTAG_IBS
, 0);
502 if (retval
!= ERROR_OK
)
506 if (dcr
& EJTAG_DCR_DB
) {
507 /* get number of data breakpoints */
508 retval
= target_read_u32(target
, EJTAG_DBS
, &bpinfo
);
509 if (retval
!= ERROR_OK
)
512 mips32
->num_data_bpoints
= (bpinfo
>> 24) & 0x0F;
513 mips32
->num_data_bpoints_avail
= mips32
->num_data_bpoints
;
514 mips32
->data_break_list
= calloc(mips32
->num_data_bpoints
, sizeof(struct mips32_comparator
));
515 for (i
= 0; i
< mips32
->num_data_bpoints
; i
++)
516 mips32
->data_break_list
[i
].reg_address
= EJTAG_DBA1
+ (0x100 * i
);
519 retval
= target_write_u32(target
, EJTAG_DBS
, 0);
520 if (retval
!= ERROR_OK
)
524 /* check if target endianness settings matches debug control register */
525 if (((dcr
& EJTAG_DCR_ENM
) && (target
->endianness
== TARGET_LITTLE_ENDIAN
)) ||
526 (!(dcr
& EJTAG_DCR_ENM
) && (target
->endianness
== TARGET_BIG_ENDIAN
)))
527 LOG_WARNING("DCR endianness settings does not match target settings");
529 LOG_DEBUG("DCR 0x%" PRIx32
" numinst %i numdata %i", dcr
, mips32
->num_inst_bpoints
,
530 mips32
->num_data_bpoints
);
532 mips32
->bp_scanned
= 1;
537 int mips32_enable_interrupts(struct target
*target
, int enable
)
543 /* read debug control register */
544 retval
= target_read_u32(target
, EJTAG_DCR
, &dcr
);
545 if (retval
!= ERROR_OK
)
549 if (!(dcr
& EJTAG_DCR_INTE
)) {
550 /* enable interrupts */
551 dcr
|= EJTAG_DCR_INTE
;
555 if (dcr
& EJTAG_DCR_INTE
) {
556 /* disable interrupts */
557 dcr
&= ~EJTAG_DCR_INTE
;
563 retval
= target_write_u32(target
, EJTAG_DCR
, dcr
);
564 if (retval
!= ERROR_OK
)
571 int mips32_checksum_memory(struct target
*target
, uint32_t address
,
572 uint32_t count
, uint32_t *checksum
)
574 struct working_area
*crc_algorithm
;
575 struct reg_param reg_params
[2];
576 struct mips32_algorithm mips32_info
;
580 /* see contib/loaders/checksum/mips32.s for src */
582 static const uint32_t mips_crc_code
[] = {
583 0x248C0000, /* addiu $t4, $a0, 0 */
584 0x24AA0000, /* addiu $t2, $a1, 0 */
585 0x2404FFFF, /* addiu $a0, $zero, 0xffffffff */
586 0x10000010, /* beq $zero, $zero, ncomp */
587 0x240B0000, /* addiu $t3, $zero, 0 */
589 0x81850000, /* lb $a1, ($t4) */
590 0x218C0001, /* addi $t4, $t4, 1 */
591 0x00052E00, /* sll $a1, $a1, 24 */
592 0x3C0204C1, /* lui $v0, 0x04c1 */
593 0x00852026, /* xor $a0, $a0, $a1 */
594 0x34471DB7, /* ori $a3, $v0, 0x1db7 */
595 0x00003021, /* addu $a2, $zero, $zero */
597 0x00044040, /* sll $t0, $a0, 1 */
598 0x24C60001, /* addiu $a2, $a2, 1 */
599 0x28840000, /* slti $a0, $a0, 0 */
600 0x01074826, /* xor $t1, $t0, $a3 */
601 0x0124400B, /* movn $t0, $t1, $a0 */
602 0x28C30008, /* slti $v1, $a2, 8 */
603 0x1460FFF9, /* bne $v1, $zero, loop */
604 0x01002021, /* addu $a0, $t0, $zero */
606 0x154BFFF0, /* bne $t2, $t3, nbyte */
607 0x256B0001, /* addiu $t3, $t3, 1 */
608 0x7000003F, /* sdbbp */
611 /* make sure we have a working area */
612 if (target_alloc_working_area(target
, sizeof(mips_crc_code
), &crc_algorithm
) != ERROR_OK
)
613 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
615 /* convert flash writing code into a buffer in target endianness */
616 for (i
= 0; i
< ARRAY_SIZE(mips_crc_code
); i
++)
617 target_write_u32(target
, crc_algorithm
->address
+ i
*sizeof(uint32_t), mips_crc_code
[i
]);
619 mips32_info
.common_magic
= MIPS32_COMMON_MAGIC
;
620 mips32_info
.isa_mode
= MIPS32_ISA_MIPS32
;
622 init_reg_param(®_params
[0], "a0", 32, PARAM_IN_OUT
);
623 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
625 init_reg_param(®_params
[1], "a1", 32, PARAM_OUT
);
626 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
628 int timeout
= 20000 * (1 + (count
/ (1024 * 1024)));
630 retval
= target_run_algorithm(target
, 0, NULL
, 2, reg_params
,
631 crc_algorithm
->address
, crc_algorithm
->address
+ (sizeof(mips_crc_code
)-4), timeout
,
633 if (retval
!= ERROR_OK
) {
634 destroy_reg_param(®_params
[0]);
635 destroy_reg_param(®_params
[1]);
636 target_free_working_area(target
, crc_algorithm
);
640 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
642 destroy_reg_param(®_params
[0]);
643 destroy_reg_param(®_params
[1]);
645 target_free_working_area(target
, crc_algorithm
);
650 /** Checks whether a memory region is zeroed. */
651 int mips32_blank_check_memory(struct target
*target
,
652 uint32_t address
, uint32_t count
, uint32_t *blank
)
654 struct working_area
*erase_check_algorithm
;
655 struct reg_param reg_params
[3];
656 struct mips32_algorithm mips32_info
;
660 static const uint32_t erase_check_code
[] = {
662 0x80880000, /* lb $t0, ($a0) */
663 0x00C83024, /* and $a2, $a2, $t0 */
664 0x24A5FFFF, /* addiu $a1, $a1, -1 */
665 0x14A0FFFC, /* bne $a1, $zero, nbyte */
666 0x24840001, /* addiu $a0, $a0, 1 */
667 0x7000003F /* sdbbp */
670 /* make sure we have a working area */
671 if (target_alloc_working_area(target
, sizeof(erase_check_code
), &erase_check_algorithm
) != ERROR_OK
)
672 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
674 /* convert flash writing code into a buffer in target endianness */
675 for (i
= 0; i
< ARRAY_SIZE(erase_check_code
); i
++) {
676 target_write_u32(target
, erase_check_algorithm
->address
+ i
*sizeof(uint32_t),
677 erase_check_code
[i
]);
680 mips32_info
.common_magic
= MIPS32_COMMON_MAGIC
;
681 mips32_info
.isa_mode
= MIPS32_ISA_MIPS32
;
683 init_reg_param(®_params
[0], "a0", 32, PARAM_OUT
);
684 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
686 init_reg_param(®_params
[1], "a1", 32, PARAM_OUT
);
687 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
689 init_reg_param(®_params
[2], "a2", 32, PARAM_IN_OUT
);
690 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
692 retval
= target_run_algorithm(target
, 0, NULL
, 3, reg_params
,
693 erase_check_algorithm
->address
,
694 erase_check_algorithm
->address
+ (sizeof(erase_check_code
)-4),
695 10000, &mips32_info
);
696 if (retval
!= ERROR_OK
) {
697 destroy_reg_param(®_params
[0]);
698 destroy_reg_param(®_params
[1]);
699 destroy_reg_param(®_params
[2]);
700 target_free_working_area(target
, erase_check_algorithm
);
704 *blank
= buf_get_u32(reg_params
[2].value
, 0, 32);
706 destroy_reg_param(®_params
[0]);
707 destroy_reg_param(®_params
[1]);
708 destroy_reg_param(®_params
[2]);
710 target_free_working_area(target
, erase_check_algorithm
);
715 static int mips32_verify_pointer(struct command_context
*cmd_ctx
,
716 struct mips32_common
*mips32
)
718 if (mips32
->common_magic
!= MIPS32_COMMON_MAGIC
) {
719 command_print(cmd_ctx
, "target is not an MIPS32");
720 return ERROR_TARGET_INVALID
;
726 * MIPS32 targets expose command interface
727 * to manipulate CP0 registers
729 COMMAND_HANDLER(mips32_handle_cp0_command
)
732 struct target
*target
= get_current_target(CMD_CTX
);
733 struct mips32_common
*mips32
= target_to_mips32(target
);
734 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
737 retval
= mips32_verify_pointer(CMD_CTX
, mips32
);
738 if (retval
!= ERROR_OK
)
741 if (target
->state
!= TARGET_HALTED
) {
742 command_print(CMD_CTX
, "target must be stopped for \"%s\" command", CMD_NAME
);
746 /* two or more argument, access a single register/select (write if third argument is given) */
748 return ERROR_COMMAND_SYNTAX_ERROR
;
750 uint32_t cp0_reg
, cp0_sel
;
751 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], cp0_reg
);
752 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], cp0_sel
);
757 retval
= mips32_cp0_read(ejtag_info
, &value
, cp0_reg
, cp0_sel
);
758 if (retval
!= ERROR_OK
) {
759 command_print(CMD_CTX
,
760 "couldn't access reg %" PRIi32
,
764 command_print(CMD_CTX
, "cp0 reg %" PRIi32
", select %" PRIi32
": %8.8" PRIx32
,
765 cp0_reg
, cp0_sel
, value
);
767 } else if (CMD_ARGC
== 3) {
769 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[2], value
);
770 retval
= mips32_cp0_write(ejtag_info
, value
, cp0_reg
, cp0_sel
);
771 if (retval
!= ERROR_OK
) {
772 command_print(CMD_CTX
,
773 "couldn't access cp0 reg %" PRIi32
", select %" PRIi32
,
777 command_print(CMD_CTX
, "cp0 reg %" PRIi32
", select %" PRIi32
": %8.8" PRIx32
,
778 cp0_reg
, cp0_sel
, value
);
785 COMMAND_HANDLER(mips32_handle_scan_delay_command
)
787 struct target
*target
= get_current_target(CMD_CTX
);
788 struct mips32_common
*mips32
= target_to_mips32(target
);
789 struct mips_ejtag
*ejtag_info
= &mips32
->ejtag_info
;
792 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], ejtag_info
->scan_delay
);
793 else if (CMD_ARGC
> 1)
794 return ERROR_COMMAND_SYNTAX_ERROR
;
796 command_print(CMD_CTX
, "scan delay: %d nsec", ejtag_info
->scan_delay
);
797 if (ejtag_info
->scan_delay
>= 2000000) {
798 ejtag_info
->mode
= 0;
799 command_print(CMD_CTX
, "running in legacy mode");
801 ejtag_info
->mode
= 1;
802 command_print(CMD_CTX
, "running in fast queued mode");
808 static const struct command_registration mips32_exec_command_handlers
[] = {
811 .handler
= mips32_handle_cp0_command
,
812 .mode
= COMMAND_EXEC
,
813 .usage
= "regnum select [value]",
814 .help
= "display/modify cp0 register",
817 .name
= "scan_delay",
818 .handler
= mips32_handle_scan_delay_command
,
820 .help
= "display/set scan delay in nano seconds",
823 COMMAND_REGISTRATION_DONE
826 const struct command_registration mips32_command_handlers
[] = {
830 .help
= "mips32 command group",
832 .chain
= mips32_exec_command_handlers
,
834 COMMAND_REGISTRATION_DONE
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