1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. *
19 ***************************************************************************/
28 #include "arm_disassembler.h"
30 #include "etm_dummy.h"
32 #if BUILD_OOCD_TRACE == 1
33 #include "oocd_trace.h"
38 * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
40 * ETM modules collect instruction and/or data trace information, compress
41 * it, and transfer it to a debugging host through either a (buffered) trace
42 * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
44 * There are several generations of these modules. Original versions have
45 * JTAG access through a dedicated scan chain. Recent versions have added
46 * access via coprocessor instructions, memory addressing, and the ARM Debug
47 * Interface v5 (ADIv5); and phased out direct JTAG access.
49 * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
50 * most common ARM9 systems. Note: "CoreSight ETM9" implements ETMv3.2,
51 * implying non-JTAG connectivity options.
53 * Relevant documentation includes:
54 * ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
55 * ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
56 * ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
67 uint8_t size
; /* low-N of 32 bits */
68 uint8_t mode
; /* RO, WO, RW */
69 uint8_t bcd_vers
; /* 1.0, 2.0, etc */
74 * Registers 0..0x7f are JTAG-addressable using scanchain 6.
75 * (Or on some processors, through coprocessor operations.)
76 * Newer versions of ETM make some W/O registers R/W, and
77 * provide definitions for some previously-unused bits.
80 /* core registers used to version/configure the ETM */
81 static const struct etm_reg_info etm_core
[] = {
82 /* NOTE: we "know" the order here ... */
83 { ETM_CONFIG
, 32, RO
, 0x10, "ETM_config", },
84 { ETM_ID
, 32, RO
, 0x20, "ETM_id", },
87 /* basic registers that are always there given the right ETM version */
88 static const struct etm_reg_info etm_basic
[] = {
89 /* ETM Trace Registers */
90 { ETM_CTRL
, 32, RW
, 0x10, "ETM_ctrl", },
91 { ETM_TRIG_EVENT
, 17, WO
, 0x10, "ETM_trig_event", },
92 { ETM_ASIC_CTRL
, 8, WO
, 0x10, "ETM_asic_ctrl", },
93 { ETM_STATUS
, 3, RO
, 0x11, "ETM_status", },
94 { ETM_SYS_CONFIG
, 9, RO
, 0x12, "ETM_sys_config", },
96 /* TraceEnable configuration */
97 { ETM_TRACE_RESOURCE_CTRL
, 32, WO
, 0x12, "ETM_trace_resource_ctrl", },
98 { ETM_TRACE_EN_CTRL2
, 16, WO
, 0x12, "ETM_trace_en_ctrl2", },
99 { ETM_TRACE_EN_EVENT
, 17, WO
, 0x10, "ETM_trace_en_event", },
100 { ETM_TRACE_EN_CTRL1
, 26, WO
, 0x10, "ETM_trace_en_ctrl1", },
102 /* ViewData configuration (data trace) */
103 { ETM_VIEWDATA_EVENT
, 17, WO
, 0x10, "ETM_viewdata_event", },
104 { ETM_VIEWDATA_CTRL1
, 32, WO
, 0x10, "ETM_viewdata_ctrl1", },
105 { ETM_VIEWDATA_CTRL2
, 32, WO
, 0x10, "ETM_viewdata_ctrl2", },
106 { ETM_VIEWDATA_CTRL3
, 17, WO
, 0x10, "ETM_viewdata_ctrl3", },
108 /* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
110 { 0x78, 12, WO
, 0x20, "ETM_sync_freq", },
111 { 0x7a, 22, RO
, 0x31, "ETM_config_code_ext", },
112 { 0x7b, 32, WO
, 0x31, "ETM_ext_input_select", },
113 { 0x7c, 32, WO
, 0x34, "ETM_trace_start_stop", },
114 { 0x7d, 8, WO
, 0x34, "ETM_behavior_control", },
117 static const struct etm_reg_info etm_fifofull
[] = {
118 /* FIFOFULL configuration */
119 { ETM_FIFOFULL_REGION
, 25, WO
, 0x10, "ETM_fifofull_region", },
120 { ETM_FIFOFULL_LEVEL
, 8, WO
, 0x10, "ETM_fifofull_level", },
123 static const struct etm_reg_info etm_addr_comp
[] = {
124 /* Address comparator register pairs */
125 #define ADDR_COMPARATOR(i) \
126 { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
127 "ETM_addr_" #i "_comparator_value", }, \
128 { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
129 "ETM_addr_" #i "_access_type", }
147 #undef ADDR_COMPARATOR
150 static const struct etm_reg_info etm_data_comp
[] = {
151 /* Data Value Comparators (NOTE: odd addresses are reserved) */
152 #define DATA_COMPARATOR(i) \
153 { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
154 "ETM_data_" #i "_comparator_value", }, \
155 { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
156 "ETM_data_" #i "_comparator_mask", }
165 #undef DATA_COMPARATOR
168 static const struct etm_reg_info etm_counters
[] = {
169 #define ETM_COUNTER(i) \
170 { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
171 "ETM_counter_" #i "_reload_value", }, \
172 { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
173 "ETM_counter_" #i "_enable", }, \
174 { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
175 "ETM_counter_" #i "_reload_event", }, \
176 { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
177 "ETM_counter_" #i "_value", }
185 static const struct etm_reg_info etm_sequencer
[] = {
187 { ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
188 "ETM_sequencer_event" #i, }
189 ETM_SEQ(0), /* 1->2 */
190 ETM_SEQ(1), /* 2->1 */
191 ETM_SEQ(2), /* 2->3 */
192 ETM_SEQ(3), /* 3->1 */
193 ETM_SEQ(4), /* 3->2 */
194 ETM_SEQ(5), /* 1->3 */
197 { ETM_SEQUENCER_STATE
, 2, RO
, 0x10, "ETM_sequencer_state", },
200 static const struct etm_reg_info etm_outputs
[] = {
201 #define ETM_OUTPUT(i) \
202 { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
203 "ETM_external_output" #i, }
213 /* registers from 0x6c..0x7f were added after ETMv1.3 */
215 /* Context ID Comparators */
216 { 0x6c, 32, RO
, 0x20, "ETM_contextid_comparator_value1", }
217 { 0x6d, 32, RO
, 0x20, "ETM_contextid_comparator_value2", }
218 { 0x6e, 32, RO
, 0x20, "ETM_contextid_comparator_value3", }
219 { 0x6f, 32, RO
, 0x20, "ETM_contextid_comparator_mask", }
222 static int etm_get_reg(struct reg
*reg
);
223 static int etm_read_reg_w_check(struct reg
*reg
,
224 uint8_t *check_value
, uint8_t *check_mask
);
225 static int etm_register_user_commands(struct command_context
*cmd_ctx
);
226 static int etm_set_reg_w_exec(struct reg
*reg
, uint8_t *buf
);
227 static int etm_write_reg(struct reg
*reg
, uint32_t value
);
229 static const struct reg_arch_type etm_scan6_type
= {
231 .set
= etm_set_reg_w_exec
,
234 /* Look up register by ID ... most ETM instances only
235 * support a subset of the possible registers.
237 static struct reg
*etm_reg_lookup(struct etm_context
*etm_ctx
, unsigned id
)
239 struct reg_cache
*cache
= etm_ctx
->reg_cache
;
242 for (i
= 0; i
< cache
->num_regs
; i
++) {
243 struct etm_reg
*reg
= cache
->reg_list
[i
].arch_info
;
245 if (reg
->reg_info
->addr
== id
)
246 return &cache
->reg_list
[i
];
249 /* caller asking for nonexistent register is a bug!
250 * REVISIT say which of the N targets was involved */
251 LOG_ERROR("ETM: register 0x%02x not available", id
);
255 static void etm_reg_add(unsigned bcd_vers
, struct arm_jtag
*jtag_info
,
256 struct reg_cache
*cache
, struct etm_reg
*ereg
,
257 const struct etm_reg_info
*r
, unsigned nreg
)
259 struct reg
*reg
= cache
->reg_list
;
261 reg
+= cache
->num_regs
;
262 ereg
+= cache
->num_regs
;
264 /* add up to "nreg" registers from "r", if supported by this
265 * version of the ETM, to the specified cache.
267 for (; nreg
--; r
++) {
269 /* this ETM may be too old to have some registers */
270 if (r
->bcd_vers
> bcd_vers
)
275 reg
->value
= &ereg
->value
;
276 reg
->arch_info
= ereg
;
277 reg
->type
= &etm_scan6_type
;
282 ereg
->jtag_info
= jtag_info
;
287 struct reg_cache
*etm_build_reg_cache(struct target
*target
,
288 struct arm_jtag
*jtag_info
, struct etm_context
*etm_ctx
)
290 struct reg_cache
*reg_cache
= malloc(sizeof(struct reg_cache
));
291 struct reg
*reg_list
= NULL
;
292 struct etm_reg
*arch_info
= NULL
;
293 unsigned bcd_vers
, config
;
295 /* the actual registers are kept in two arrays */
296 reg_list
= calloc(128, sizeof(struct reg
));
297 arch_info
= calloc(128, sizeof(struct etm_reg
));
299 /* fill in values for the reg cache */
300 reg_cache
->name
= "etm registers";
301 reg_cache
->next
= NULL
;
302 reg_cache
->reg_list
= reg_list
;
303 reg_cache
->num_regs
= 0;
305 /* add ETM_CONFIG, then parse its values to see
306 * which other registers exist in this ETM
308 etm_reg_add(0x10, jtag_info
, reg_cache
, arch_info
,
311 etm_get_reg(reg_list
);
312 etm_ctx
->config
= buf_get_u32((void *)&arch_info
->value
, 0, 32);
313 config
= etm_ctx
->config
;
315 /* figure ETM version then add base registers */
316 if (config
& (1 << 31)) {
317 LOG_WARNING("ETMv2+ support is incomplete");
319 /* REVISIT more registers may exist; they may now be
320 * readable; more register bits have defined meanings;
321 * don't presume trace start/stop support is present;
322 * and include any context ID comparator registers.
324 etm_reg_add(0x20, jtag_info
, reg_cache
, arch_info
,
326 etm_get_reg(reg_list
+ 1);
327 etm_ctx
->id
= buf_get_u32(
328 (void *)&arch_info
[1].value
, 0, 32);
329 LOG_DEBUG("ETM ID: %08x", (unsigned) etm_ctx
->id
);
330 bcd_vers
= 0x10 + (((etm_ctx
->id
) >> 4) & 0xff);
333 switch (config
>> 28) {
350 LOG_WARNING("Bad ETMv1 protocol %d", config
>> 28);
354 etm_ctx
->bcd_vers
= bcd_vers
;
355 LOG_INFO("ETM v%d.%d", bcd_vers
>> 4, bcd_vers
& 0xf);
357 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
358 etm_basic
, ARRAY_SIZE(etm_basic
));
360 /* address and data comparators; counters; outputs */
361 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
362 etm_addr_comp
, 4 * (0x0f & (config
>> 0)));
363 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
364 etm_data_comp
, 2 * (0x0f & (config
>> 4)));
365 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
366 etm_counters
, 4 * (0x07 & (config
>> 13)));
367 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
368 etm_outputs
, (0x07 & (config
>> 20)));
370 /* FIFOFULL presence is optional
371 * REVISIT for ETMv1.2 and later, don't bother adding this
372 * unless ETM_SYS_CONFIG says it's also *supported* ...
374 if (config
& (1 << 23))
375 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
376 etm_fifofull
, ARRAY_SIZE(etm_fifofull
));
378 /* sequencer is optional (for state-dependant triggering) */
379 if (config
& (1 << 16))
380 etm_reg_add(bcd_vers
, jtag_info
, reg_cache
, arch_info
,
381 etm_sequencer
, ARRAY_SIZE(etm_sequencer
));
383 /* REVISIT could realloc and likely save half the memory
384 * in the two chunks we allocated...
387 /* the ETM might have an ETB connected */
388 if (strcmp(etm_ctx
->capture_driver
->name
, "etb") == 0) {
389 struct etb
*etb
= etm_ctx
->capture_driver_priv
;
392 LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
396 reg_cache
->next
= etb_build_reg_cache(etb
);
398 etb
->reg_cache
= reg_cache
->next
;
401 etm_ctx
->reg_cache
= reg_cache
;
411 static int etm_read_reg(struct reg
*reg
)
413 return etm_read_reg_w_check(reg
, NULL
, NULL
);
416 static int etm_store_reg(struct reg
*reg
)
418 return etm_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
421 int etm_setup(struct target
*target
)
424 uint32_t etm_ctrl_value
;
425 struct arm
*arm
= target_to_arm(target
);
426 struct etm_context
*etm_ctx
= arm
->etm
;
427 struct reg
*etm_ctrl_reg
;
429 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
433 /* initialize some ETM control register settings */
434 etm_get_reg(etm_ctrl_reg
);
435 etm_ctrl_value
= buf_get_u32(etm_ctrl_reg
->value
, 0, 32);
437 /* clear the ETM powerdown bit (0) */
438 etm_ctrl_value
&= ~ETM_CTRL_POWERDOWN
;
440 /* configure port width (21,6:4), mode (13,17:16) and
441 * for older modules clocking (13)
443 etm_ctrl_value
= (etm_ctrl_value
444 & ~ETM_PORT_WIDTH_MASK
445 & ~ETM_PORT_MODE_MASK
447 & ~ETM_PORT_CLOCK_MASK
)
450 buf_set_u32(etm_ctrl_reg
->value
, 0, 32, etm_ctrl_value
);
451 etm_store_reg(etm_ctrl_reg
);
453 etm_ctx
->control
= etm_ctrl_value
;
455 retval
= jtag_execute_queue();
456 if (retval
!= ERROR_OK
)
459 /* REVISIT for ETMv3.0 and later, read ETM_sys_config to
460 * verify that those width and mode settings are OK ...
463 retval
= etm_ctx
->capture_driver
->init(etm_ctx
);
464 if (retval
!= ERROR_OK
) {
465 LOG_ERROR("ETM capture driver initialization failed");
471 static int etm_get_reg(struct reg
*reg
)
475 retval
= etm_read_reg(reg
);
476 if (retval
!= ERROR_OK
) {
477 LOG_ERROR("BUG: error scheduling etm register read");
481 retval
= jtag_execute_queue();
482 if (retval
!= ERROR_OK
) {
483 LOG_ERROR("register read failed");
490 static int etm_read_reg_w_check(struct reg
*reg
,
491 uint8_t *check_value
, uint8_t *check_mask
)
493 struct etm_reg
*etm_reg
= reg
->arch_info
;
494 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
495 uint8_t reg_addr
= r
->addr
& 0x7f;
496 struct scan_field fields
[3];
499 if (etm_reg
->reg_info
->mode
== WO
) {
500 LOG_ERROR("BUG: can't read write-only register %s", r
->name
);
501 return ERROR_COMMAND_SYNTAX_ERROR
;
504 LOG_DEBUG("%s (%u)", r
->name
, reg_addr
);
506 retval
= arm_jtag_scann(etm_reg
->jtag_info
, 0x6, TAP_IDLE
);
507 if (retval
!= ERROR_OK
)
509 retval
= arm_jtag_set_instr(etm_reg
->jtag_info
,
510 etm_reg
->jtag_info
->intest_instr
,
513 if (retval
!= ERROR_OK
)
516 fields
[0].num_bits
= 32;
517 fields
[0].out_value
= reg
->value
;
518 fields
[0].in_value
= NULL
;
519 fields
[0].check_value
= NULL
;
520 fields
[0].check_mask
= NULL
;
522 fields
[1].num_bits
= 7;
524 fields
[1].out_value
= &temp1
;
525 buf_set_u32(&temp1
, 0, 7, reg_addr
);
526 fields
[1].in_value
= NULL
;
527 fields
[1].check_value
= NULL
;
528 fields
[1].check_mask
= NULL
;
530 fields
[2].num_bits
= 1;
532 fields
[2].out_value
= &temp2
;
533 buf_set_u32(&temp2
, 0, 1, 0);
534 fields
[2].in_value
= NULL
;
535 fields
[2].check_value
= NULL
;
536 fields
[2].check_mask
= NULL
;
538 jtag_add_dr_scan(etm_reg
->jtag_info
->tap
, 3, fields
, TAP_IDLE
);
540 fields
[0].in_value
= reg
->value
;
541 fields
[0].check_value
= check_value
;
542 fields
[0].check_mask
= check_mask
;
544 jtag_add_dr_scan_check(etm_reg
->jtag_info
->tap
, 3, fields
, TAP_IDLE
);
549 static int etm_set_reg(struct reg
*reg
, uint32_t value
)
551 int retval
= etm_write_reg(reg
, value
);
552 if (retval
!= ERROR_OK
) {
553 LOG_ERROR("BUG: error scheduling etm register write");
557 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
564 static int etm_set_reg_w_exec(struct reg
*reg
, uint8_t *buf
)
568 etm_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
570 retval
= jtag_execute_queue();
571 if (retval
!= ERROR_OK
) {
572 LOG_ERROR("register write failed");
578 static int etm_write_reg(struct reg
*reg
, uint32_t value
)
580 struct etm_reg
*etm_reg
= reg
->arch_info
;
581 const struct etm_reg_info
*r
= etm_reg
->reg_info
;
582 uint8_t reg_addr
= r
->addr
& 0x7f;
583 struct scan_field fields
[3];
586 if (etm_reg
->reg_info
->mode
== RO
) {
587 LOG_ERROR("BUG: can't write read--only register %s", r
->name
);
588 return ERROR_COMMAND_SYNTAX_ERROR
;
591 LOG_DEBUG("%s (%u): 0x%8.8" PRIx32
"", r
->name
, reg_addr
, value
);
593 retval
= arm_jtag_scann(etm_reg
->jtag_info
, 0x6, TAP_IDLE
);
594 if (retval
!= ERROR_OK
)
596 retval
= arm_jtag_set_instr(etm_reg
->jtag_info
,
597 etm_reg
->jtag_info
->intest_instr
,
600 if (retval
!= ERROR_OK
)
603 fields
[0].num_bits
= 32;
605 fields
[0].out_value
= tmp1
;
606 buf_set_u32(tmp1
, 0, 32, value
);
607 fields
[0].in_value
= NULL
;
609 fields
[1].num_bits
= 7;
611 fields
[1].out_value
= &tmp2
;
612 buf_set_u32(&tmp2
, 0, 7, reg_addr
);
613 fields
[1].in_value
= NULL
;
615 fields
[2].num_bits
= 1;
617 fields
[2].out_value
= &tmp3
;
618 buf_set_u32(&tmp3
, 0, 1, 1);
619 fields
[2].in_value
= NULL
;
621 jtag_add_dr_scan(etm_reg
->jtag_info
->tap
, 3, fields
, TAP_IDLE
);
627 /* ETM trace analysis functionality */
629 static struct etm_capture_driver
*etm_capture_drivers
[] = {
631 &etm_dummy_capture_driver
,
632 #if BUILD_OOCD_TRACE == 1
633 &oocd_trace_capture_driver
,
638 static int etm_read_instruction(struct etm_context
*ctx
, struct arm_instruction
*instruction
)
647 return ERROR_TRACE_IMAGE_UNAVAILABLE
;
649 /* search for the section the current instruction belongs to */
650 for (i
= 0; i
< ctx
->image
->num_sections
; i
++) {
651 if ((ctx
->image
->sections
[i
].base_address
<= ctx
->current_pc
) &&
652 (ctx
->image
->sections
[i
].base_address
+ ctx
->image
->sections
[i
].size
>
660 /* current instruction couldn't be found in the image */
661 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
664 if (ctx
->core_state
== ARM_STATE_ARM
) {
666 retval
= image_read_section(ctx
->image
, section
,
668 ctx
->image
->sections
[section
].base_address
,
670 if (retval
!= ERROR_OK
) {
671 LOG_ERROR("error while reading instruction");
672 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
674 opcode
= target_buffer_get_u32(ctx
->target
, buf
);
675 arm_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
676 } else if (ctx
->core_state
== ARM_STATE_THUMB
) {
678 retval
= image_read_section(ctx
->image
, section
,
680 ctx
->image
->sections
[section
].base_address
,
682 if (retval
!= ERROR_OK
) {
683 LOG_ERROR("error while reading instruction");
684 return ERROR_TRACE_INSTRUCTION_UNAVAILABLE
;
686 opcode
= target_buffer_get_u16(ctx
->target
, buf
);
687 thumb_evaluate_opcode(opcode
, ctx
->current_pc
, instruction
);
688 } else if (ctx
->core_state
== ARM_STATE_JAZELLE
) {
689 LOG_ERROR("BUG: tracing of jazelle code not supported");
692 LOG_ERROR("BUG: unknown core state encountered");
699 static int etmv1_next_packet(struct etm_context
*ctx
, uint8_t *packet
, int apo
)
701 while (ctx
->data_index
< ctx
->trace_depth
) {
702 /* if the caller specified an address packet offset, skip until the
703 * we reach the n-th cycle marked with tracesync */
705 if (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRACESYNC_CYCLE
)
715 /* no tracedata output during a TD cycle
716 * or in a trigger cycle */
717 if ((ctx
->trace_data
[ctx
->data_index
].pipestat
== STAT_TD
)
718 || (ctx
->trace_data
[ctx
->data_index
].flags
& ETMV1_TRIGGER_CYCLE
)) {
724 /* FIXME there are more port widths than these... */
725 if ((ctx
->control
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_16BIT
) {
726 if (ctx
->data_half
== 0) {
727 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
730 *packet
= (ctx
->trace_data
[ctx
->data_index
].packet
& 0xff00) >> 8;
734 } else if ((ctx
->control
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
) {
735 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xff;
738 /* on a 4-bit port, a packet will be output during two consecutive cycles */
739 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
742 *packet
= ctx
->trace_data
[ctx
->data_index
].packet
& 0xf;
743 *packet
|= (ctx
->trace_data
[ctx
->data_index
+ 1].packet
& 0xf) << 4;
744 ctx
->data_index
+= 2;
753 static int etmv1_branch_address(struct etm_context
*ctx
)
761 /* quit analysis if less than two cycles are left in the trace
762 * because we can't extract the APO */
763 if (ctx
->data_index
> (ctx
->trace_depth
- 2))
766 /* a BE could be output during an APO cycle, skip the current
767 * and continue with the new one */
768 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x4)
770 if (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x4)
773 /* address packet offset encoded in the next two cycles' pipestat bits */
774 apo
= ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& 0x3;
775 apo
|= (ctx
->trace_data
[ctx
->pipe_index
+ 2].pipestat
& 0x3) << 2;
777 /* count number of tracesync cycles between current pipe_index and data_index
778 * i.e. the number of tracesyncs that data_index already passed by
779 * to subtract them from the APO */
780 for (i
= ctx
->pipe_index
; i
< ctx
->data_index
; i
++) {
781 if (ctx
->trace_data
[ctx
->pipe_index
+ 1].pipestat
& ETMV1_TRACESYNC_CYCLE
)
785 /* extract up to four 7-bit packets */
787 retval
= etmv1_next_packet(ctx
, &packet
, (shift
== 0) ? apo
+ 1 : 0);
790 ctx
->last_branch
&= ~(0x7f << shift
);
791 ctx
->last_branch
|= (packet
& 0x7f) << shift
;
793 } while ((packet
& 0x80) && (shift
< 28));
795 /* one last packet holding 4 bits of the address, plus the branch reason code */
796 if ((shift
== 28) && (packet
& 0x80)) {
797 retval
= etmv1_next_packet(ctx
, &packet
, 0);
800 ctx
->last_branch
&= 0x0fffffff;
801 ctx
->last_branch
|= (packet
& 0x0f) << 28;
802 ctx
->last_branch_reason
= (packet
& 0x70) >> 4;
805 ctx
->last_branch_reason
= 0;
810 /* if a full address was output, we might have branched into Jazelle state */
811 if ((shift
== 32) && (packet
& 0x80))
812 ctx
->core_state
= ARM_STATE_JAZELLE
;
814 /* if we didn't branch into Jazelle state, the current processor state is
815 * encoded in bit 0 of the branch target address */
816 if (ctx
->last_branch
& 0x1) {
817 ctx
->core_state
= ARM_STATE_THUMB
;
818 ctx
->last_branch
&= ~0x1;
820 ctx
->core_state
= ARM_STATE_ARM
;
821 ctx
->last_branch
&= ~0x3;
828 static int etmv1_data(struct etm_context
*ctx
, int size
, uint32_t *data
)
834 for (j
= 0; j
< size
; j
++) {
835 retval
= etmv1_next_packet(ctx
, &buf
[j
], 0);
841 LOG_ERROR("TODO: add support for 64-bit values");
843 } else if (size
== 4)
844 *data
= target_buffer_get_u32(ctx
->target
, buf
);
846 *data
= target_buffer_get_u16(ctx
->target
, buf
);
855 static int etmv1_analyze_trace(struct etm_context
*ctx
, struct command_context
*cmd_ctx
)
858 struct arm_instruction instruction
;
860 /* read the trace data if it wasn't read already */
861 if (ctx
->trace_depth
== 0)
862 ctx
->capture_driver
->read_trace(ctx
);
864 if (ctx
->trace_depth
== 0) {
865 command_print(cmd_ctx
, "Trace is empty.");
869 /* start at the beginning of the captured trace */
874 /* neither the PC nor the data pointer are valid */
878 while (ctx
->pipe_index
< ctx
->trace_depth
) {
879 uint8_t pipestat
= ctx
->trace_data
[ctx
->pipe_index
].pipestat
;
880 uint32_t next_pc
= ctx
->current_pc
;
881 uint32_t old_data_index
= ctx
->data_index
;
882 uint32_t old_data_half
= ctx
->data_half
;
883 uint32_t old_index
= ctx
->pipe_index
;
884 uint32_t last_instruction
= ctx
->last_instruction
;
886 int current_pc_ok
= ctx
->pc_ok
;
888 if (ctx
->trace_data
[ctx
->pipe_index
].flags
& ETMV1_TRIGGER_CYCLE
)
889 command_print(cmd_ctx
, "--- trigger ---");
891 /* instructions execute in IE/D or BE/D cycles */
892 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
))
893 ctx
->last_instruction
= ctx
->pipe_index
;
895 /* if we don't have a valid pc skip until we reach an indirect branch */
896 if ((!ctx
->pc_ok
) && (pipestat
!= STAT_BE
)) {
901 /* any indirect branch could have interrupted instruction flow
902 * - the branch reason code could indicate a trace discontinuity
903 * - a branch to the exception vectors indicates an exception
905 if ((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) {
906 /* backup current data index, to be able to consume the branch address
907 * before examining data address and values
909 old_data_index
= ctx
->data_index
;
910 old_data_half
= ctx
->data_half
;
912 ctx
->last_instruction
= ctx
->pipe_index
;
914 retval
= etmv1_branch_address(ctx
);
916 /* negative return value from etmv1_branch_address means we ran out of packets,
917 * quit analysing the trace */
921 /* a positive return values means the current branch was abandoned,
922 * and a new branch was encountered in cycle ctx->pipe_index + retval;
925 "abandoned branch encountered, correctnes of analysis uncertain");
926 ctx
->pipe_index
+= retval
;
930 /* skip over APO cycles */
931 ctx
->pipe_index
+= 2;
933 switch (ctx
->last_branch_reason
) {
934 case 0x0: /* normal PC change */
935 next_pc
= ctx
->last_branch
;
937 case 0x1: /* tracing enabled */
938 command_print(cmd_ctx
,
939 "--- tracing enabled at 0x%8.8" PRIx32
" ---",
941 ctx
->current_pc
= ctx
->last_branch
;
945 case 0x2: /* trace restarted after FIFO overflow */
946 command_print(cmd_ctx
,
947 "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32
" ---",
949 ctx
->current_pc
= ctx
->last_branch
;
953 case 0x3: /* exit from debug state */
954 command_print(cmd_ctx
,
955 "--- exit from debug state at 0x%8.8" PRIx32
" ---",
957 ctx
->current_pc
= ctx
->last_branch
;
961 case 0x4: /* periodic synchronization point */
962 next_pc
= ctx
->last_branch
;
963 /* if we had no valid PC prior to this synchronization point,
964 * we have to move on with the next trace cycle
966 if (!current_pc_ok
) {
967 command_print(cmd_ctx
,
968 "--- periodic synchronization point at 0x%8.8" PRIx32
" ---",
970 ctx
->current_pc
= next_pc
;
975 default: /* reserved */
977 "BUG: branch reason code 0x%" PRIx32
" is reserved",
978 ctx
->last_branch_reason
);
982 /* if we got here the branch was a normal PC change
983 * (or a periodic synchronization point, which means the same for that matter)
984 * if we didn't accquire a complete PC continue with the next cycle
989 /* indirect branch to the exception vector means an exception occured */
990 if ((ctx
->last_branch
<= 0x20)
991 || ((ctx
->last_branch
>= 0xffff0000) &&
992 (ctx
->last_branch
<= 0xffff0020))) {
993 if ((ctx
->last_branch
& 0xff) == 0x10)
994 command_print(cmd_ctx
, "data abort");
996 command_print(cmd_ctx
,
997 "exception vector 0x%2.2" PRIx32
"",
999 ctx
->current_pc
= ctx
->last_branch
;
1006 /* an instruction was executed (or not, depending on the condition flags)
1007 * retrieve it from the image for displaying */
1008 if (ctx
->pc_ok
&& (pipestat
!= STAT_WT
) && (pipestat
!= STAT_TD
) &&
1009 !(((pipestat
== STAT_BE
) || (pipestat
== STAT_BD
)) &&
1010 ((ctx
->last_branch_reason
!= 0x0) && (ctx
->last_branch_reason
!= 0x4)))) {
1011 retval
= etm_read_instruction(ctx
, &instruction
);
1012 if (retval
!= ERROR_OK
) {
1013 /* can't continue tracing with no image available */
1014 if (retval
== ERROR_TRACE_IMAGE_UNAVAILABLE
)
1016 else if (retval
== ERROR_TRACE_INSTRUCTION_UNAVAILABLE
) {
1017 /* TODO: handle incomplete images
1018 * for now we just quit the analsysis*/
1023 cycles
= old_index
- last_instruction
;
1026 if ((pipestat
== STAT_ID
) || (pipestat
== STAT_BD
)) {
1027 uint32_t new_data_index
= ctx
->data_index
;
1028 uint32_t new_data_half
= ctx
->data_half
;
1030 /* in case of a branch with data, the branch target address was consumed before
1031 * we temporarily go back to the saved data index */
1032 if (pipestat
== STAT_BD
) {
1033 ctx
->data_index
= old_data_index
;
1034 ctx
->data_half
= old_data_half
;
1037 if (ctx
->control
& ETM_CTRL_TRACE_ADDR
) {
1042 retval
= etmv1_next_packet(ctx
, &packet
, 0);
1044 return ERROR_ETM_ANALYSIS_FAILED
;
1045 ctx
->last_ptr
&= ~(0x7f << shift
);
1046 ctx
->last_ptr
|= (packet
& 0x7f) << shift
;
1048 } while ((packet
& 0x80) && (shift
< 32));
1054 command_print(cmd_ctx
,
1055 "address: 0x%8.8" PRIx32
"",
1059 if (ctx
->control
& ETM_CTRL_TRACE_DATA
) {
1060 if ((instruction
.type
== ARM_LDM
) ||
1061 (instruction
.type
== ARM_STM
)) {
1063 for (i
= 0; i
< 16; i
++) {
1064 if (instruction
.info
.load_store_multiple
.
1065 register_list
& (1 << i
)) {
1067 if (etmv1_data(ctx
, 4, &data
) != 0)
1068 return ERROR_ETM_ANALYSIS_FAILED
;
1069 command_print(cmd_ctx
,
1070 "data: 0x%8.8" PRIx32
"",
1074 } else if ((instruction
.type
>= ARM_LDR
) &&
1075 (instruction
.type
<= ARM_STRH
)) {
1077 if (etmv1_data(ctx
, arm_access_size(&instruction
),
1079 return ERROR_ETM_ANALYSIS_FAILED
;
1080 command_print(cmd_ctx
, "data: 0x%8.8" PRIx32
"", data
);
1084 /* restore data index after consuming BD address and data */
1085 if (pipestat
== STAT_BD
) {
1086 ctx
->data_index
= new_data_index
;
1087 ctx
->data_half
= new_data_half
;
1092 if ((pipestat
== STAT_IE
) || (pipestat
== STAT_ID
)) {
1093 if (((instruction
.type
== ARM_B
) ||
1094 (instruction
.type
== ARM_BL
) ||
1095 (instruction
.type
== ARM_BLX
)) &&
1096 (instruction
.info
.b_bl_bx_blx
.target_address
!= 0xffffffff))
1097 next_pc
= instruction
.info
.b_bl_bx_blx
.target_address
;
1099 next_pc
+= (ctx
->core_state
== ARM_STATE_ARM
) ? 4 : 2;
1100 } else if (pipestat
== STAT_IN
)
1101 next_pc
+= (ctx
->core_state
== ARM_STATE_ARM
) ? 4 : 2;
1103 if ((pipestat
!= STAT_TD
) && (pipestat
!= STAT_WT
)) {
1104 char cycles_text
[32] = "";
1106 /* if the trace was captured with cycle accurate tracing enabled,
1107 * output the number of cycles since the last executed instruction
1109 if (ctx
->control
& ETM_CTRL_CYCLE_ACCURATE
) {
1110 snprintf(cycles_text
, 32, " (%i %s)",
1112 (cycles
== 1) ? "cycle" : "cycles");
1115 command_print(cmd_ctx
, "%s%s%s",
1117 (pipestat
== STAT_IN
) ? " (not executed)" : "",
1120 ctx
->current_pc
= next_pc
;
1122 /* packets for an instruction don't start on or before the preceding
1123 * functional pipestat (i.e. other than WT or TD)
1125 if (ctx
->data_index
<= ctx
->pipe_index
) {
1126 ctx
->data_index
= ctx
->pipe_index
+ 1;
1131 ctx
->pipe_index
+= 1;
1137 static COMMAND_HELPER(handle_etm_tracemode_command_update
,
1142 /* what parts of data access are traced? */
1143 if (strcmp(CMD_ARGV
[0], "none") == 0)
1145 else if (strcmp(CMD_ARGV
[0], "data") == 0)
1146 tracemode
= ETM_CTRL_TRACE_DATA
;
1147 else if (strcmp(CMD_ARGV
[0], "address") == 0)
1148 tracemode
= ETM_CTRL_TRACE_ADDR
;
1149 else if (strcmp(CMD_ARGV
[0], "all") == 0)
1150 tracemode
= ETM_CTRL_TRACE_DATA
| ETM_CTRL_TRACE_ADDR
;
1152 command_print(CMD_CTX
, "invalid option '%s'", CMD_ARGV
[0]);
1153 return ERROR_COMMAND_SYNTAX_ERROR
;
1157 COMMAND_PARSE_NUMBER(u8
, CMD_ARGV
[1], context_id
);
1158 switch (context_id
) {
1160 tracemode
|= ETM_CTRL_CONTEXTID_NONE
;
1163 tracemode
|= ETM_CTRL_CONTEXTID_8
;
1166 tracemode
|= ETM_CTRL_CONTEXTID_16
;
1169 tracemode
|= ETM_CTRL_CONTEXTID_32
;
1172 command_print(CMD_CTX
, "invalid option '%s'", CMD_ARGV
[1]);
1173 return ERROR_COMMAND_SYNTAX_ERROR
;
1176 bool etmv1_cycle_accurate
;
1177 COMMAND_PARSE_ENABLE(CMD_ARGV
[2], etmv1_cycle_accurate
);
1178 if (etmv1_cycle_accurate
)
1179 tracemode
|= ETM_CTRL_CYCLE_ACCURATE
;
1181 bool etmv1_branch_output
;
1182 COMMAND_PARSE_ENABLE(CMD_ARGV
[3], etmv1_branch_output
);
1183 if (etmv1_branch_output
)
1184 tracemode
|= ETM_CTRL_BRANCH_OUTPUT
;
1187 * - CPRT tracing (coprocessor register transfers)
1188 * - debug request (causes debug entry on trigger)
1189 * - stall on FIFOFULL (preventing tracedata lossage)
1196 COMMAND_HANDLER(handle_etm_tracemode_command
)
1198 struct target
*target
= get_current_target(CMD_CTX
);
1199 struct arm
*arm
= target_to_arm(target
);
1200 struct etm_context
*etm
;
1203 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1209 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1213 uint32_t tracemode
= etm
->control
;
1219 CALL_COMMAND_HANDLER(handle_etm_tracemode_command_update
,
1223 return ERROR_COMMAND_SYNTAX_ERROR
;
1227 * todo: fail if parameters were invalid for this hardware,
1228 * or couldn't be written; display actual hardware state...
1231 command_print(CMD_CTX
, "current tracemode configuration:");
1233 switch (tracemode
& ETM_CTRL_TRACE_MASK
) {
1235 command_print(CMD_CTX
, "data tracing: none");
1237 case ETM_CTRL_TRACE_DATA
:
1238 command_print(CMD_CTX
, "data tracing: data only");
1240 case ETM_CTRL_TRACE_ADDR
:
1241 command_print(CMD_CTX
, "data tracing: address only");
1243 case ETM_CTRL_TRACE_DATA
| ETM_CTRL_TRACE_ADDR
:
1244 command_print(CMD_CTX
, "data tracing: address and data");
1248 switch (tracemode
& ETM_CTRL_CONTEXTID_MASK
) {
1249 case ETM_CTRL_CONTEXTID_NONE
:
1250 command_print(CMD_CTX
, "contextid tracing: none");
1252 case ETM_CTRL_CONTEXTID_8
:
1253 command_print(CMD_CTX
, "contextid tracing: 8 bit");
1255 case ETM_CTRL_CONTEXTID_16
:
1256 command_print(CMD_CTX
, "contextid tracing: 16 bit");
1258 case ETM_CTRL_CONTEXTID_32
:
1259 command_print(CMD_CTX
, "contextid tracing: 32 bit");
1263 if (tracemode
& ETM_CTRL_CYCLE_ACCURATE
)
1264 command_print(CMD_CTX
, "cycle-accurate tracing enabled");
1266 command_print(CMD_CTX
, "cycle-accurate tracing disabled");
1268 if (tracemode
& ETM_CTRL_BRANCH_OUTPUT
)
1269 command_print(CMD_CTX
, "full branch address output enabled");
1271 command_print(CMD_CTX
, "full branch address output disabled");
1273 #define TRACEMODE_MASK ( \
1274 ETM_CTRL_CONTEXTID_MASK \
1275 | ETM_CTRL_BRANCH_OUTPUT \
1276 | ETM_CTRL_CYCLE_ACCURATE \
1277 | ETM_CTRL_TRACE_MASK \
1280 /* only update ETM_CTRL register if tracemode changed */
1281 if ((etm
->control
& TRACEMODE_MASK
) != tracemode
) {
1282 struct reg
*etm_ctrl_reg
;
1284 etm_ctrl_reg
= etm_reg_lookup(etm
, ETM_CTRL
);
1288 etm
->control
&= ~TRACEMODE_MASK
;
1289 etm
->control
|= tracemode
& TRACEMODE_MASK
;
1291 buf_set_u32(etm_ctrl_reg
->value
, 0, 32, etm
->control
);
1292 etm_store_reg(etm_ctrl_reg
);
1294 /* invalidate old trace data */
1295 etm
->capture_status
= TRACE_IDLE
;
1296 if (etm
->trace_depth
> 0) {
1297 free(etm
->trace_data
);
1298 etm
->trace_data
= NULL
;
1300 etm
->trace_depth
= 0;
1303 #undef TRACEMODE_MASK
1308 COMMAND_HANDLER(handle_etm_config_command
)
1310 struct target
*target
;
1312 uint32_t portmode
= 0x0;
1313 struct etm_context
*etm_ctx
;
1317 return ERROR_COMMAND_SYNTAX_ERROR
;
1319 target
= get_target(CMD_ARGV
[0]);
1321 LOG_ERROR("target '%s' not defined", CMD_ARGV
[0]);
1325 arm
= target_to_arm(target
);
1327 command_print(CMD_CTX
, "target '%s' is '%s'; not an ARM",
1328 target_name(target
),
1329 target_type_name(target
));
1333 /* FIXME for ETMv3.0 and above -- and we don't yet know what ETM
1334 * version we'll be using!! -- so we can't know how to validate
1335 * params yet. "etm config" should likely be *AFTER* hookup...
1337 * - Many more widths might be supported ... and we can easily
1338 * check whether our setting "took".
1340 * - The "clock" and "mode" bits are interpreted differently.
1341 * See ARM IHI 0014O table 2-17 for the old behavior, and
1342 * table 2-18 for the new. With ETB it's best to specify
1346 COMMAND_PARSE_NUMBER(u8
, CMD_ARGV
[1], port_width
);
1347 switch (port_width
) {
1348 /* before ETMv3.0 */
1350 portmode
|= ETM_PORT_4BIT
;
1353 portmode
|= ETM_PORT_8BIT
;
1356 portmode
|= ETM_PORT_16BIT
;
1358 /* ETMv3.0 and later*/
1360 portmode
|= ETM_PORT_24BIT
;
1363 portmode
|= ETM_PORT_32BIT
;
1366 portmode
|= ETM_PORT_48BIT
;
1369 portmode
|= ETM_PORT_64BIT
;
1372 portmode
|= ETM_PORT_1BIT
;
1375 portmode
|= ETM_PORT_2BIT
;
1378 command_print(CMD_CTX
,
1379 "unsupported ETM port width '%s'", CMD_ARGV
[1]);
1383 if (strcmp("normal", CMD_ARGV
[2]) == 0)
1384 portmode
|= ETM_PORT_NORMAL
;
1385 else if (strcmp("multiplexed", CMD_ARGV
[2]) == 0)
1386 portmode
|= ETM_PORT_MUXED
;
1387 else if (strcmp("demultiplexed", CMD_ARGV
[2]) == 0)
1388 portmode
|= ETM_PORT_DEMUXED
;
1390 command_print(CMD_CTX
,
1391 "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'",
1396 if (strcmp("half", CMD_ARGV
[3]) == 0)
1397 portmode
|= ETM_PORT_HALF_CLOCK
;
1398 else if (strcmp("full", CMD_ARGV
[3]) == 0)
1399 portmode
|= ETM_PORT_FULL_CLOCK
;
1401 command_print(CMD_CTX
,
1402 "unsupported ETM port clocking '%s', must be 'full' or 'half'",
1407 etm_ctx
= calloc(1, sizeof(struct etm_context
));
1409 LOG_DEBUG("out of memory");
1413 for (i
= 0; etm_capture_drivers
[i
]; i
++) {
1414 if (strcmp(CMD_ARGV
[4], etm_capture_drivers
[i
]->name
) == 0) {
1415 int retval
= register_commands(CMD_CTX
, NULL
,
1416 etm_capture_drivers
[i
]->commands
);
1417 if (ERROR_OK
!= retval
) {
1422 etm_ctx
->capture_driver
= etm_capture_drivers
[i
];
1428 if (!etm_capture_drivers
[i
]) {
1429 /* no supported capture driver found, don't register an ETM */
1431 LOG_ERROR("trace capture driver '%s' not found", CMD_ARGV
[4]);
1435 etm_ctx
->target
= target
;
1436 etm_ctx
->trace_data
= NULL
;
1437 etm_ctx
->control
= portmode
;
1438 etm_ctx
->core_state
= ARM_STATE_ARM
;
1442 return etm_register_user_commands(CMD_CTX
);
1445 COMMAND_HANDLER(handle_etm_info_command
)
1447 struct target
*target
;
1449 struct etm_context
*etm
;
1450 struct reg
*etm_sys_config_reg
;
1454 target
= get_current_target(CMD_CTX
);
1455 arm
= target_to_arm(target
);
1457 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1463 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1467 command_print(CMD_CTX
, "ETM v%d.%d",
1468 etm
->bcd_vers
>> 4, etm
->bcd_vers
& 0xf);
1469 command_print(CMD_CTX
, "pairs of address comparators: %i",
1470 (int) (etm
->config
>> 0) & 0x0f);
1471 command_print(CMD_CTX
, "data comparators: %i",
1472 (int) (etm
->config
>> 4) & 0x0f);
1473 command_print(CMD_CTX
, "memory map decoders: %i",
1474 (int) (etm
->config
>> 8) & 0x1f);
1475 command_print(CMD_CTX
, "number of counters: %i",
1476 (int) (etm
->config
>> 13) & 0x07);
1477 command_print(CMD_CTX
, "sequencer %spresent",
1478 (int) (etm
->config
& (1 << 16)) ? "" : "not ");
1479 command_print(CMD_CTX
, "number of ext. inputs: %i",
1480 (int) (etm
->config
>> 17) & 0x07);
1481 command_print(CMD_CTX
, "number of ext. outputs: %i",
1482 (int) (etm
->config
>> 20) & 0x07);
1483 command_print(CMD_CTX
, "FIFO full %spresent",
1484 (int) (etm
->config
& (1 << 23)) ? "" : "not ");
1485 if (etm
->bcd_vers
< 0x20)
1486 command_print(CMD_CTX
, "protocol version: %i",
1487 (int) (etm
->config
>> 28) & 0x07);
1489 command_print(CMD_CTX
,
1490 "coprocessor and memory access %ssupported",
1491 (etm
->config
& (1 << 26)) ? "" : "not ");
1492 command_print(CMD_CTX
, "trace start/stop %spresent",
1493 (etm
->config
& (1 << 26)) ? "" : "not ");
1494 command_print(CMD_CTX
, "number of context comparators: %i",
1495 (int) (etm
->config
>> 24) & 0x03);
1498 /* SYS_CONFIG isn't present before ETMv1.2 */
1499 etm_sys_config_reg
= etm_reg_lookup(etm
, ETM_SYS_CONFIG
);
1500 if (!etm_sys_config_reg
)
1503 etm_get_reg(etm_sys_config_reg
);
1504 config
= buf_get_u32(etm_sys_config_reg
->value
, 0, 32);
1506 LOG_DEBUG("ETM SYS CONFIG %08x", (unsigned) config
);
1508 max_port_size
= config
& 0x7;
1509 if (etm
->bcd_vers
>= 0x30)
1510 max_port_size
|= (config
>> 6) & 0x08;
1511 switch (max_port_size
) {
1512 /* before ETMv3.0 */
1522 /* ETMv3.0 and later*/
1542 LOG_ERROR("Illegal max_port_size");
1545 command_print(CMD_CTX
, "max. port size: %i", max_port_size
);
1547 if (etm
->bcd_vers
< 0x30) {
1548 command_print(CMD_CTX
, "half-rate clocking %ssupported",
1549 (config
& (1 << 3)) ? "" : "not ");
1550 command_print(CMD_CTX
, "full-rate clocking %ssupported",
1551 (config
& (1 << 4)) ? "" : "not ");
1552 command_print(CMD_CTX
, "normal trace format %ssupported",
1553 (config
& (1 << 5)) ? "" : "not ");
1554 command_print(CMD_CTX
, "multiplex trace format %ssupported",
1555 (config
& (1 << 6)) ? "" : "not ");
1556 command_print(CMD_CTX
, "demultiplex trace format %ssupported",
1557 (config
& (1 << 7)) ? "" : "not ");
1559 /* REVISIT show which size and format are selected ... */
1560 command_print(CMD_CTX
, "current port size %ssupported",
1561 (config
& (1 << 10)) ? "" : "not ");
1562 command_print(CMD_CTX
, "current trace format %ssupported",
1563 (config
& (1 << 11)) ? "" : "not ");
1565 if (etm
->bcd_vers
>= 0x21)
1566 command_print(CMD_CTX
, "fetch comparisons %ssupported",
1567 (config
& (1 << 17)) ? "not " : "");
1568 command_print(CMD_CTX
, "FIFO full %ssupported",
1569 (config
& (1 << 8)) ? "" : "not ");
1574 COMMAND_HANDLER(handle_etm_status_command
)
1576 struct target
*target
;
1578 struct etm_context
*etm
;
1579 trace_status_t trace_status
;
1581 target
= get_current_target(CMD_CTX
);
1582 arm
= target_to_arm(target
);
1584 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1590 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1595 if (etm
->bcd_vers
>= 0x11) {
1598 reg
= etm_reg_lookup(etm
, ETM_STATUS
);
1601 if (etm_get_reg(reg
) == ERROR_OK
) {
1602 unsigned s
= buf_get_u32(reg
->value
, 0, reg
->size
);
1604 command_print(CMD_CTX
, "etm: %s%s%s%s",
1605 /* bit(1) == progbit */
1606 (etm
->bcd_vers
>= 0x12)
1608 ? "disabled" : "enabled")
1610 ((s
& (1 << 3)) && etm
->bcd_vers
>= 0x31)
1611 ? " triggered" : "",
1612 ((s
& (1 << 2)) && etm
->bcd_vers
>= 0x12)
1613 ? " start/stop" : "",
1614 ((s
& (1 << 0)) && etm
->bcd_vers
>= 0x11)
1615 ? " untraced-overflow" : "");
1616 } /* else ignore and try showing trace port status */
1619 /* Trace Port Driver status */
1620 trace_status
= etm
->capture_driver
->status(etm
);
1621 if (trace_status
== TRACE_IDLE
)
1622 command_print(CMD_CTX
, "%s: idle", etm
->capture_driver
->name
);
1624 static char *completed
= " completed";
1625 static char *running
= " is running";
1626 static char *overflowed
= ", overflowed";
1627 static char *triggered
= ", triggered";
1629 command_print(CMD_CTX
, "%s: trace collection%s%s%s",
1630 etm
->capture_driver
->name
,
1631 (trace_status
& TRACE_RUNNING
) ? running
: completed
,
1632 (trace_status
& TRACE_OVERFLOWED
) ? overflowed
: "",
1633 (trace_status
& TRACE_TRIGGERED
) ? triggered
: "");
1635 if (etm
->trace_depth
> 0) {
1636 command_print(CMD_CTX
, "%i frames of trace data read",
1637 (int)(etm
->trace_depth
));
1644 COMMAND_HANDLER(handle_etm_image_command
)
1646 struct target
*target
;
1648 struct etm_context
*etm_ctx
;
1651 return ERROR_COMMAND_SYNTAX_ERROR
;
1653 target
= get_current_target(CMD_CTX
);
1654 arm
= target_to_arm(target
);
1656 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1662 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1666 if (etm_ctx
->image
) {
1667 image_close(etm_ctx
->image
);
1668 free(etm_ctx
->image
);
1669 command_print(CMD_CTX
, "previously loaded image found and closed");
1672 etm_ctx
->image
= malloc(sizeof(struct image
));
1673 etm_ctx
->image
->base_address_set
= 0;
1674 etm_ctx
->image
->start_address_set
= 0;
1676 /* a base address isn't always necessary, default to 0x0 (i.e. don't relocate) */
1677 if (CMD_ARGC
>= 2) {
1678 etm_ctx
->image
->base_address_set
= 1;
1679 COMMAND_PARSE_NUMBER(llong
, CMD_ARGV
[1], etm_ctx
->image
->base_address
);
1681 etm_ctx
->image
->base_address_set
= 0;
1683 if (image_open(etm_ctx
->image
, CMD_ARGV
[0],
1684 (CMD_ARGC
>= 3) ? CMD_ARGV
[2] : NULL
) != ERROR_OK
) {
1685 free(etm_ctx
->image
);
1686 etm_ctx
->image
= NULL
;
1693 COMMAND_HANDLER(handle_etm_dump_command
)
1696 struct target
*target
;
1698 struct etm_context
*etm_ctx
;
1702 return ERROR_COMMAND_SYNTAX_ERROR
;
1704 target
= get_current_target(CMD_CTX
);
1705 arm
= target_to_arm(target
);
1707 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1713 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1717 if (etm_ctx
->capture_driver
->status
== TRACE_IDLE
) {
1718 command_print(CMD_CTX
, "trace capture wasn't enabled, no trace data captured");
1722 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
) {
1723 /* TODO: if on-the-fly capture is to be supported, this needs to be changed */
1724 command_print(CMD_CTX
, "trace capture not completed");
1728 /* read the trace data if it wasn't read already */
1729 if (etm_ctx
->trace_depth
== 0)
1730 etm_ctx
->capture_driver
->read_trace(etm_ctx
);
1732 if (fileio_open(&file
, CMD_ARGV
[0], FILEIO_WRITE
, FILEIO_BINARY
) != ERROR_OK
)
1735 fileio_write_u32(&file
, etm_ctx
->capture_status
);
1736 fileio_write_u32(&file
, etm_ctx
->control
);
1737 fileio_write_u32(&file
, etm_ctx
->trace_depth
);
1739 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++) {
1740 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].pipestat
);
1741 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].packet
);
1742 fileio_write_u32(&file
, etm_ctx
->trace_data
[i
].flags
);
1745 fileio_close(&file
);
1750 COMMAND_HANDLER(handle_etm_load_command
)
1753 struct target
*target
;
1755 struct etm_context
*etm_ctx
;
1759 return ERROR_COMMAND_SYNTAX_ERROR
;
1761 target
= get_current_target(CMD_CTX
);
1762 arm
= target_to_arm(target
);
1764 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1770 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1774 if (etm_ctx
->capture_driver
->status(etm_ctx
) & TRACE_RUNNING
) {
1775 command_print(CMD_CTX
, "trace capture running, stop first");
1779 if (fileio_open(&file
, CMD_ARGV
[0], FILEIO_READ
, FILEIO_BINARY
) != ERROR_OK
)
1783 int retval
= fileio_size(&file
, &filesize
);
1784 if (retval
!= ERROR_OK
) {
1785 fileio_close(&file
);
1790 command_print(CMD_CTX
, "size isn't a multiple of 4, no valid trace data");
1791 fileio_close(&file
);
1795 if (etm_ctx
->trace_depth
> 0) {
1796 free(etm_ctx
->trace_data
);
1797 etm_ctx
->trace_data
= NULL
;
1802 fileio_read_u32(&file
, &tmp
); etm_ctx
->capture_status
= tmp
;
1803 fileio_read_u32(&file
, &tmp
); etm_ctx
->control
= tmp
;
1804 fileio_read_u32(&file
, &etm_ctx
->trace_depth
);
1806 etm_ctx
->trace_data
= malloc(sizeof(struct etmv1_trace_data
) * etm_ctx
->trace_depth
);
1807 if (etm_ctx
->trace_data
== NULL
) {
1808 command_print(CMD_CTX
, "not enough memory to perform operation");
1809 fileio_close(&file
);
1813 for (i
= 0; i
< etm_ctx
->trace_depth
; i
++) {
1814 uint32_t pipestat
, packet
, flags
;
1815 fileio_read_u32(&file
, &pipestat
);
1816 fileio_read_u32(&file
, &packet
);
1817 fileio_read_u32(&file
, &flags
);
1818 etm_ctx
->trace_data
[i
].pipestat
= pipestat
& 0xff;
1819 etm_ctx
->trace_data
[i
].packet
= packet
& 0xffff;
1820 etm_ctx
->trace_data
[i
].flags
= flags
;
1823 fileio_close(&file
);
1828 COMMAND_HANDLER(handle_etm_start_command
)
1830 struct target
*target
;
1832 struct etm_context
*etm_ctx
;
1833 struct reg
*etm_ctrl_reg
;
1835 target
= get_current_target(CMD_CTX
);
1836 arm
= target_to_arm(target
);
1838 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1844 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1848 /* invalidate old tracing data */
1849 etm_ctx
->capture_status
= TRACE_IDLE
;
1850 if (etm_ctx
->trace_depth
> 0) {
1851 free(etm_ctx
->trace_data
);
1852 etm_ctx
->trace_data
= NULL
;
1854 etm_ctx
->trace_depth
= 0;
1856 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1860 etm_get_reg(etm_ctrl_reg
);
1862 /* Clear programming bit (10), set port selection bit (11) */
1863 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x2);
1865 etm_store_reg(etm_ctrl_reg
);
1866 jtag_execute_queue();
1868 etm_ctx
->capture_driver
->start_capture(etm_ctx
);
1873 COMMAND_HANDLER(handle_etm_stop_command
)
1875 struct target
*target
;
1877 struct etm_context
*etm_ctx
;
1878 struct reg
*etm_ctrl_reg
;
1880 target
= get_current_target(CMD_CTX
);
1881 arm
= target_to_arm(target
);
1883 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1889 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1893 etm_ctrl_reg
= etm_reg_lookup(etm_ctx
, ETM_CTRL
);
1897 etm_get_reg(etm_ctrl_reg
);
1899 /* Set programming bit (10), clear port selection bit (11) */
1900 buf_set_u32(etm_ctrl_reg
->value
, 10, 2, 0x1);
1902 etm_store_reg(etm_ctrl_reg
);
1903 jtag_execute_queue();
1905 etm_ctx
->capture_driver
->stop_capture(etm_ctx
);
1910 COMMAND_HANDLER(handle_etm_trigger_debug_command
)
1912 struct target
*target
;
1914 struct etm_context
*etm
;
1916 target
= get_current_target(CMD_CTX
);
1917 arm
= target_to_arm(target
);
1919 command_print(CMD_CTX
, "ETM: %s isn't an ARM",
1920 target_name(target
));
1926 command_print(CMD_CTX
, "ETM: no ETM configured for %s",
1927 target_name(target
));
1931 if (CMD_ARGC
== 1) {
1932 struct reg
*etm_ctrl_reg
;
1935 etm_ctrl_reg
= etm_reg_lookup(etm
, ETM_CTRL
);
1939 COMMAND_PARSE_ENABLE(CMD_ARGV
[0], dbgrq
);
1941 etm
->control
|= ETM_CTRL_DBGRQ
;
1943 etm
->control
&= ~ETM_CTRL_DBGRQ
;
1945 /* etm->control will be written to hardware
1946 * the next time an "etm start" is issued.
1948 buf_set_u32(etm_ctrl_reg
->value
, 0, 32, etm
->control
);
1951 command_print(CMD_CTX
, "ETM: %s debug halt",
1952 (etm
->control
& ETM_CTRL_DBGRQ
)
1954 : "does not trigger");
1958 COMMAND_HANDLER(handle_etm_analyze_command
)
1960 struct target
*target
;
1962 struct etm_context
*etm_ctx
;
1965 target
= get_current_target(CMD_CTX
);
1966 arm
= target_to_arm(target
);
1968 command_print(CMD_CTX
, "ETM: current target isn't an ARM");
1974 command_print(CMD_CTX
, "current target doesn't have an ETM configured");
1978 retval
= etmv1_analyze_trace(etm_ctx
, CMD_CTX
);
1979 if (retval
!= ERROR_OK
) {
1980 /* FIX! error should be reported inside etmv1_analyze_trace() */
1982 case ERROR_ETM_ANALYSIS_FAILED
:
1983 command_print(CMD_CTX
,
1984 "further analysis failed (corrupted trace data or just end of data");
1986 case ERROR_TRACE_INSTRUCTION_UNAVAILABLE
:
1987 command_print(CMD_CTX
,
1988 "no instruction for current address available, analysis aborted");
1990 case ERROR_TRACE_IMAGE_UNAVAILABLE
:
1991 command_print(CMD_CTX
, "no image available for trace analysis");
1994 command_print(CMD_CTX
, "unknown error");
2001 static const struct command_registration etm_config_command_handlers
[] = {
2003 /* NOTE: with ADIv5, ETMs are accessed by DAP operations,
2004 * possibly over SWD, not JTAG scanchain 6 of 'target'.
2006 * Also, these parameters don't match ETM v3+ modules...
2009 .handler
= handle_etm_config_command
,
2010 .mode
= COMMAND_CONFIG
,
2011 .help
= "Set up ETM output port.",
2012 .usage
= "target port_width port_mode clocking capture_driver",
2014 COMMAND_REGISTRATION_DONE
2016 const struct command_registration etm_command_handlers
[] = {
2019 .mode
= COMMAND_ANY
,
2020 .help
= "Emebdded Trace Macrocell command group",
2022 .chain
= etm_config_command_handlers
,
2024 COMMAND_REGISTRATION_DONE
2027 static const struct command_registration etm_exec_command_handlers
[] = {
2029 .name
= "tracemode",
2030 .handler
= handle_etm_tracemode_command
,
2031 .mode
= COMMAND_EXEC
,
2032 .help
= "configure/display trace mode",
2033 .usage
= "('none'|'data'|'address'|'all') "
2035 "['enable'|'disable'] "
2036 "['enable'|'disable']",
2040 .handler
= handle_etm_info_command
,
2041 .mode
= COMMAND_EXEC
,
2043 .help
= "display info about the current target's ETM",
2047 .handler
= handle_etm_status_command
,
2048 .mode
= COMMAND_EXEC
,
2050 .help
= "display current target's ETM status",
2054 .handler
= handle_etm_start_command
,
2055 .mode
= COMMAND_EXEC
,
2057 .help
= "start ETM trace collection",
2061 .handler
= handle_etm_stop_command
,
2062 .mode
= COMMAND_EXEC
,
2064 .help
= "stop ETM trace collection",
2067 .name
= "trigger_debug",
2068 .handler
= handle_etm_trigger_debug_command
,
2069 .mode
= COMMAND_EXEC
,
2070 .help
= "enable/disable debug entry on trigger",
2071 .usage
= "['enable'|'disable']",
2075 .handler
= handle_etm_analyze_command
,
2076 .mode
= COMMAND_EXEC
,
2078 .help
= "analyze collected ETM trace",
2082 .handler
= handle_etm_image_command
,
2083 .mode
= COMMAND_EXEC
,
2084 .help
= "load image from file with optional offset",
2085 .usage
= "<file> [base address] [type]",
2089 .handler
= handle_etm_dump_command
,
2090 .mode
= COMMAND_EXEC
,
2091 .help
= "dump captured trace data to file",
2092 .usage
= "filename",
2096 .handler
= handle_etm_load_command
,
2097 .mode
= COMMAND_EXEC
,
2099 .help
= "load trace data for analysis <file>",
2101 COMMAND_REGISTRATION_DONE
2104 static int etm_register_user_commands(struct command_context
*cmd_ctx
)
2106 struct command
*etm_cmd
= command_find_in_context(cmd_ctx
, "etm");
2107 return register_commands(cmd_ctx
, etm_cmd
, etm_exec_command_handlers
);
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