1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
32 #include "binarybuffer.h"
39 char* etb_reg_list
[] =
46 "ETB_ram_read_pointer",
47 "ETB_ram_write_pointer",
48 "ETB_trigger_counter",
52 int etb_reg_arch_type
= -1;
54 int etb_get_reg(reg_t
*reg
);
55 int etb_set_reg(reg_t
*reg
, u32 value
);
56 int etb_set_reg_w_exec(reg_t
*reg
, u8
*buf
);
58 int etb_write_reg(reg_t
*reg
, u32 value
);
59 int etb_read_reg(reg_t
*reg
);
61 int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
63 int etb_set_instr(etb_t
*etb
, u32 new_instr
)
65 jtag_device_t
*device
= jtag_get_device(etb
->chain_pos
);
67 if (buf_get_u32(device
->cur_instr
, 0, device
->ir_length
) != new_instr
)
71 field
.device
= etb
->chain_pos
;
72 field
.num_bits
= device
->ir_length
;
73 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
74 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
75 field
.out_mask
= NULL
;
76 field
.in_value
= NULL
;
77 field
.in_check_value
= NULL
;
78 field
.in_check_mask
= NULL
;
79 field
.in_handler
= NULL
;
80 field
.in_handler_priv
= NULL
;
82 jtag_add_ir_scan(1, &field
, -1);
84 free(field
.out_value
);
90 int etb_scann(etb_t
*etb
, u32 new_scan_chain
)
92 if(etb
->cur_scan_chain
!= new_scan_chain
)
96 field
.device
= etb
->chain_pos
;
98 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
99 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_scan_chain
);
100 field
.out_mask
= NULL
;
101 field
.in_value
= NULL
;
102 field
.in_check_value
= NULL
;
103 field
.in_check_mask
= NULL
;
104 field
.in_handler
= NULL
;
105 field
.in_handler_priv
= NULL
;
107 /* select INTEST instruction */
108 etb_set_instr(etb
, 0x2);
109 jtag_add_dr_scan(1, &field
, -1);
111 etb
->cur_scan_chain
= new_scan_chain
;
113 free(field
.out_value
);
119 reg_cache_t
* etb_build_reg_cache(etb_t
*etb
)
121 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
122 reg_t
*reg_list
= NULL
;
123 etb_reg_t
*arch_info
= NULL
;
127 /* register a register arch-type for etm registers only once */
128 if (etb_reg_arch_type
== -1)
129 etb_reg_arch_type
= register_reg_arch_type(etb_get_reg
, etb_set_reg_w_exec
);
131 /* the actual registers are kept in two arrays */
132 reg_list
= calloc(num_regs
, sizeof(reg_t
));
133 arch_info
= calloc(num_regs
, sizeof(etb_reg_t
));
135 /* fill in values for the reg cache */
136 reg_cache
->name
= "etb registers";
137 reg_cache
->next
= NULL
;
138 reg_cache
->reg_list
= reg_list
;
139 reg_cache
->num_regs
= num_regs
;
141 /* set up registers */
142 for (i
= 0; i
< num_regs
; i
++)
144 reg_list
[i
].name
= etb_reg_list
[i
];
145 reg_list
[i
].size
= 32;
146 reg_list
[i
].dirty
= 0;
147 reg_list
[i
].valid
= 0;
148 reg_list
[i
].bitfield_desc
= NULL
;
149 reg_list
[i
].num_bitfields
= 0;
150 reg_list
[i
].value
= calloc(1, 4);
151 reg_list
[i
].arch_info
= &arch_info
[i
];
152 reg_list
[i
].arch_type
= etb_reg_arch_type
;
153 reg_list
[i
].size
= 32;
154 arch_info
[i
].addr
= i
;
155 arch_info
[i
].etb
= etb
;
161 int etb_get_reg(reg_t
*reg
)
164 if ((retval
= etb_read_reg(reg
)) != ERROR_OK
)
166 LOG_ERROR("BUG: error scheduling etm register read");
170 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
172 LOG_ERROR("register read failed");
179 int etb_read_ram(etb_t
*etb
, u32
*data
, int num_frames
)
181 scan_field_t fields
[3];
184 jtag_add_end_state(TAP_RTI
);
186 etb_set_instr(etb
, 0xc);
188 fields
[0].device
= etb
->chain_pos
;
189 fields
[0].num_bits
= 32;
190 fields
[0].out_value
= NULL
;
191 fields
[0].out_mask
= NULL
;
192 fields
[0].in_value
= NULL
;
193 fields
[0].in_check_value
= NULL
;
194 fields
[0].in_check_mask
= NULL
;
195 fields
[0].in_handler
= NULL
;
196 fields
[0].in_handler_priv
= NULL
;
198 fields
[1].device
= etb
->chain_pos
;
199 fields
[1].num_bits
= 7;
200 fields
[1].out_value
= malloc(1);
201 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
202 fields
[1].out_mask
= NULL
;
203 fields
[1].in_value
= NULL
;
204 fields
[1].in_check_value
= NULL
;
205 fields
[1].in_check_mask
= NULL
;
206 fields
[1].in_handler
= NULL
;
207 fields
[1].in_handler_priv
= NULL
;
209 fields
[2].device
= etb
->chain_pos
;
210 fields
[2].num_bits
= 1;
211 fields
[2].out_value
= malloc(1);
212 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
213 fields
[2].out_mask
= NULL
;
214 fields
[2].in_value
= NULL
;
215 fields
[2].in_check_value
= NULL
;
216 fields
[2].in_check_mask
= NULL
;
217 fields
[2].in_handler
= NULL
;
218 fields
[2].in_handler_priv
= NULL
;
220 jtag_add_dr_scan(3, fields
, -1);
222 fields
[0].in_handler
= buf_to_u32_handler
;
224 for (i
= 0; i
< num_frames
; i
++)
226 /* ensure nR/W reamins set to read */
227 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
229 /* address remains set to 0x4 (RAM data) until we read the last frame */
230 if (i
< num_frames
- 1)
231 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
233 buf_set_u32(fields
[1].out_value
, 0, 7, 0);
235 fields
[0].in_handler_priv
= &data
[i
];
236 jtag_add_dr_scan(3, fields
, -1);
239 jtag_execute_queue();
241 free(fields
[1].out_value
);
242 free(fields
[2].out_value
);
247 int etb_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
)
249 etb_reg_t
*etb_reg
= reg
->arch_info
;
250 u8 reg_addr
= etb_reg
->addr
& 0x7f;
251 scan_field_t fields
[3];
253 LOG_DEBUG("%i", etb_reg
->addr
);
255 jtag_add_end_state(TAP_RTI
);
256 etb_scann(etb_reg
->etb
, 0x0);
257 etb_set_instr(etb_reg
->etb
, 0xc);
259 fields
[0].device
= etb_reg
->etb
->chain_pos
;
260 fields
[0].num_bits
= 32;
261 fields
[0].out_value
= reg
->value
;
262 fields
[0].out_mask
= NULL
;
263 fields
[0].in_value
= NULL
;
264 fields
[0].in_check_value
= NULL
;
265 fields
[0].in_check_mask
= NULL
;
266 fields
[0].in_handler
= NULL
;
267 fields
[0].in_handler_priv
= NULL
;
269 fields
[1].device
= etb_reg
->etb
->chain_pos
;
270 fields
[1].num_bits
= 7;
271 fields
[1].out_value
= malloc(1);
272 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
273 fields
[1].out_mask
= NULL
;
274 fields
[1].in_value
= NULL
;
275 fields
[1].in_check_value
= NULL
;
276 fields
[1].in_check_mask
= NULL
;
277 fields
[1].in_handler
= NULL
;
278 fields
[1].in_handler_priv
= NULL
;
280 fields
[2].device
= etb_reg
->etb
->chain_pos
;
281 fields
[2].num_bits
= 1;
282 fields
[2].out_value
= malloc(1);
283 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
284 fields
[2].out_mask
= NULL
;
285 fields
[2].in_value
= NULL
;
286 fields
[2].in_check_value
= NULL
;
287 fields
[2].in_check_mask
= NULL
;
288 fields
[2].in_handler
= NULL
;
289 fields
[2].in_handler_priv
= NULL
;
291 jtag_add_dr_scan(3, fields
, -1);
293 /* read the identification register in the second run, to make sure we
294 * don't read the ETB data register twice, skipping every second entry
296 buf_set_u32(fields
[1].out_value
, 0, 7, 0x0);
297 fields
[0].in_value
= reg
->value
;
299 jtag_set_check_value(fields
+0, check_value
, check_mask
, NULL
);
301 jtag_add_dr_scan(3, fields
, -1);
303 free(fields
[1].out_value
);
304 free(fields
[2].out_value
);
309 int etb_read_reg(reg_t
*reg
)
311 return etb_read_reg_w_check(reg
, NULL
, NULL
);
314 int etb_set_reg(reg_t
*reg
, u32 value
)
317 if ((retval
= etb_write_reg(reg
, value
)) != ERROR_OK
)
319 LOG_ERROR("BUG: error scheduling etm register write");
323 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
330 int etb_set_reg_w_exec(reg_t
*reg
, u8
*buf
)
333 etb_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
335 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
337 LOG_ERROR("register write failed");
343 int etb_write_reg(reg_t
*reg
, u32 value
)
345 etb_reg_t
*etb_reg
= reg
->arch_info
;
346 u8 reg_addr
= etb_reg
->addr
& 0x7f;
347 scan_field_t fields
[3];
349 LOG_DEBUG("%i: 0x%8.8x", etb_reg
->addr
, value
);
351 jtag_add_end_state(TAP_RTI
);
352 etb_scann(etb_reg
->etb
, 0x0);
353 etb_set_instr(etb_reg
->etb
, 0xc);
355 fields
[0].device
= etb_reg
->etb
->chain_pos
;
356 fields
[0].num_bits
= 32;
357 fields
[0].out_value
= malloc(4);
358 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
359 fields
[0].out_mask
= NULL
;
360 fields
[0].in_value
= NULL
;
361 fields
[0].in_check_value
= NULL
;
362 fields
[0].in_check_mask
= NULL
;
363 fields
[0].in_handler
= NULL
;
364 fields
[0].in_handler_priv
= NULL
;
366 fields
[1].device
= etb_reg
->etb
->chain_pos
;
367 fields
[1].num_bits
= 7;
368 fields
[1].out_value
= malloc(1);
369 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
370 fields
[1].out_mask
= NULL
;
371 fields
[1].in_value
= NULL
;
372 fields
[1].in_check_value
= NULL
;
373 fields
[1].in_check_mask
= NULL
;
374 fields
[1].in_handler
= NULL
;
375 fields
[1].in_handler_priv
= NULL
;
377 fields
[2].device
= etb_reg
->etb
->chain_pos
;
378 fields
[2].num_bits
= 1;
379 fields
[2].out_value
= malloc(1);
380 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
381 fields
[2].out_mask
= NULL
;
382 fields
[2].in_value
= NULL
;
383 fields
[2].in_check_value
= NULL
;
384 fields
[2].in_check_mask
= NULL
;
385 fields
[2].in_handler
= NULL
;
386 fields
[2].in_handler_priv
= NULL
;
388 jtag_add_dr_scan(3, fields
, -1);
390 free(fields
[0].out_value
);
391 free(fields
[1].out_value
);
392 free(fields
[2].out_value
);
397 int etb_store_reg(reg_t
*reg
)
399 return etb_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
402 int etb_register_commands(struct command_context_s
*cmd_ctx
)
406 etb_cmd
= register_command(cmd_ctx
, NULL
, "etb", NULL
, COMMAND_ANY
, "Embedded Trace Buffer");
408 register_command(cmd_ctx
, etb_cmd
, "config", handle_etb_config_command
, COMMAND_CONFIG
, NULL
);
413 int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
416 jtag_device_t
*jtag_device
;
417 armv4_5_common_t
*armv4_5
;
418 arm7_9_common_t
*arm7_9
;
422 return ERROR_COMMAND_SYNTAX_ERROR
;
425 target
= get_target_by_num(strtoul(args
[0], NULL
, 0));
429 LOG_ERROR("target number '%s' not defined", args
[0]);
433 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
435 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
439 jtag_device
= jtag_get_device(strtoul(args
[1], NULL
, 0));
443 LOG_ERROR("jtag device number '%s' not defined", args
[1]);
449 etb_t
*etb
= malloc(sizeof(etb_t
));
451 arm7_9
->etm_ctx
->capture_driver_priv
= etb
;
453 etb
->chain_pos
= strtoul(args
[1], NULL
, 0);
454 etb
->cur_scan_chain
= -1;
455 etb
->reg_cache
= NULL
;
461 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
468 int etb_init(etm_context_t
*etm_ctx
)
470 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
472 etb
->etm_ctx
= etm_ctx
;
474 /* identify ETB RAM depth and width */
475 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
]);
476 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
]);
477 jtag_execute_queue();
479 etb
->ram_depth
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
].value
, 0, 32);
480 etb
->ram_width
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
].value
, 0, 32);
485 trace_status_t
etb_status(etm_context_t
*etm_ctx
)
487 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
489 etb
->etm_ctx
= etm_ctx
;
491 /* if tracing is currently idle, return this information */
492 if (etm_ctx
->capture_status
== TRACE_IDLE
)
494 return etm_ctx
->capture_status
;
496 else if (etm_ctx
->capture_status
& TRACE_RUNNING
)
498 reg_t
*etb_status_reg
= &etb
->reg_cache
->reg_list
[ETB_STATUS
];
499 int etb_timeout
= 100;
501 /* trace is running, check the ETB status flags */
502 etb_get_reg(etb_status_reg
);
504 /* check Full bit to identify an overflow */
505 if (buf_get_u32(etb_status_reg
->value
, 0, 1) == 1)
506 etm_ctx
->capture_status
|= TRACE_OVERFLOWED
;
508 /* check Triggered bit to identify trigger condition */
509 if (buf_get_u32(etb_status_reg
->value
, 1, 1) == 1)
510 etm_ctx
->capture_status
|= TRACE_TRIGGERED
;
512 /* check AcqComp to identify trace completion */
513 if (buf_get_u32(etb_status_reg
->value
, 2, 1) == 1)
515 while (etb_timeout
-- && (buf_get_u32(etb_status_reg
->value
, 3, 1) == 0))
517 /* wait for data formatter idle */
518 etb_get_reg(etb_status_reg
);
521 if (etb_timeout
== 0)
523 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
524 buf_get_u32(etb_status_reg
->value
, 0, etb_status_reg
->size
));
527 if (!(etm_ctx
->capture_status
&& TRACE_TRIGGERED
))
529 LOG_ERROR("trace completed, but no trigger condition detected");
532 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
533 etm_ctx
->capture_status
|= TRACE_COMPLETED
;
537 return etm_ctx
->capture_status
;
540 int etb_read_trace(etm_context_t
*etm_ctx
)
542 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
544 int num_frames
= etb
->ram_depth
;
545 u32
*trace_data
= NULL
;
548 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_STATUS
]);
549 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
]);
550 jtag_execute_queue();
552 /* check if we overflowed, and adjust first frame of the trace accordingly
553 * if we didn't overflow, read only up to the frame that would be written next,
554 * i.e. don't read invalid entries
556 if (buf_get_u32(etb
->reg_cache
->reg_list
[ETB_STATUS
].value
, 0, 1))
558 first_frame
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
562 num_frames
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
565 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_READ_POINTER
], first_frame
);
567 /* read data into temporary array for unpacking */
568 trace_data
= malloc(sizeof(u32
) * num_frames
);
569 etb_read_ram(etb
, trace_data
, num_frames
);
571 if (etm_ctx
->trace_depth
> 0)
573 free(etm_ctx
->trace_data
);
576 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
577 etm_ctx
->trace_depth
= num_frames
* 3;
578 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
579 etm_ctx
->trace_depth
= num_frames
* 2;
581 etm_ctx
->trace_depth
= num_frames
;
583 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
585 for (i
= 0, j
= 0; i
< num_frames
; i
++)
587 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
590 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
591 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x78) >> 3;
592 etm_ctx
->trace_data
[j
].flags
= 0;
593 if ((trace_data
[i
] & 0x80) >> 7)
595 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
597 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
599 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
600 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
604 etm_ctx
->trace_data
[j
+1].pipestat
= (trace_data
[i
] & 0x100) >> 8;
605 etm_ctx
->trace_data
[j
+1].packet
= (trace_data
[i
] & 0x7800) >> 11;
606 etm_ctx
->trace_data
[j
+1].flags
= 0;
607 if ((trace_data
[i
] & 0x8000) >> 15)
609 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRACESYNC_CYCLE
;
611 if (etm_ctx
->trace_data
[j
+1].pipestat
== STAT_TR
)
613 etm_ctx
->trace_data
[j
+1].pipestat
= etm_ctx
->trace_data
[j
+1].packet
& 0x7;
614 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRIGGER_CYCLE
;
618 etm_ctx
->trace_data
[j
+2].pipestat
= (trace_data
[i
] & 0x10000) >> 16;
619 etm_ctx
->trace_data
[j
+2].packet
= (trace_data
[i
] & 0x780000) >> 19;
620 etm_ctx
->trace_data
[j
+2].flags
= 0;
621 if ((trace_data
[i
] & 0x800000) >> 23)
623 etm_ctx
->trace_data
[j
+2].flags
|= ETMV1_TRACESYNC_CYCLE
;
625 if (etm_ctx
->trace_data
[j
+2].pipestat
== STAT_TR
)
627 etm_ctx
->trace_data
[j
+2].pipestat
= etm_ctx
->trace_data
[j
+2].packet
& 0x7;
628 etm_ctx
->trace_data
[j
+2].flags
|= ETMV1_TRIGGER_CYCLE
;
633 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
636 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
637 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7f8) >> 3;
638 etm_ctx
->trace_data
[j
].flags
= 0;
639 if ((trace_data
[i
] & 0x800) >> 11)
641 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
643 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
645 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
646 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
650 etm_ctx
->trace_data
[j
+1].pipestat
= (trace_data
[i
] & 0x7000) >> 12;
651 etm_ctx
->trace_data
[j
+1].packet
= (trace_data
[i
] & 0x7f8000) >> 15;
652 etm_ctx
->trace_data
[j
+1].flags
= 0;
653 if ((trace_data
[i
] & 0x800000) >> 23)
655 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRACESYNC_CYCLE
;
657 if (etm_ctx
->trace_data
[j
+1].pipestat
== STAT_TR
)
659 etm_ctx
->trace_data
[j
+1].pipestat
= etm_ctx
->trace_data
[j
+1].packet
& 0x7;
660 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRIGGER_CYCLE
;
668 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
669 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7fff8) >> 3;
670 etm_ctx
->trace_data
[j
].flags
= 0;
671 if ((trace_data
[i
] & 0x80000) >> 19)
673 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
675 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
677 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
678 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
690 int etb_start_capture(etm_context_t
*etm_ctx
)
692 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
693 u32 etb_ctrl_value
= 0x1;
696 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_DEMUXED
)
698 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) != ETM_PORT_8BIT
)
700 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
701 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
703 etb_ctrl_value
|= 0x2;
706 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_MUXED
)
707 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
709 trigger_count
= (etb
->ram_depth
* etm_ctx
->trigger_percent
) / 100;
711 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_TRIGGER_COUNTER
], trigger_count
);
712 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
], 0x0);
713 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_CTRL
], etb_ctrl_value
);
714 jtag_execute_queue();
716 /* we're starting a new trace, initialize capture status */
717 etm_ctx
->capture_status
= TRACE_RUNNING
;
722 int etb_stop_capture(etm_context_t
*etm_ctx
)
724 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
725 reg_t
*etb_ctrl_reg
= &etb
->reg_cache
->reg_list
[ETB_CTRL
];
727 etb_write_reg(etb_ctrl_reg
, 0x0);
728 jtag_execute_queue();
730 /* trace stopped, just clear running flag, but preserve others */
731 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
736 etm_capture_driver_t etb_capture_driver
=
739 .register_commands
= etb_register_commands
,
741 .status
= etb_status
,
742 .start_capture
= etb_start_capture
,
743 .stop_capture
= etb_stop_capture
,
744 .read_trace
= etb_read_trace
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)