1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
32 #include "binarybuffer.h"
39 char* etb_reg_list
[] =
46 "ETB_ram_read_pointer",
47 "ETB_ram_write_pointer",
48 "ETB_trigger_counter",
52 int etb_reg_arch_type
= -1;
54 int etb_get_reg(reg_t
*reg
);
55 int etb_set_reg(reg_t
*reg
, u32 value
);
56 int etb_set_reg_w_exec(reg_t
*reg
, u8
*buf
);
58 int etb_write_reg(reg_t
*reg
, u32 value
);
59 int etb_read_reg(reg_t
*reg
);
61 int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
63 int etb_set_instr(etb_t
*etb
, u32 new_instr
)
70 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
75 field
.num_bits
= tap
->ir_length
;
76 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
77 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
78 field
.out_mask
= NULL
;
79 field
.in_value
= NULL
;
80 field
.in_check_value
= NULL
;
81 field
.in_check_mask
= NULL
;
82 field
.in_handler
= NULL
;
83 field
.in_handler_priv
= NULL
;
85 jtag_add_ir_scan(1, &field
, -1);
87 free(field
.out_value
);
93 int etb_scann(etb_t
*etb
, u32 new_scan_chain
)
95 if(etb
->cur_scan_chain
!= new_scan_chain
)
101 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
102 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_scan_chain
);
103 field
.out_mask
= NULL
;
104 field
.in_value
= NULL
;
105 field
.in_check_value
= NULL
;
106 field
.in_check_mask
= NULL
;
107 field
.in_handler
= NULL
;
108 field
.in_handler_priv
= NULL
;
110 /* select INTEST instruction */
111 etb_set_instr(etb
, 0x2);
112 jtag_add_dr_scan(1, &field
, -1);
114 etb
->cur_scan_chain
= new_scan_chain
;
116 free(field
.out_value
);
122 reg_cache_t
* etb_build_reg_cache(etb_t
*etb
)
124 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
125 reg_t
*reg_list
= NULL
;
126 etb_reg_t
*arch_info
= NULL
;
130 /* register a register arch-type for etm registers only once */
131 if (etb_reg_arch_type
== -1)
132 etb_reg_arch_type
= register_reg_arch_type(etb_get_reg
, etb_set_reg_w_exec
);
134 /* the actual registers are kept in two arrays */
135 reg_list
= calloc(num_regs
, sizeof(reg_t
));
136 arch_info
= calloc(num_regs
, sizeof(etb_reg_t
));
138 /* fill in values for the reg cache */
139 reg_cache
->name
= "etb registers";
140 reg_cache
->next
= NULL
;
141 reg_cache
->reg_list
= reg_list
;
142 reg_cache
->num_regs
= num_regs
;
144 /* set up registers */
145 for (i
= 0; i
< num_regs
; i
++)
147 reg_list
[i
].name
= etb_reg_list
[i
];
148 reg_list
[i
].size
= 32;
149 reg_list
[i
].dirty
= 0;
150 reg_list
[i
].valid
= 0;
151 reg_list
[i
].bitfield_desc
= NULL
;
152 reg_list
[i
].num_bitfields
= 0;
153 reg_list
[i
].value
= calloc(1, 4);
154 reg_list
[i
].arch_info
= &arch_info
[i
];
155 reg_list
[i
].arch_type
= etb_reg_arch_type
;
156 reg_list
[i
].size
= 32;
157 arch_info
[i
].addr
= i
;
158 arch_info
[i
].etb
= etb
;
164 int etb_get_reg(reg_t
*reg
)
167 if ((retval
= etb_read_reg(reg
)) != ERROR_OK
)
169 LOG_ERROR("BUG: error scheduling etm register read");
173 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
175 LOG_ERROR("register read failed");
182 int etb_read_ram(etb_t
*etb
, u32
*data
, int num_frames
)
184 scan_field_t fields
[3];
187 jtag_add_end_state(TAP_RTI
);
189 etb_set_instr(etb
, 0xc);
191 fields
[0].tap
= etb
->tap
;
192 fields
[0].num_bits
= 32;
193 fields
[0].out_value
= NULL
;
194 fields
[0].out_mask
= NULL
;
195 fields
[0].in_value
= NULL
;
196 fields
[0].in_check_value
= NULL
;
197 fields
[0].in_check_mask
= NULL
;
198 fields
[0].in_handler
= NULL
;
199 fields
[0].in_handler_priv
= NULL
;
201 fields
[1].tap
= etb
->tap
;
202 fields
[1].num_bits
= 7;
203 fields
[1].out_value
= malloc(1);
204 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
205 fields
[1].out_mask
= NULL
;
206 fields
[1].in_value
= NULL
;
207 fields
[1].in_check_value
= NULL
;
208 fields
[1].in_check_mask
= NULL
;
209 fields
[1].in_handler
= NULL
;
210 fields
[1].in_handler_priv
= NULL
;
212 fields
[2].tap
= etb
->tap
;
213 fields
[2].num_bits
= 1;
214 fields
[2].out_value
= malloc(1);
215 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
216 fields
[2].out_mask
= NULL
;
217 fields
[2].in_value
= NULL
;
218 fields
[2].in_check_value
= NULL
;
219 fields
[2].in_check_mask
= NULL
;
220 fields
[2].in_handler
= NULL
;
221 fields
[2].in_handler_priv
= NULL
;
223 jtag_add_dr_scan(3, fields
, -1);
225 fields
[0].in_handler
= buf_to_u32_handler
;
227 for (i
= 0; i
< num_frames
; i
++)
229 /* ensure nR/W reamins set to read */
230 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
232 /* address remains set to 0x4 (RAM data) until we read the last frame */
233 if (i
< num_frames
- 1)
234 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
236 buf_set_u32(fields
[1].out_value
, 0, 7, 0);
238 fields
[0].in_handler_priv
= &data
[i
];
239 jtag_add_dr_scan(3, fields
, -1);
242 jtag_execute_queue();
244 free(fields
[1].out_value
);
245 free(fields
[2].out_value
);
250 int etb_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
)
252 etb_reg_t
*etb_reg
= reg
->arch_info
;
253 u8 reg_addr
= etb_reg
->addr
& 0x7f;
254 scan_field_t fields
[3];
256 LOG_DEBUG("%i", etb_reg
->addr
);
258 jtag_add_end_state(TAP_RTI
);
259 etb_scann(etb_reg
->etb
, 0x0);
260 etb_set_instr(etb_reg
->etb
, 0xc);
262 fields
[0].tap
= etb_reg
->etb
->tap
;
263 fields
[0].num_bits
= 32;
264 fields
[0].out_value
= reg
->value
;
265 fields
[0].out_mask
= NULL
;
266 fields
[0].in_value
= NULL
;
267 fields
[0].in_check_value
= NULL
;
268 fields
[0].in_check_mask
= NULL
;
269 fields
[0].in_handler
= NULL
;
270 fields
[0].in_handler_priv
= NULL
;
272 fields
[1].tap
= etb_reg
->etb
->tap
;
273 fields
[1].num_bits
= 7;
274 fields
[1].out_value
= malloc(1);
275 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
276 fields
[1].out_mask
= NULL
;
277 fields
[1].in_value
= NULL
;
278 fields
[1].in_check_value
= NULL
;
279 fields
[1].in_check_mask
= NULL
;
280 fields
[1].in_handler
= NULL
;
281 fields
[1].in_handler_priv
= NULL
;
283 fields
[2].tap
= etb_reg
->etb
->tap
;
284 fields
[2].num_bits
= 1;
285 fields
[2].out_value
= malloc(1);
286 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
287 fields
[2].out_mask
= NULL
;
288 fields
[2].in_value
= NULL
;
289 fields
[2].in_check_value
= NULL
;
290 fields
[2].in_check_mask
= NULL
;
291 fields
[2].in_handler
= NULL
;
292 fields
[2].in_handler_priv
= NULL
;
294 jtag_add_dr_scan(3, fields
, -1);
296 /* read the identification register in the second run, to make sure we
297 * don't read the ETB data register twice, skipping every second entry
299 buf_set_u32(fields
[1].out_value
, 0, 7, 0x0);
300 fields
[0].in_value
= reg
->value
;
302 jtag_set_check_value(fields
+0, check_value
, check_mask
, NULL
);
304 jtag_add_dr_scan(3, fields
, -1);
306 free(fields
[1].out_value
);
307 free(fields
[2].out_value
);
312 int etb_read_reg(reg_t
*reg
)
314 return etb_read_reg_w_check(reg
, NULL
, NULL
);
317 int etb_set_reg(reg_t
*reg
, u32 value
)
320 if ((retval
= etb_write_reg(reg
, value
)) != ERROR_OK
)
322 LOG_ERROR("BUG: error scheduling etm register write");
326 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
333 int etb_set_reg_w_exec(reg_t
*reg
, u8
*buf
)
336 etb_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
338 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
340 LOG_ERROR("register write failed");
346 int etb_write_reg(reg_t
*reg
, u32 value
)
348 etb_reg_t
*etb_reg
= reg
->arch_info
;
349 u8 reg_addr
= etb_reg
->addr
& 0x7f;
350 scan_field_t fields
[3];
352 LOG_DEBUG("%i: 0x%8.8x", etb_reg
->addr
, value
);
354 jtag_add_end_state(TAP_RTI
);
355 etb_scann(etb_reg
->etb
, 0x0);
356 etb_set_instr(etb_reg
->etb
, 0xc);
358 fields
[0].tap
= etb_reg
->etb
->tap
;
359 fields
[0].num_bits
= 32;
360 fields
[0].out_value
= malloc(4);
361 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
362 fields
[0].out_mask
= NULL
;
363 fields
[0].in_value
= NULL
;
364 fields
[0].in_check_value
= NULL
;
365 fields
[0].in_check_mask
= NULL
;
366 fields
[0].in_handler
= NULL
;
367 fields
[0].in_handler_priv
= NULL
;
369 fields
[1].tap
= etb_reg
->etb
->tap
;
370 fields
[1].num_bits
= 7;
371 fields
[1].out_value
= malloc(1);
372 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
373 fields
[1].out_mask
= NULL
;
374 fields
[1].in_value
= NULL
;
375 fields
[1].in_check_value
= NULL
;
376 fields
[1].in_check_mask
= NULL
;
377 fields
[1].in_handler
= NULL
;
378 fields
[1].in_handler_priv
= NULL
;
380 fields
[2].tap
= etb_reg
->etb
->tap
;
381 fields
[2].num_bits
= 1;
382 fields
[2].out_value
= malloc(1);
383 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
384 fields
[2].out_mask
= NULL
;
385 fields
[2].in_value
= NULL
;
386 fields
[2].in_check_value
= NULL
;
387 fields
[2].in_check_mask
= NULL
;
388 fields
[2].in_handler
= NULL
;
389 fields
[2].in_handler_priv
= NULL
;
391 jtag_add_dr_scan(3, fields
, -1);
393 free(fields
[0].out_value
);
394 free(fields
[1].out_value
);
395 free(fields
[2].out_value
);
400 int etb_store_reg(reg_t
*reg
)
402 return etb_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
405 int etb_register_commands(struct command_context_s
*cmd_ctx
)
409 etb_cmd
= register_command(cmd_ctx
, NULL
, "etb", NULL
, COMMAND_ANY
, "Embedded Trace Buffer");
411 register_command(cmd_ctx
, etb_cmd
, "config", handle_etb_config_command
, COMMAND_CONFIG
, NULL
);
416 int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
420 armv4_5_common_t
*armv4_5
;
421 arm7_9_common_t
*arm7_9
;
425 return ERROR_COMMAND_SYNTAX_ERROR
;
428 target
= get_target_by_num(strtoul(args
[0], NULL
, 0));
432 LOG_ERROR("target number '%s' not defined", args
[0]);
436 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
438 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
442 tap
= jtag_TapByString( args
[1] );
444 command_print(cmd_ctx
, "Tap: %s does not exist", args
[1] );
451 etb_t
*etb
= malloc(sizeof(etb_t
));
453 arm7_9
->etm_ctx
->capture_driver_priv
= etb
;
456 etb
->cur_scan_chain
= -1;
457 etb
->reg_cache
= NULL
;
463 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
470 int etb_init(etm_context_t
*etm_ctx
)
472 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
474 etb
->etm_ctx
= etm_ctx
;
476 /* identify ETB RAM depth and width */
477 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
]);
478 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
]);
479 jtag_execute_queue();
481 etb
->ram_depth
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
].value
, 0, 32);
482 etb
->ram_width
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
].value
, 0, 32);
487 trace_status_t
etb_status(etm_context_t
*etm_ctx
)
489 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
491 etb
->etm_ctx
= etm_ctx
;
493 /* if tracing is currently idle, return this information */
494 if (etm_ctx
->capture_status
== TRACE_IDLE
)
496 return etm_ctx
->capture_status
;
498 else if (etm_ctx
->capture_status
& TRACE_RUNNING
)
500 reg_t
*etb_status_reg
= &etb
->reg_cache
->reg_list
[ETB_STATUS
];
501 int etb_timeout
= 100;
503 /* trace is running, check the ETB status flags */
504 etb_get_reg(etb_status_reg
);
506 /* check Full bit to identify an overflow */
507 if (buf_get_u32(etb_status_reg
->value
, 0, 1) == 1)
508 etm_ctx
->capture_status
|= TRACE_OVERFLOWED
;
510 /* check Triggered bit to identify trigger condition */
511 if (buf_get_u32(etb_status_reg
->value
, 1, 1) == 1)
512 etm_ctx
->capture_status
|= TRACE_TRIGGERED
;
514 /* check AcqComp to identify trace completion */
515 if (buf_get_u32(etb_status_reg
->value
, 2, 1) == 1)
517 while (etb_timeout
-- && (buf_get_u32(etb_status_reg
->value
, 3, 1) == 0))
519 /* wait for data formatter idle */
520 etb_get_reg(etb_status_reg
);
523 if (etb_timeout
== 0)
525 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
526 buf_get_u32(etb_status_reg
->value
, 0, etb_status_reg
->size
));
529 if (!(etm_ctx
->capture_status
&& TRACE_TRIGGERED
))
531 LOG_ERROR("trace completed, but no trigger condition detected");
534 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
535 etm_ctx
->capture_status
|= TRACE_COMPLETED
;
539 return etm_ctx
->capture_status
;
542 int etb_read_trace(etm_context_t
*etm_ctx
)
544 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
546 int num_frames
= etb
->ram_depth
;
547 u32
*trace_data
= NULL
;
550 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_STATUS
]);
551 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
]);
552 jtag_execute_queue();
554 /* check if we overflowed, and adjust first frame of the trace accordingly
555 * if we didn't overflow, read only up to the frame that would be written next,
556 * i.e. don't read invalid entries
558 if (buf_get_u32(etb
->reg_cache
->reg_list
[ETB_STATUS
].value
, 0, 1))
560 first_frame
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
564 num_frames
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
567 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_READ_POINTER
], first_frame
);
569 /* read data into temporary array for unpacking */
570 trace_data
= malloc(sizeof(u32
) * num_frames
);
571 etb_read_ram(etb
, trace_data
, num_frames
);
573 if (etm_ctx
->trace_depth
> 0)
575 free(etm_ctx
->trace_data
);
578 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
579 etm_ctx
->trace_depth
= num_frames
* 3;
580 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
581 etm_ctx
->trace_depth
= num_frames
* 2;
583 etm_ctx
->trace_depth
= num_frames
;
585 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
587 for (i
= 0, j
= 0; i
< num_frames
; i
++)
589 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
592 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
593 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x78) >> 3;
594 etm_ctx
->trace_data
[j
].flags
= 0;
595 if ((trace_data
[i
] & 0x80) >> 7)
597 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
599 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
601 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
602 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
606 etm_ctx
->trace_data
[j
+1].pipestat
= (trace_data
[i
] & 0x100) >> 8;
607 etm_ctx
->trace_data
[j
+1].packet
= (trace_data
[i
] & 0x7800) >> 11;
608 etm_ctx
->trace_data
[j
+1].flags
= 0;
609 if ((trace_data
[i
] & 0x8000) >> 15)
611 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRACESYNC_CYCLE
;
613 if (etm_ctx
->trace_data
[j
+1].pipestat
== STAT_TR
)
615 etm_ctx
->trace_data
[j
+1].pipestat
= etm_ctx
->trace_data
[j
+1].packet
& 0x7;
616 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRIGGER_CYCLE
;
620 etm_ctx
->trace_data
[j
+2].pipestat
= (trace_data
[i
] & 0x10000) >> 16;
621 etm_ctx
->trace_data
[j
+2].packet
= (trace_data
[i
] & 0x780000) >> 19;
622 etm_ctx
->trace_data
[j
+2].flags
= 0;
623 if ((trace_data
[i
] & 0x800000) >> 23)
625 etm_ctx
->trace_data
[j
+2].flags
|= ETMV1_TRACESYNC_CYCLE
;
627 if (etm_ctx
->trace_data
[j
+2].pipestat
== STAT_TR
)
629 etm_ctx
->trace_data
[j
+2].pipestat
= etm_ctx
->trace_data
[j
+2].packet
& 0x7;
630 etm_ctx
->trace_data
[j
+2].flags
|= ETMV1_TRIGGER_CYCLE
;
635 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
638 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
639 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7f8) >> 3;
640 etm_ctx
->trace_data
[j
].flags
= 0;
641 if ((trace_data
[i
] & 0x800) >> 11)
643 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
645 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
647 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
648 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
652 etm_ctx
->trace_data
[j
+1].pipestat
= (trace_data
[i
] & 0x7000) >> 12;
653 etm_ctx
->trace_data
[j
+1].packet
= (trace_data
[i
] & 0x7f8000) >> 15;
654 etm_ctx
->trace_data
[j
+1].flags
= 0;
655 if ((trace_data
[i
] & 0x800000) >> 23)
657 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRACESYNC_CYCLE
;
659 if (etm_ctx
->trace_data
[j
+1].pipestat
== STAT_TR
)
661 etm_ctx
->trace_data
[j
+1].pipestat
= etm_ctx
->trace_data
[j
+1].packet
& 0x7;
662 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRIGGER_CYCLE
;
670 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
671 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7fff8) >> 3;
672 etm_ctx
->trace_data
[j
].flags
= 0;
673 if ((trace_data
[i
] & 0x80000) >> 19)
675 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
677 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
679 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
680 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
692 int etb_start_capture(etm_context_t
*etm_ctx
)
694 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
695 u32 etb_ctrl_value
= 0x1;
698 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_DEMUXED
)
700 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) != ETM_PORT_8BIT
)
702 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
703 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
705 etb_ctrl_value
|= 0x2;
708 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_MUXED
)
709 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
711 trigger_count
= (etb
->ram_depth
* etm_ctx
->trigger_percent
) / 100;
713 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_TRIGGER_COUNTER
], trigger_count
);
714 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
], 0x0);
715 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_CTRL
], etb_ctrl_value
);
716 jtag_execute_queue();
718 /* we're starting a new trace, initialize capture status */
719 etm_ctx
->capture_status
= TRACE_RUNNING
;
724 int etb_stop_capture(etm_context_t
*etm_ctx
)
726 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
727 reg_t
*etb_ctrl_reg
= &etb
->reg_cache
->reg_list
[ETB_CTRL
];
729 etb_write_reg(etb_ctrl_reg
, 0x0);
730 jtag_execute_queue();
732 /* trace stopped, just clear running flag, but preserve others */
733 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
738 etm_capture_driver_t etb_capture_driver
=
741 .register_commands
= etb_register_commands
,
743 .status
= etb_status
,
744 .start_capture
= etb_start_capture
,
745 .stop_capture
= etb_stop_capture
,
746 .read_trace
= etb_read_trace
,
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