1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
32 #include "binarybuffer.h"
39 static char* etb_reg_list
[] =
46 "ETB_ram_read_pointer",
47 "ETB_ram_write_pointer",
48 "ETB_trigger_counter",
52 static int etb_reg_arch_type
= -1;
54 static int etb_get_reg(reg_t
*reg
);
56 static int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
58 static int etb_set_instr(etb_t
*etb
, u32 new_instr
)
65 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
70 field
.num_bits
= tap
->ir_length
;
71 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
72 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
73 field
.out_mask
= NULL
;
74 field
.in_value
= NULL
;
75 field
.in_check_value
= NULL
;
76 field
.in_check_mask
= NULL
;
77 field
.in_handler
= NULL
;
78 field
.in_handler_priv
= NULL
;
80 jtag_add_ir_scan(1, &field
, TAP_INVALID
);
82 free(field
.out_value
);
88 static int etb_scann(etb_t
*etb
, u32 new_scan_chain
)
90 if(etb
->cur_scan_chain
!= new_scan_chain
)
96 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
97 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_scan_chain
);
98 field
.out_mask
= NULL
;
99 field
.in_value
= NULL
;
100 field
.in_check_value
= NULL
;
101 field
.in_check_mask
= NULL
;
102 field
.in_handler
= NULL
;
103 field
.in_handler_priv
= NULL
;
105 /* select INTEST instruction */
106 etb_set_instr(etb
, 0x2);
107 jtag_add_dr_scan(1, &field
, TAP_INVALID
);
109 etb
->cur_scan_chain
= new_scan_chain
;
111 free(field
.out_value
);
117 reg_cache_t
* etb_build_reg_cache(etb_t
*etb
)
119 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
120 reg_t
*reg_list
= NULL
;
121 etb_reg_t
*arch_info
= NULL
;
125 /* register a register arch-type for etm registers only once */
126 if (etb_reg_arch_type
== -1)
127 etb_reg_arch_type
= register_reg_arch_type(etb_get_reg
, etb_set_reg_w_exec
);
129 /* the actual registers are kept in two arrays */
130 reg_list
= calloc(num_regs
, sizeof(reg_t
));
131 arch_info
= calloc(num_regs
, sizeof(etb_reg_t
));
133 /* fill in values for the reg cache */
134 reg_cache
->name
= "etb registers";
135 reg_cache
->next
= NULL
;
136 reg_cache
->reg_list
= reg_list
;
137 reg_cache
->num_regs
= num_regs
;
139 /* set up registers */
140 for (i
= 0; i
< num_regs
; i
++)
142 reg_list
[i
].name
= etb_reg_list
[i
];
143 reg_list
[i
].size
= 32;
144 reg_list
[i
].dirty
= 0;
145 reg_list
[i
].valid
= 0;
146 reg_list
[i
].bitfield_desc
= NULL
;
147 reg_list
[i
].num_bitfields
= 0;
148 reg_list
[i
].value
= calloc(1, 4);
149 reg_list
[i
].arch_info
= &arch_info
[i
];
150 reg_list
[i
].arch_type
= etb_reg_arch_type
;
151 reg_list
[i
].size
= 32;
152 arch_info
[i
].addr
= i
;
153 arch_info
[i
].etb
= etb
;
159 static int etb_get_reg(reg_t
*reg
)
162 if ((retval
= etb_read_reg(reg
)) != ERROR_OK
)
164 LOG_ERROR("BUG: error scheduling etm register read");
168 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
170 LOG_ERROR("register read failed");
177 static int etb_read_ram(etb_t
*etb
, u32
*data
, int num_frames
)
179 scan_field_t fields
[3];
182 jtag_add_end_state(TAP_IDLE
);
184 etb_set_instr(etb
, 0xc);
186 fields
[0].tap
= etb
->tap
;
187 fields
[0].num_bits
= 32;
188 fields
[0].out_value
= NULL
;
189 fields
[0].out_mask
= NULL
;
190 fields
[0].in_value
= NULL
;
191 fields
[0].in_check_value
= NULL
;
192 fields
[0].in_check_mask
= NULL
;
193 fields
[0].in_handler
= NULL
;
194 fields
[0].in_handler_priv
= NULL
;
196 fields
[1].tap
= etb
->tap
;
197 fields
[1].num_bits
= 7;
198 fields
[1].out_value
= malloc(1);
199 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
200 fields
[1].out_mask
= NULL
;
201 fields
[1].in_value
= NULL
;
202 fields
[1].in_check_value
= NULL
;
203 fields
[1].in_check_mask
= NULL
;
204 fields
[1].in_handler
= NULL
;
205 fields
[1].in_handler_priv
= NULL
;
207 fields
[2].tap
= etb
->tap
;
208 fields
[2].num_bits
= 1;
209 fields
[2].out_value
= malloc(1);
210 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
211 fields
[2].out_mask
= NULL
;
212 fields
[2].in_value
= NULL
;
213 fields
[2].in_check_value
= NULL
;
214 fields
[2].in_check_mask
= NULL
;
215 fields
[2].in_handler
= NULL
;
216 fields
[2].in_handler_priv
= NULL
;
218 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
220 fields
[0].in_handler
= buf_to_u32_handler
;
222 for (i
= 0; i
< num_frames
; i
++)
224 /* ensure nR/W reamins set to read */
225 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
227 /* address remains set to 0x4 (RAM data) until we read the last frame */
228 if (i
< num_frames
- 1)
229 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
231 buf_set_u32(fields
[1].out_value
, 0, 7, 0);
233 fields
[0].in_handler_priv
= &data
[i
];
234 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
237 jtag_execute_queue();
239 free(fields
[1].out_value
);
240 free(fields
[2].out_value
);
245 int etb_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
)
247 etb_reg_t
*etb_reg
= reg
->arch_info
;
248 u8 reg_addr
= etb_reg
->addr
& 0x7f;
249 scan_field_t fields
[3];
251 LOG_DEBUG("%i", etb_reg
->addr
);
253 jtag_add_end_state(TAP_IDLE
);
254 etb_scann(etb_reg
->etb
, 0x0);
255 etb_set_instr(etb_reg
->etb
, 0xc);
257 fields
[0].tap
= etb_reg
->etb
->tap
;
258 fields
[0].num_bits
= 32;
259 fields
[0].out_value
= reg
->value
;
260 fields
[0].out_mask
= NULL
;
261 fields
[0].in_value
= NULL
;
262 fields
[0].in_check_value
= NULL
;
263 fields
[0].in_check_mask
= NULL
;
264 fields
[0].in_handler
= NULL
;
265 fields
[0].in_handler_priv
= NULL
;
267 fields
[1].tap
= etb_reg
->etb
->tap
;
268 fields
[1].num_bits
= 7;
269 fields
[1].out_value
= malloc(1);
270 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
271 fields
[1].out_mask
= NULL
;
272 fields
[1].in_value
= NULL
;
273 fields
[1].in_check_value
= NULL
;
274 fields
[1].in_check_mask
= NULL
;
275 fields
[1].in_handler
= NULL
;
276 fields
[1].in_handler_priv
= NULL
;
278 fields
[2].tap
= etb_reg
->etb
->tap
;
279 fields
[2].num_bits
= 1;
280 fields
[2].out_value
= malloc(1);
281 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
282 fields
[2].out_mask
= NULL
;
283 fields
[2].in_value
= NULL
;
284 fields
[2].in_check_value
= NULL
;
285 fields
[2].in_check_mask
= NULL
;
286 fields
[2].in_handler
= NULL
;
287 fields
[2].in_handler_priv
= NULL
;
289 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
291 /* read the identification register in the second run, to make sure we
292 * don't read the ETB data register twice, skipping every second entry
294 buf_set_u32(fields
[1].out_value
, 0, 7, 0x0);
295 fields
[0].in_value
= reg
->value
;
297 jtag_set_check_value(fields
+0, check_value
, check_mask
, NULL
);
299 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
301 free(fields
[1].out_value
);
302 free(fields
[2].out_value
);
307 int etb_read_reg(reg_t
*reg
)
309 return etb_read_reg_w_check(reg
, NULL
, NULL
);
312 int etb_set_reg(reg_t
*reg
, u32 value
)
315 if ((retval
= etb_write_reg(reg
, value
)) != ERROR_OK
)
317 LOG_ERROR("BUG: error scheduling etm register write");
321 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
328 int etb_set_reg_w_exec(reg_t
*reg
, u8
*buf
)
331 etb_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
333 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
335 LOG_ERROR("register write failed");
341 int etb_write_reg(reg_t
*reg
, u32 value
)
343 etb_reg_t
*etb_reg
= reg
->arch_info
;
344 u8 reg_addr
= etb_reg
->addr
& 0x7f;
345 scan_field_t fields
[3];
347 LOG_DEBUG("%i: 0x%8.8x", etb_reg
->addr
, value
);
349 jtag_add_end_state(TAP_IDLE
);
350 etb_scann(etb_reg
->etb
, 0x0);
351 etb_set_instr(etb_reg
->etb
, 0xc);
353 fields
[0].tap
= etb_reg
->etb
->tap
;
354 fields
[0].num_bits
= 32;
355 fields
[0].out_value
= malloc(4);
356 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
357 fields
[0].out_mask
= NULL
;
358 fields
[0].in_value
= NULL
;
359 fields
[0].in_check_value
= NULL
;
360 fields
[0].in_check_mask
= NULL
;
361 fields
[0].in_handler
= NULL
;
362 fields
[0].in_handler_priv
= NULL
;
364 fields
[1].tap
= etb_reg
->etb
->tap
;
365 fields
[1].num_bits
= 7;
366 fields
[1].out_value
= malloc(1);
367 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
368 fields
[1].out_mask
= NULL
;
369 fields
[1].in_value
= NULL
;
370 fields
[1].in_check_value
= NULL
;
371 fields
[1].in_check_mask
= NULL
;
372 fields
[1].in_handler
= NULL
;
373 fields
[1].in_handler_priv
= NULL
;
375 fields
[2].tap
= etb_reg
->etb
->tap
;
376 fields
[2].num_bits
= 1;
377 fields
[2].out_value
= malloc(1);
378 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
379 fields
[2].out_mask
= NULL
;
380 fields
[2].in_value
= NULL
;
381 fields
[2].in_check_value
= NULL
;
382 fields
[2].in_check_mask
= NULL
;
383 fields
[2].in_handler
= NULL
;
384 fields
[2].in_handler_priv
= NULL
;
386 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
388 free(fields
[0].out_value
);
389 free(fields
[1].out_value
);
390 free(fields
[2].out_value
);
395 int etb_store_reg(reg_t
*reg
)
397 return etb_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
400 static int etb_register_commands(struct command_context_s
*cmd_ctx
)
404 etb_cmd
= register_command(cmd_ctx
, NULL
, "etb", NULL
, COMMAND_ANY
, "Embedded Trace Buffer");
406 register_command(cmd_ctx
, etb_cmd
, "config", handle_etb_config_command
, COMMAND_CONFIG
, NULL
);
411 static int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
415 armv4_5_common_t
*armv4_5
;
416 arm7_9_common_t
*arm7_9
;
420 return ERROR_COMMAND_SYNTAX_ERROR
;
423 target
= get_target_by_num(strtoul(args
[0], NULL
, 0));
427 LOG_ERROR("target number '%s' not defined", args
[0]);
431 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
433 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
437 tap
= jtag_TapByString( args
[1] );
439 command_print(cmd_ctx
, "Tap: %s does not exist", args
[1] );
446 etb_t
*etb
= malloc(sizeof(etb_t
));
448 arm7_9
->etm_ctx
->capture_driver_priv
= etb
;
451 etb
->cur_scan_chain
= ~0UL;
452 etb
->reg_cache
= NULL
;
458 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
465 static int etb_init(etm_context_t
*etm_ctx
)
467 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
469 etb
->etm_ctx
= etm_ctx
;
471 /* identify ETB RAM depth and width */
472 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
]);
473 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
]);
474 jtag_execute_queue();
476 etb
->ram_depth
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
].value
, 0, 32);
477 etb
->ram_width
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
].value
, 0, 32);
482 static trace_status_t
etb_status(etm_context_t
*etm_ctx
)
484 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
486 etb
->etm_ctx
= etm_ctx
;
488 /* if tracing is currently idle, return this information */
489 if (etm_ctx
->capture_status
== TRACE_IDLE
)
491 return etm_ctx
->capture_status
;
493 else if (etm_ctx
->capture_status
& TRACE_RUNNING
)
495 reg_t
*etb_status_reg
= &etb
->reg_cache
->reg_list
[ETB_STATUS
];
496 int etb_timeout
= 100;
498 /* trace is running, check the ETB status flags */
499 etb_get_reg(etb_status_reg
);
501 /* check Full bit to identify an overflow */
502 if (buf_get_u32(etb_status_reg
->value
, 0, 1) == 1)
503 etm_ctx
->capture_status
|= TRACE_OVERFLOWED
;
505 /* check Triggered bit to identify trigger condition */
506 if (buf_get_u32(etb_status_reg
->value
, 1, 1) == 1)
507 etm_ctx
->capture_status
|= TRACE_TRIGGERED
;
509 /* check AcqComp to identify trace completion */
510 if (buf_get_u32(etb_status_reg
->value
, 2, 1) == 1)
512 while (etb_timeout
-- && (buf_get_u32(etb_status_reg
->value
, 3, 1) == 0))
514 /* wait for data formatter idle */
515 etb_get_reg(etb_status_reg
);
518 if (etb_timeout
== 0)
520 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
521 buf_get_u32(etb_status_reg
->value
, 0, etb_status_reg
->size
));
524 if (!(etm_ctx
->capture_status
&& TRACE_TRIGGERED
))
526 LOG_ERROR("trace completed, but no trigger condition detected");
529 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
530 etm_ctx
->capture_status
|= TRACE_COMPLETED
;
534 return etm_ctx
->capture_status
;
537 static int etb_read_trace(etm_context_t
*etm_ctx
)
539 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
541 int num_frames
= etb
->ram_depth
;
542 u32
*trace_data
= NULL
;
545 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_STATUS
]);
546 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
]);
547 jtag_execute_queue();
549 /* check if we overflowed, and adjust first frame of the trace accordingly
550 * if we didn't overflow, read only up to the frame that would be written next,
551 * i.e. don't read invalid entries
553 if (buf_get_u32(etb
->reg_cache
->reg_list
[ETB_STATUS
].value
, 0, 1))
555 first_frame
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
559 num_frames
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
562 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_READ_POINTER
], first_frame
);
564 /* read data into temporary array for unpacking */
565 trace_data
= malloc(sizeof(u32
) * num_frames
);
566 etb_read_ram(etb
, trace_data
, num_frames
);
568 if (etm_ctx
->trace_depth
> 0)
570 free(etm_ctx
->trace_data
);
573 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
574 etm_ctx
->trace_depth
= num_frames
* 3;
575 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
576 etm_ctx
->trace_depth
= num_frames
* 2;
578 etm_ctx
->trace_depth
= num_frames
;
580 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
582 for (i
= 0, j
= 0; i
< num_frames
; i
++)
584 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
587 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
588 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x78) >> 3;
589 etm_ctx
->trace_data
[j
].flags
= 0;
590 if ((trace_data
[i
] & 0x80) >> 7)
592 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
594 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
596 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
597 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
601 etm_ctx
->trace_data
[j
+1].pipestat
= (trace_data
[i
] & 0x100) >> 8;
602 etm_ctx
->trace_data
[j
+1].packet
= (trace_data
[i
] & 0x7800) >> 11;
603 etm_ctx
->trace_data
[j
+1].flags
= 0;
604 if ((trace_data
[i
] & 0x8000) >> 15)
606 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRACESYNC_CYCLE
;
608 if (etm_ctx
->trace_data
[j
+1].pipestat
== STAT_TR
)
610 etm_ctx
->trace_data
[j
+1].pipestat
= etm_ctx
->trace_data
[j
+1].packet
& 0x7;
611 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRIGGER_CYCLE
;
615 etm_ctx
->trace_data
[j
+2].pipestat
= (trace_data
[i
] & 0x10000) >> 16;
616 etm_ctx
->trace_data
[j
+2].packet
= (trace_data
[i
] & 0x780000) >> 19;
617 etm_ctx
->trace_data
[j
+2].flags
= 0;
618 if ((trace_data
[i
] & 0x800000) >> 23)
620 etm_ctx
->trace_data
[j
+2].flags
|= ETMV1_TRACESYNC_CYCLE
;
622 if (etm_ctx
->trace_data
[j
+2].pipestat
== STAT_TR
)
624 etm_ctx
->trace_data
[j
+2].pipestat
= etm_ctx
->trace_data
[j
+2].packet
& 0x7;
625 etm_ctx
->trace_data
[j
+2].flags
|= ETMV1_TRIGGER_CYCLE
;
630 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
633 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
634 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7f8) >> 3;
635 etm_ctx
->trace_data
[j
].flags
= 0;
636 if ((trace_data
[i
] & 0x800) >> 11)
638 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
640 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
642 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
643 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
647 etm_ctx
->trace_data
[j
+1].pipestat
= (trace_data
[i
] & 0x7000) >> 12;
648 etm_ctx
->trace_data
[j
+1].packet
= (trace_data
[i
] & 0x7f8000) >> 15;
649 etm_ctx
->trace_data
[j
+1].flags
= 0;
650 if ((trace_data
[i
] & 0x800000) >> 23)
652 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRACESYNC_CYCLE
;
654 if (etm_ctx
->trace_data
[j
+1].pipestat
== STAT_TR
)
656 etm_ctx
->trace_data
[j
+1].pipestat
= etm_ctx
->trace_data
[j
+1].packet
& 0x7;
657 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRIGGER_CYCLE
;
665 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
666 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7fff8) >> 3;
667 etm_ctx
->trace_data
[j
].flags
= 0;
668 if ((trace_data
[i
] & 0x80000) >> 19)
670 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
672 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
674 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
675 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
687 static int etb_start_capture(etm_context_t
*etm_ctx
)
689 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
690 u32 etb_ctrl_value
= 0x1;
693 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_DEMUXED
)
695 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) != ETM_PORT_8BIT
)
697 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
698 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
700 etb_ctrl_value
|= 0x2;
703 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_MUXED
)
704 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
706 trigger_count
= (etb
->ram_depth
* etm_ctx
->trigger_percent
) / 100;
708 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_TRIGGER_COUNTER
], trigger_count
);
709 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
], 0x0);
710 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_CTRL
], etb_ctrl_value
);
711 jtag_execute_queue();
713 /* we're starting a new trace, initialize capture status */
714 etm_ctx
->capture_status
= TRACE_RUNNING
;
719 static int etb_stop_capture(etm_context_t
*etm_ctx
)
721 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
722 reg_t
*etb_ctrl_reg
= &etb
->reg_cache
->reg_list
[ETB_CTRL
];
724 etb_write_reg(etb_ctrl_reg
, 0x0);
725 jtag_execute_queue();
727 /* trace stopped, just clear running flag, but preserve others */
728 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
733 etm_capture_driver_t etb_capture_driver
=
736 .register_commands
= etb_register_commands
,
738 .status
= etb_status
,
739 .start_capture
= etb_start_capture
,
740 .stop_capture
= etb_stop_capture
,
741 .read_trace
= etb_read_trace
,
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