1 /***************************************************************************
2 * Copyright (C) 2007 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
26 #include "arm7_9_common.h"
32 #include "binarybuffer.h"
39 static char* etb_reg_list
[] =
46 "ETB_ram_read_pointer",
47 "ETB_ram_write_pointer",
48 "ETB_trigger_counter",
52 static int etb_reg_arch_type
= -1;
54 static int etb_get_reg(reg_t
*reg
);
56 static int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
);
58 static int etb_set_instr(etb_t
*etb
, u32 new_instr
)
65 if (buf_get_u32(tap
->cur_instr
, 0, tap
->ir_length
) != new_instr
)
70 field
.num_bits
= tap
->ir_length
;
71 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
72 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_instr
);
74 field
.in_value
= NULL
;
80 jtag_add_ir_scan(1, &field
, TAP_INVALID
);
82 free(field
.out_value
);
88 static int etb_scann(etb_t
*etb
, u32 new_scan_chain
)
90 if(etb
->cur_scan_chain
!= new_scan_chain
)
96 field
.out_value
= calloc(CEIL(field
.num_bits
, 8), 1);
97 buf_set_u32(field
.out_value
, 0, field
.num_bits
, new_scan_chain
);
99 field
.in_value
= NULL
;
105 /* select INTEST instruction */
106 etb_set_instr(etb
, 0x2);
107 jtag_add_dr_scan(1, &field
, TAP_INVALID
);
109 etb
->cur_scan_chain
= new_scan_chain
;
111 free(field
.out_value
);
117 reg_cache_t
* etb_build_reg_cache(etb_t
*etb
)
119 reg_cache_t
*reg_cache
= malloc(sizeof(reg_cache_t
));
120 reg_t
*reg_list
= NULL
;
121 etb_reg_t
*arch_info
= NULL
;
125 /* register a register arch-type for etm registers only once */
126 if (etb_reg_arch_type
== -1)
127 etb_reg_arch_type
= register_reg_arch_type(etb_get_reg
, etb_set_reg_w_exec
);
129 /* the actual registers are kept in two arrays */
130 reg_list
= calloc(num_regs
, sizeof(reg_t
));
131 arch_info
= calloc(num_regs
, sizeof(etb_reg_t
));
133 /* fill in values for the reg cache */
134 reg_cache
->name
= "etb registers";
135 reg_cache
->next
= NULL
;
136 reg_cache
->reg_list
= reg_list
;
137 reg_cache
->num_regs
= num_regs
;
139 /* set up registers */
140 for (i
= 0; i
< num_regs
; i
++)
142 reg_list
[i
].name
= etb_reg_list
[i
];
143 reg_list
[i
].size
= 32;
144 reg_list
[i
].dirty
= 0;
145 reg_list
[i
].valid
= 0;
146 reg_list
[i
].bitfield_desc
= NULL
;
147 reg_list
[i
].num_bitfields
= 0;
148 reg_list
[i
].value
= calloc(1, 4);
149 reg_list
[i
].arch_info
= &arch_info
[i
];
150 reg_list
[i
].arch_type
= etb_reg_arch_type
;
151 reg_list
[i
].size
= 32;
152 arch_info
[i
].addr
= i
;
153 arch_info
[i
].etb
= etb
;
159 static int etb_get_reg(reg_t
*reg
)
162 if ((retval
= etb_read_reg(reg
)) != ERROR_OK
)
164 LOG_ERROR("BUG: error scheduling etm register read");
168 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
170 LOG_ERROR("register read failed");
177 static int etb_read_ram(etb_t
*etb
, u32
*data
, int num_frames
)
179 scan_field_t fields
[3];
182 jtag_add_end_state(TAP_IDLE
);
184 etb_set_instr(etb
, 0xc);
186 fields
[0].tap
= etb
->tap
;
187 fields
[0].num_bits
= 32;
188 fields
[0].out_value
= NULL
;
190 fields
[0].in_value
= tmp
;
193 fields
[1].tap
= etb
->tap
;
194 fields
[1].num_bits
= 7;
195 fields
[1].out_value
= malloc(1);
196 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
197 fields
[1].in_value
= NULL
;
200 fields
[2].tap
= etb
->tap
;
201 fields
[2].num_bits
= 1;
202 fields
[2].out_value
= malloc(1);
203 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
204 fields
[2].in_value
= NULL
;
207 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
210 for (i
= 0; i
< num_frames
; i
++)
212 /* ensure nR/W reamins set to read */
213 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
215 /* address remains set to 0x4 (RAM data) until we read the last frame */
216 if (i
< num_frames
- 1)
217 buf_set_u32(fields
[1].out_value
, 0, 7, 4);
219 buf_set_u32(fields
[1].out_value
, 0, 7, 0);
221 jtag_add_dr_scan_now(3, fields
, TAP_INVALID
);
223 data
[i
]=buf_get_u32(tmp
, 0, 32);
226 jtag_execute_queue();
228 free(fields
[1].out_value
);
229 free(fields
[2].out_value
);
234 int etb_read_reg_w_check(reg_t
*reg
, u8
* check_value
, u8
* check_mask
)
236 etb_reg_t
*etb_reg
= reg
->arch_info
;
237 u8 reg_addr
= etb_reg
->addr
& 0x7f;
238 scan_field_t fields
[3];
240 LOG_DEBUG("%i", etb_reg
->addr
);
242 jtag_add_end_state(TAP_IDLE
);
243 etb_scann(etb_reg
->etb
, 0x0);
244 etb_set_instr(etb_reg
->etb
, 0xc);
246 fields
[0].tap
= etb_reg
->etb
->tap
;
247 fields
[0].num_bits
= 32;
248 fields
[0].out_value
= reg
->value
;
250 fields
[0].in_value
= NULL
;
256 fields
[1].tap
= etb_reg
->etb
->tap
;
257 fields
[1].num_bits
= 7;
258 fields
[1].out_value
= malloc(1);
259 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
261 fields
[1].in_value
= NULL
;
267 fields
[2].tap
= etb_reg
->etb
->tap
;
268 fields
[2].num_bits
= 1;
269 fields
[2].out_value
= malloc(1);
270 buf_set_u32(fields
[2].out_value
, 0, 1, 0);
272 fields
[2].in_value
= NULL
;
278 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
280 /* read the identification register in the second run, to make sure we
281 * don't read the ETB data register twice, skipping every second entry
283 buf_set_u32(fields
[1].out_value
, 0, 7, 0x0);
284 fields
[0].in_value
= reg
->value
;
286 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
288 jtag_check_value_mask(fields
+0, check_value
, check_mask
);
290 free(fields
[1].out_value
);
291 free(fields
[2].out_value
);
296 int etb_read_reg(reg_t
*reg
)
298 return etb_read_reg_w_check(reg
, NULL
, NULL
);
301 int etb_set_reg(reg_t
*reg
, u32 value
)
304 if ((retval
= etb_write_reg(reg
, value
)) != ERROR_OK
)
306 LOG_ERROR("BUG: error scheduling etm register write");
310 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
317 int etb_set_reg_w_exec(reg_t
*reg
, u8
*buf
)
320 etb_set_reg(reg
, buf_get_u32(buf
, 0, reg
->size
));
322 if ((retval
= jtag_execute_queue()) != ERROR_OK
)
324 LOG_ERROR("register write failed");
330 int etb_write_reg(reg_t
*reg
, u32 value
)
332 etb_reg_t
*etb_reg
= reg
->arch_info
;
333 u8 reg_addr
= etb_reg
->addr
& 0x7f;
334 scan_field_t fields
[3];
336 LOG_DEBUG("%i: 0x%8.8x", etb_reg
->addr
, value
);
338 jtag_add_end_state(TAP_IDLE
);
339 etb_scann(etb_reg
->etb
, 0x0);
340 etb_set_instr(etb_reg
->etb
, 0xc);
342 fields
[0].tap
= etb_reg
->etb
->tap
;
343 fields
[0].num_bits
= 32;
344 fields
[0].out_value
= malloc(4);
345 buf_set_u32(fields
[0].out_value
, 0, 32, value
);
347 fields
[0].in_value
= NULL
;
353 fields
[1].tap
= etb_reg
->etb
->tap
;
354 fields
[1].num_bits
= 7;
355 fields
[1].out_value
= malloc(1);
356 buf_set_u32(fields
[1].out_value
, 0, 7, reg_addr
);
358 fields
[1].in_value
= NULL
;
364 fields
[2].tap
= etb_reg
->etb
->tap
;
365 fields
[2].num_bits
= 1;
366 fields
[2].out_value
= malloc(1);
367 buf_set_u32(fields
[2].out_value
, 0, 1, 1);
369 fields
[2].in_value
= NULL
;
375 jtag_add_dr_scan(3, fields
, TAP_INVALID
);
377 free(fields
[0].out_value
);
378 free(fields
[1].out_value
);
379 free(fields
[2].out_value
);
384 int etb_store_reg(reg_t
*reg
)
386 return etb_write_reg(reg
, buf_get_u32(reg
->value
, 0, reg
->size
));
389 static int etb_register_commands(struct command_context_s
*cmd_ctx
)
393 etb_cmd
= register_command(cmd_ctx
, NULL
, "etb", NULL
, COMMAND_ANY
, "Embedded Trace Buffer");
395 register_command(cmd_ctx
, etb_cmd
, "config", handle_etb_config_command
, COMMAND_CONFIG
, NULL
);
400 static int handle_etb_config_command(struct command_context_s
*cmd_ctx
, char *cmd
, char **args
, int argc
)
404 armv4_5_common_t
*armv4_5
;
405 arm7_9_common_t
*arm7_9
;
409 return ERROR_COMMAND_SYNTAX_ERROR
;
412 target
= get_target_by_num(strtoul(args
[0], NULL
, 0));
416 LOG_ERROR("target number '%s' not defined", args
[0]);
420 if (arm7_9_get_arch_pointers(target
, &armv4_5
, &arm7_9
) != ERROR_OK
)
422 command_print(cmd_ctx
, "current target isn't an ARM7/ARM9 target");
426 tap
= jtag_TapByString( args
[1] );
428 command_print(cmd_ctx
, "Tap: %s does not exist", args
[1] );
435 etb_t
*etb
= malloc(sizeof(etb_t
));
437 arm7_9
->etm_ctx
->capture_driver_priv
= etb
;
440 etb
->cur_scan_chain
= 0xffffffff;
441 etb
->reg_cache
= NULL
;
447 LOG_ERROR("target has no ETM defined, ETB left unconfigured");
454 static int etb_init(etm_context_t
*etm_ctx
)
456 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
458 etb
->etm_ctx
= etm_ctx
;
460 /* identify ETB RAM depth and width */
461 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
]);
462 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
]);
463 jtag_execute_queue();
465 etb
->ram_depth
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_DEPTH
].value
, 0, 32);
466 etb
->ram_width
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WIDTH
].value
, 0, 32);
471 static trace_status_t
etb_status(etm_context_t
*etm_ctx
)
473 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
475 etb
->etm_ctx
= etm_ctx
;
477 /* if tracing is currently idle, return this information */
478 if (etm_ctx
->capture_status
== TRACE_IDLE
)
480 return etm_ctx
->capture_status
;
482 else if (etm_ctx
->capture_status
& TRACE_RUNNING
)
484 reg_t
*etb_status_reg
= &etb
->reg_cache
->reg_list
[ETB_STATUS
];
485 int etb_timeout
= 100;
487 /* trace is running, check the ETB status flags */
488 etb_get_reg(etb_status_reg
);
490 /* check Full bit to identify an overflow */
491 if (buf_get_u32(etb_status_reg
->value
, 0, 1) == 1)
492 etm_ctx
->capture_status
|= TRACE_OVERFLOWED
;
494 /* check Triggered bit to identify trigger condition */
495 if (buf_get_u32(etb_status_reg
->value
, 1, 1) == 1)
496 etm_ctx
->capture_status
|= TRACE_TRIGGERED
;
498 /* check AcqComp to identify trace completion */
499 if (buf_get_u32(etb_status_reg
->value
, 2, 1) == 1)
501 while (etb_timeout
-- && (buf_get_u32(etb_status_reg
->value
, 3, 1) == 0))
503 /* wait for data formatter idle */
504 etb_get_reg(etb_status_reg
);
507 if (etb_timeout
== 0)
509 LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
510 buf_get_u32(etb_status_reg
->value
, 0, etb_status_reg
->size
));
513 if (!(etm_ctx
->capture_status
&& TRACE_TRIGGERED
))
515 LOG_ERROR("trace completed, but no trigger condition detected");
518 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
519 etm_ctx
->capture_status
|= TRACE_COMPLETED
;
523 return etm_ctx
->capture_status
;
526 static int etb_read_trace(etm_context_t
*etm_ctx
)
528 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
530 int num_frames
= etb
->ram_depth
;
531 u32
*trace_data
= NULL
;
534 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_STATUS
]);
535 etb_read_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
]);
536 jtag_execute_queue();
538 /* check if we overflowed, and adjust first frame of the trace accordingly
539 * if we didn't overflow, read only up to the frame that would be written next,
540 * i.e. don't read invalid entries
542 if (buf_get_u32(etb
->reg_cache
->reg_list
[ETB_STATUS
].value
, 0, 1))
544 first_frame
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
548 num_frames
= buf_get_u32(etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
].value
, 0, 32);
551 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_READ_POINTER
], first_frame
);
553 /* read data into temporary array for unpacking */
554 trace_data
= malloc(sizeof(u32
) * num_frames
);
555 etb_read_ram(etb
, trace_data
, num_frames
);
557 if (etm_ctx
->trace_depth
> 0)
559 free(etm_ctx
->trace_data
);
562 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
563 etm_ctx
->trace_depth
= num_frames
* 3;
564 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
565 etm_ctx
->trace_depth
= num_frames
* 2;
567 etm_ctx
->trace_depth
= num_frames
;
569 etm_ctx
->trace_data
= malloc(sizeof(etmv1_trace_data_t
) * etm_ctx
->trace_depth
);
571 for (i
= 0, j
= 0; i
< num_frames
; i
++)
573 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_4BIT
)
576 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
577 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x78) >> 3;
578 etm_ctx
->trace_data
[j
].flags
= 0;
579 if ((trace_data
[i
] & 0x80) >> 7)
581 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
583 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
585 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
586 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
590 etm_ctx
->trace_data
[j
+1].pipestat
= (trace_data
[i
] & 0x100) >> 8;
591 etm_ctx
->trace_data
[j
+1].packet
= (trace_data
[i
] & 0x7800) >> 11;
592 etm_ctx
->trace_data
[j
+1].flags
= 0;
593 if ((trace_data
[i
] & 0x8000) >> 15)
595 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRACESYNC_CYCLE
;
597 if (etm_ctx
->trace_data
[j
+1].pipestat
== STAT_TR
)
599 etm_ctx
->trace_data
[j
+1].pipestat
= etm_ctx
->trace_data
[j
+1].packet
& 0x7;
600 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRIGGER_CYCLE
;
604 etm_ctx
->trace_data
[j
+2].pipestat
= (trace_data
[i
] & 0x10000) >> 16;
605 etm_ctx
->trace_data
[j
+2].packet
= (trace_data
[i
] & 0x780000) >> 19;
606 etm_ctx
->trace_data
[j
+2].flags
= 0;
607 if ((trace_data
[i
] & 0x800000) >> 23)
609 etm_ctx
->trace_data
[j
+2].flags
|= ETMV1_TRACESYNC_CYCLE
;
611 if (etm_ctx
->trace_data
[j
+2].pipestat
== STAT_TR
)
613 etm_ctx
->trace_data
[j
+2].pipestat
= etm_ctx
->trace_data
[j
+2].packet
& 0x7;
614 etm_ctx
->trace_data
[j
+2].flags
|= ETMV1_TRIGGER_CYCLE
;
619 else if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) == ETM_PORT_8BIT
)
622 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
623 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7f8) >> 3;
624 etm_ctx
->trace_data
[j
].flags
= 0;
625 if ((trace_data
[i
] & 0x800) >> 11)
627 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
629 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
631 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
632 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
636 etm_ctx
->trace_data
[j
+1].pipestat
= (trace_data
[i
] & 0x7000) >> 12;
637 etm_ctx
->trace_data
[j
+1].packet
= (trace_data
[i
] & 0x7f8000) >> 15;
638 etm_ctx
->trace_data
[j
+1].flags
= 0;
639 if ((trace_data
[i
] & 0x800000) >> 23)
641 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRACESYNC_CYCLE
;
643 if (etm_ctx
->trace_data
[j
+1].pipestat
== STAT_TR
)
645 etm_ctx
->trace_data
[j
+1].pipestat
= etm_ctx
->trace_data
[j
+1].packet
& 0x7;
646 etm_ctx
->trace_data
[j
+1].flags
|= ETMV1_TRIGGER_CYCLE
;
654 etm_ctx
->trace_data
[j
].pipestat
= trace_data
[i
] & 0x7;
655 etm_ctx
->trace_data
[j
].packet
= (trace_data
[i
] & 0x7fff8) >> 3;
656 etm_ctx
->trace_data
[j
].flags
= 0;
657 if ((trace_data
[i
] & 0x80000) >> 19)
659 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRACESYNC_CYCLE
;
661 if (etm_ctx
->trace_data
[j
].pipestat
== STAT_TR
)
663 etm_ctx
->trace_data
[j
].pipestat
= etm_ctx
->trace_data
[j
].packet
& 0x7;
664 etm_ctx
->trace_data
[j
].flags
|= ETMV1_TRIGGER_CYCLE
;
676 static int etb_start_capture(etm_context_t
*etm_ctx
)
678 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
679 u32 etb_ctrl_value
= 0x1;
682 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_DEMUXED
)
684 if ((etm_ctx
->portmode
& ETM_PORT_WIDTH_MASK
) != ETM_PORT_8BIT
)
686 LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
687 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
689 etb_ctrl_value
|= 0x2;
692 if ((etm_ctx
->portmode
& ETM_PORT_MODE_MASK
) == ETM_PORT_MUXED
)
693 return ERROR_ETM_PORTMODE_NOT_SUPPORTED
;
695 trigger_count
= (etb
->ram_depth
* etm_ctx
->trigger_percent
) / 100;
697 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_TRIGGER_COUNTER
], trigger_count
);
698 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_RAM_WRITE_POINTER
], 0x0);
699 etb_write_reg(&etb
->reg_cache
->reg_list
[ETB_CTRL
], etb_ctrl_value
);
700 jtag_execute_queue();
702 /* we're starting a new trace, initialize capture status */
703 etm_ctx
->capture_status
= TRACE_RUNNING
;
708 static int etb_stop_capture(etm_context_t
*etm_ctx
)
710 etb_t
*etb
= etm_ctx
->capture_driver_priv
;
711 reg_t
*etb_ctrl_reg
= &etb
->reg_cache
->reg_list
[ETB_CTRL
];
713 etb_write_reg(etb_ctrl_reg
, 0x0);
714 jtag_execute_queue();
716 /* trace stopped, just clear running flag, but preserve others */
717 etm_ctx
->capture_status
&= ~TRACE_RUNNING
;
722 etm_capture_driver_t etb_capture_driver
=
725 .register_commands
= etb_register_commands
,
727 .status
= etb_status
,
728 .start_capture
= etb_start_capture
,
729 .stop_capture
= etb_stop_capture
,
730 .read_trace
= etb_read_trace
,
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