1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * ESP Xtensa SMP target API for OpenOCD *
5 * Copyright (C) 2020 Espressif Systems Ltd. Co *
6 ***************************************************************************/
13 #include <target/target.h>
14 #include <target/target_type.h>
15 #include <target/smp.h>
16 #include <target/semihosting_common.h>
17 #include "esp_xtensa_smp.h"
18 #include "esp_xtensa_semihosting.h"
21 Multiprocessor stuff common:
23 The ESP Xtensa chip can have several cores in it, which can run in SMP-mode if an
24 SMP-capable OS is running. The hardware has a few features which makes
25 SMP debugging much easier.
27 First of all, there's something called a 'break network', consisting of a
28 BreakIn input and a BreakOut output on each CPU. The idea is that as soon
29 as a CPU goes into debug mode for whatever reason, it'll signal that using
30 its DebugOut pin. This signal is connected to the other CPU's DebugIn
31 input, causing this CPU also to go into debugging mode. To resume execution
32 when using only this break network, we will need to manually resume both
35 An alternative to this is the XOCDMode output and the RunStall (or DebugStall)
36 input. When these are cross-connected, a CPU that goes into debug mode will
37 halt execution entirely on the other CPU. Execution on the other CPU can be
38 resumed by either the first CPU going out of debug mode, or the second CPU
39 going into debug mode: the stall is temporarily lifted as long as the stalled
42 A third, separate, signal is CrossTrigger. This is connected in the same way
43 as the breakIn/breakOut network, but is for the TRAX (trace memory) feature;
44 it does not affect OCD in any way.
50 The ESP Xtensa chip has several Xtensa cores inside, but represent themself to the OCD
51 as one chip that works in multithreading mode under FreeRTOS OS.
52 The core that initiate the stop condition will be defined as an active cpu.
53 When one core stops, then other core will be stopped automatically by smpbreak.
54 The core that initiates stop condition will be defined as an active core, and
55 registers of this core will be transferred.
58 #define ESP_XTENSA_SMP_EXAMINE_OTHER_CORES 5
60 static int esp_xtensa_smp_update_halt_gdb(struct target
*target
, bool *need_resume
);
62 static inline struct esp_xtensa_smp_common
*target_to_esp_xtensa_smp(struct target
*target
)
64 return container_of(target
->arch_info
, struct esp_xtensa_smp_common
, esp_xtensa
);
67 int esp_xtensa_smp_assert_reset(struct target
*target
)
72 int esp_xtensa_smp_deassert_reset(struct target
*target
)
74 LOG_TARGET_DEBUG(target
, "begin");
76 int ret
= xtensa_deassert_reset(target
);
79 /* in SMP mode when chip was running single-core app the other core can be left un-examined,
80 because examination is done before SOC reset. But after SOC reset it is functional and should be handled.
81 So try to examine un-examined core just after SOC reset */
82 if (target
->smp
&& !target_was_examined(target
))
83 ret
= xtensa_examine(target
);
87 int esp_xtensa_smp_soft_reset_halt(struct target
*target
)
90 struct target_list
*head
;
91 struct esp_xtensa_smp_common
*esp_xtensa_smp
= target_to_esp_xtensa_smp(target
);
93 LOG_TARGET_DEBUG(target
, "begin");
94 /* in SMP mode we need to ensure that at first we reset SOC on PRO-CPU
95 and then call xtensa_assert_reset() for all cores */
96 if (target
->smp
&& target
->coreid
!= 0)
98 /* Reset the SoC first */
99 if (esp_xtensa_smp
->chip_ops
->reset
) {
100 res
= esp_xtensa_smp
->chip_ops
->reset(target
);
105 return xtensa_assert_reset(target
);
107 foreach_smp_target(head
, target
->smp_targets
) {
108 res
= xtensa_assert_reset(head
->target
);
115 static struct target
*get_halted_esp_xtensa_smp(struct target
*target
, int32_t coreid
)
117 struct target_list
*head
;
120 foreach_smp_target(head
, target
->smp_targets
) {
122 if ((curr
->coreid
== coreid
) && (curr
->state
== TARGET_HALTED
))
129 int esp_xtensa_smp_poll(struct target
*target
)
131 enum target_state old_state
= target
->state
;
132 struct esp_xtensa_smp_common
*esp_xtensa_smp
= target_to_esp_xtensa_smp(target
);
133 struct esp_xtensa_common
*esp_xtensa
= target_to_esp_xtensa(target
);
134 struct target_list
*head
;
136 bool other_core_resume_req
= false;
138 if (target
->state
== TARGET_HALTED
&& target
->smp
&& target
->gdb_service
&& !target
->gdb_service
->target
) {
139 target
->gdb_service
->target
= get_halted_esp_xtensa_smp(target
, target
->gdb_service
->core
[1]);
140 LOG_INFO("Switch GDB target to '%s'", target_name(target
->gdb_service
->target
));
141 if (esp_xtensa_smp
->chip_ops
->on_halt
)
142 esp_xtensa_smp
->chip_ops
->on_halt(target
);
143 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
147 int ret
= esp_xtensa_poll(target
);
152 if (target
->state
== TARGET_RESET
) {
153 esp_xtensa_smp
->examine_other_cores
= ESP_XTENSA_SMP_EXAMINE_OTHER_CORES
;
154 } else if (esp_xtensa_smp
->examine_other_cores
> 0 &&
155 (target
->state
== TARGET_RUNNING
|| target
->state
== TARGET_HALTED
)) {
156 LOG_TARGET_DEBUG(target
, "Check for unexamined cores after reset");
157 bool all_examined
= true;
158 foreach_smp_target(head
, target
->smp_targets
) {
162 if (!target_was_examined(curr
)) {
163 if (target_examine_one(curr
) != ERROR_OK
) {
164 LOG_DEBUG("Failed to examine!");
165 all_examined
= false;
170 esp_xtensa_smp
->examine_other_cores
= 0;
172 esp_xtensa_smp
->examine_other_cores
--;
176 if (old_state
!= TARGET_HALTED
&& target
->state
== TARGET_HALTED
) {
178 ret
= esp_xtensa_smp_update_halt_gdb(target
, &other_core_resume_req
);
182 /* Call any event callbacks that are applicable */
183 if (old_state
== TARGET_DEBUG_RUNNING
) {
184 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
186 if (esp_xtensa_semihosting(target
, &ret
) == SEMIHOSTING_HANDLED
) {
187 if (ret
== ERROR_OK
&& esp_xtensa
->semihost
.need_resume
&&
188 !esp_xtensa_smp
->other_core_does_resume
) {
189 esp_xtensa
->semihost
.need_resume
= false;
190 /* Resume xtensa_resume will handle BREAK instruction. */
191 ret
= target_resume(target
, 1, 0, 1, 0);
192 if (ret
!= ERROR_OK
) {
193 LOG_ERROR("Failed to resume target");
199 /* check whether any core polled by esp_xtensa_smp_update_halt_gdb() requested resume */
200 if (target
->smp
&& other_core_resume_req
) {
201 /* Resume xtensa_resume will handle BREAK instruction. */
202 ret
= target_resume(target
, 1, 0, 1, 0);
203 if (ret
!= ERROR_OK
) {
204 LOG_ERROR("Failed to resume target");
209 if (esp_xtensa_smp
->chip_ops
->on_halt
)
210 esp_xtensa_smp
->chip_ops
->on_halt(target
);
211 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
218 static int esp_xtensa_smp_update_halt_gdb(struct target
*target
, bool *need_resume
)
220 struct esp_xtensa_smp_common
*esp_xtensa_smp
;
221 struct target
*gdb_target
= NULL
;
222 struct target_list
*head
;
226 *need_resume
= false;
228 if (target
->gdb_service
&& target
->gdb_service
->target
)
229 LOG_DEBUG("GDB target '%s'", target_name(target
->gdb_service
->target
));
231 if (target
->gdb_service
&& target
->gdb_service
->core
[0] == -1) {
232 target
->gdb_service
->target
= target
;
233 target
->gdb_service
->core
[0] = target
->coreid
;
234 LOG_INFO("Set GDB target to '%s'", target_name(target
));
237 if (target
->gdb_service
)
238 gdb_target
= target
->gdb_service
->target
;
240 /* due to smpbreak config other cores can also go to HALTED state */
241 foreach_smp_target(head
, target
->smp_targets
) {
243 LOG_DEBUG("Check target '%s'", target_name(curr
));
244 /* skip calling context */
247 if (!target_was_examined(curr
)) {
248 curr
->state
= TARGET_HALTED
;
251 /* skip targets that were already halted */
252 if (curr
->state
== TARGET_HALTED
)
254 /* Skip gdb_target; it alerts GDB so has to be polled as last one */
255 if (curr
== gdb_target
)
257 LOG_DEBUG("Poll target '%s'", target_name(curr
));
259 esp_xtensa_smp
= target_to_esp_xtensa_smp(curr
);
260 /* avoid auto-resume after syscall, it will be done later */
261 esp_xtensa_smp
->other_core_does_resume
= true;
262 /* avoid recursion in esp_xtensa_smp_poll() */
264 if (esp_xtensa_smp
->chip_ops
->poll
)
265 ret
= esp_xtensa_smp
->chip_ops
->poll(curr
);
267 ret
= esp_xtensa_smp_poll(curr
);
271 esp_xtensa_smp
->other_core_does_resume
= false;
272 struct esp_xtensa_common
*curr_esp_xtensa
= target_to_esp_xtensa(curr
);
273 if (curr_esp_xtensa
->semihost
.need_resume
) {
274 curr_esp_xtensa
->semihost
.need_resume
= false;
279 /* after all targets were updated, poll the gdb serving target */
280 if (gdb_target
&& gdb_target
!= target
) {
281 esp_xtensa_smp
= target_to_esp_xtensa_smp(gdb_target
);
282 if (esp_xtensa_smp
->chip_ops
->poll
)
283 ret
= esp_xtensa_smp
->chip_ops
->poll(gdb_target
);
285 ret
= esp_xtensa_smp_poll(gdb_target
);
293 static inline int esp_xtensa_smp_smpbreak_disable(struct target
*target
, uint32_t *smp_break
)
295 int res
= xtensa_smpbreak_get(target
, smp_break
);
298 return xtensa_smpbreak_set(target
, 0);
301 static inline int esp_xtensa_smp_smpbreak_restore(struct target
*target
, uint32_t smp_break
)
303 return xtensa_smpbreak_set(target
, smp_break
);
306 static int esp_xtensa_smp_resume_cores(struct target
*target
,
307 int handle_breakpoints
,
310 struct target_list
*head
;
313 LOG_TARGET_DEBUG(target
, "begin");
315 foreach_smp_target(head
, target
->smp_targets
) {
317 /* in single-core mode disabled core cannot be examined, but need to be resumed too*/
318 if ((curr
!= target
) && (curr
->state
!= TARGET_RUNNING
) && target_was_examined(curr
)) {
319 /* resume current address, not in SMP mode */
321 int res
= esp_xtensa_smp_resume(curr
, 1, 0, handle_breakpoints
, debug_execution
);
330 int esp_xtensa_smp_resume(struct target
*target
,
332 target_addr_t address
,
333 int handle_breakpoints
,
339 xtensa_smpbreak_get(target
, &smp_break
);
340 LOG_TARGET_DEBUG(target
, "smp_break=0x%" PRIx32
, smp_break
);
342 /* dummy resume for smp toggle in order to reduce gdb impact */
343 if ((target
->smp
) && (target
->gdb_service
) && (target
->gdb_service
->core
[1] != -1)) {
344 /* simulate a start and halt of target */
345 target
->gdb_service
->target
= NULL
;
346 target
->gdb_service
->core
[0] = target
->gdb_service
->core
[1];
347 /* fake resume at next poll we play the target core[1], see poll*/
348 LOG_TARGET_DEBUG(target
, "Fake resume");
349 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
353 /* xtensa_prepare_resume() can step over breakpoint/watchpoint and generate signals on BreakInOut circuit for
354 * other cores. So disconnect this core from BreakInOut circuit and do xtensa_prepare_resume(). */
355 res
= esp_xtensa_smp_smpbreak_disable(target
, &smp_break
);
358 res
= xtensa_prepare_resume(target
, current
, address
, handle_breakpoints
, debug_execution
);
359 /* restore configured BreakInOut signals config */
360 int ret
= esp_xtensa_smp_smpbreak_restore(target
, smp_break
);
363 if (res
!= ERROR_OK
) {
364 LOG_TARGET_ERROR(target
, "Failed to prepare for resume!");
369 if (target
->gdb_service
)
370 target
->gdb_service
->core
[0] = -1;
371 res
= esp_xtensa_smp_resume_cores(target
, handle_breakpoints
, debug_execution
);
376 res
= xtensa_do_resume(target
);
377 if (res
!= ERROR_OK
) {
378 LOG_TARGET_ERROR(target
, "Failed to resume!");
382 target
->debug_reason
= DBG_REASON_NOTHALTED
;
383 if (!debug_execution
)
384 target
->state
= TARGET_RUNNING
;
386 target
->state
= TARGET_DEBUG_RUNNING
;
388 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
392 int esp_xtensa_smp_step(struct target
*target
,
394 target_addr_t address
,
395 int handle_breakpoints
)
398 uint32_t smp_break
= 0;
399 struct esp_xtensa_smp_common
*esp_xtensa_smp
= target_to_esp_xtensa_smp(target
);
402 res
= esp_xtensa_smp_smpbreak_disable(target
, &smp_break
);
406 res
= xtensa_step(target
, current
, address
, handle_breakpoints
);
408 if (res
== ERROR_OK
) {
409 if (esp_xtensa_smp
->chip_ops
->on_halt
)
410 esp_xtensa_smp
->chip_ops
->on_halt(target
);
411 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
415 int ret
= esp_xtensa_smp_smpbreak_restore(target
, smp_break
);
423 int esp_xtensa_smp_watchpoint_add(struct target
*target
, struct watchpoint
*watchpoint
)
425 int res
= xtensa_watchpoint_add(target
, watchpoint
);
432 struct target_list
*head
;
433 foreach_smp_target(head
, target
->smp_targets
) {
434 struct target
*curr
= head
->target
;
435 if (curr
== target
|| !target_was_examined(curr
))
437 /* Need to use high level API here because every target for core contains list of watchpoints.
438 * GDB works with active core only, so we need to duplicate every watchpoint on other cores,
439 * otherwise watchpoint_free() on active core can fail if WP has been initially added on another core. */
441 res
= watchpoint_add(curr
, watchpoint
->address
, watchpoint
->length
,
442 watchpoint
->rw
, watchpoint
->value
, watchpoint
->mask
);
450 int esp_xtensa_smp_watchpoint_remove(struct target
*target
, struct watchpoint
*watchpoint
)
452 int res
= xtensa_watchpoint_remove(target
, watchpoint
);
459 struct target_list
*head
;
460 foreach_smp_target(head
, target
->smp_targets
) {
461 struct target
*curr
= head
->target
;
464 /* see big comment in esp_xtensa_smp_watchpoint_add() */
466 watchpoint_remove(curr
, watchpoint
->address
);
472 int esp_xtensa_smp_init_arch_info(struct target
*target
,
473 struct esp_xtensa_smp_common
*esp_xtensa_smp
,
474 struct xtensa_debug_module_config
*dm_cfg
,
475 const struct esp_xtensa_smp_chip_ops
*chip_ops
,
476 const struct esp_semihost_ops
*semihost_ops
)
478 int ret
= esp_xtensa_init_arch_info(target
, &esp_xtensa_smp
->esp_xtensa
, dm_cfg
, semihost_ops
);
481 esp_xtensa_smp
->chip_ops
= chip_ops
;
482 esp_xtensa_smp
->examine_other_cores
= ESP_XTENSA_SMP_EXAMINE_OTHER_CORES
;
486 int esp_xtensa_smp_target_init(struct command_context
*cmd_ctx
, struct target
*target
)
488 int ret
= esp_xtensa_target_init(cmd_ctx
, target
);
493 struct target_list
*head
;
494 foreach_smp_target(head
, target
->smp_targets
) {
495 struct target
*curr
= head
->target
;
496 ret
= esp_xtensa_semihosting_init(curr
);
501 ret
= esp_xtensa_semihosting_init(target
);
508 COMMAND_HANDLER(esp_xtensa_smp_cmd_xtdef
)
510 struct target
*target
= get_current_target(CMD_CTX
);
511 if (target
->smp
&& CMD_ARGC
> 0) {
512 struct target_list
*head
;
514 foreach_smp_target(head
, target
->smp_targets
) {
516 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do
,
517 target_to_xtensa(curr
));
523 return CALL_COMMAND_HANDLER(xtensa_cmd_xtdef_do
,
524 target_to_xtensa(target
));
527 COMMAND_HANDLER(esp_xtensa_smp_cmd_xtopt
)
529 struct target
*target
= get_current_target(CMD_CTX
);
530 if (target
->smp
&& CMD_ARGC
> 0) {
531 struct target_list
*head
;
533 foreach_smp_target(head
, target
->smp_targets
) {
535 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do
,
536 target_to_xtensa(curr
));
542 return CALL_COMMAND_HANDLER(xtensa_cmd_xtopt_do
,
543 target_to_xtensa(target
));
546 COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmem
)
548 struct target
*target
= get_current_target(CMD_CTX
);
549 if (target
->smp
&& CMD_ARGC
> 0) {
550 struct target_list
*head
;
552 foreach_smp_target(head
, target
->smp_targets
) {
554 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do
,
555 target_to_xtensa(curr
));
561 return CALL_COMMAND_HANDLER(xtensa_cmd_xtmem_do
,
562 target_to_xtensa(target
));
565 COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmpu
)
567 struct target
*target
= get_current_target(CMD_CTX
);
568 if (target
->smp
&& CMD_ARGC
> 0) {
569 struct target_list
*head
;
571 foreach_smp_target(head
, target
->smp_targets
) {
573 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do
,
574 target_to_xtensa(curr
));
580 return CALL_COMMAND_HANDLER(xtensa_cmd_xtmpu_do
,
581 target_to_xtensa(target
));
584 COMMAND_HANDLER(esp_xtensa_smp_cmd_xtmmu
)
586 struct target
*target
= get_current_target(CMD_CTX
);
587 if (target
->smp
&& CMD_ARGC
> 0) {
588 struct target_list
*head
;
590 foreach_smp_target(head
, target
->smp_targets
) {
592 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do
,
593 target_to_xtensa(curr
));
599 return CALL_COMMAND_HANDLER(xtensa_cmd_xtmmu_do
,
600 target_to_xtensa(target
));
603 COMMAND_HANDLER(esp_xtensa_smp_cmd_xtreg
)
605 struct target
*target
= get_current_target(CMD_CTX
);
606 if (target
->smp
&& CMD_ARGC
> 0) {
607 struct target_list
*head
;
609 foreach_smp_target(head
, target
->smp_targets
) {
611 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do
,
612 target_to_xtensa(curr
));
618 return CALL_COMMAND_HANDLER(xtensa_cmd_xtreg_do
,
619 target_to_xtensa(target
));
622 COMMAND_HANDLER(esp_xtensa_smp_cmd_xtregfmt
)
624 struct target
*target
= get_current_target(CMD_CTX
);
625 if (target
->smp
&& CMD_ARGC
> 0) {
626 struct target_list
*head
;
628 foreach_smp_target(head
, target
->smp_targets
) {
630 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do
,
631 target_to_xtensa(curr
));
637 return CALL_COMMAND_HANDLER(xtensa_cmd_xtregfmt_do
,
638 target_to_xtensa(target
));
641 COMMAND_HANDLER(esp_xtensa_smp_cmd_permissive_mode
)
643 struct target
*target
= get_current_target(CMD_CTX
);
644 if (target
->smp
&& CMD_ARGC
> 0) {
645 struct target_list
*head
;
647 foreach_smp_target(head
, target
->smp_targets
) {
649 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_permissive_mode_do
,
650 target_to_xtensa(curr
));
656 return CALL_COMMAND_HANDLER(xtensa_cmd_permissive_mode_do
,
657 target_to_xtensa(target
));
660 COMMAND_HANDLER(esp_xtensa_smp_cmd_smpbreak
)
662 struct target
*target
= get_current_target(CMD_CTX
);
663 if (target
->smp
&& CMD_ARGC
> 0) {
664 struct target_list
*head
;
666 foreach_smp_target(head
, target
->smp_targets
) {
668 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_smpbreak_do
, curr
);
674 return CALL_COMMAND_HANDLER(xtensa_cmd_smpbreak_do
, target
);
677 COMMAND_HANDLER(esp_xtensa_smp_cmd_mask_interrupts
)
679 struct target
*target
= get_current_target(CMD_CTX
);
680 if (target
->smp
&& CMD_ARGC
> 0) {
681 struct target_list
*head
;
683 foreach_smp_target(head
, target
->smp_targets
) {
685 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_mask_interrupts_do
,
686 target_to_xtensa(curr
));
692 return CALL_COMMAND_HANDLER(xtensa_cmd_mask_interrupts_do
,
693 target_to_xtensa(target
));
696 COMMAND_HANDLER(esp_xtensa_smp_cmd_perfmon_enable
)
698 struct target
*target
= get_current_target(CMD_CTX
);
699 if (target
->smp
&& CMD_ARGC
> 0) {
700 struct target_list
*head
;
702 foreach_smp_target(head
, target
->smp_targets
) {
704 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_enable_do
,
705 target_to_xtensa(curr
));
711 return CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_enable_do
,
712 target_to_xtensa(target
));
715 COMMAND_HANDLER(esp_xtensa_smp_cmd_perfmon_dump
)
717 struct target
*target
= get_current_target(CMD_CTX
);
719 struct target_list
*head
;
721 foreach_smp_target(head
, target
->smp_targets
) {
723 LOG_INFO("CPU%d:", curr
->coreid
);
724 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_dump_do
,
725 target_to_xtensa(curr
));
731 return CALL_COMMAND_HANDLER(xtensa_cmd_perfmon_dump_do
,
732 target_to_xtensa(target
));
735 COMMAND_HANDLER(esp_xtensa_smp_cmd_tracestart
)
737 struct target
*target
= get_current_target(CMD_CTX
);
739 struct target_list
*head
;
741 foreach_smp_target(head
, target
->smp_targets
) {
743 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_tracestart_do
,
744 target_to_xtensa(curr
));
750 return CALL_COMMAND_HANDLER(xtensa_cmd_tracestart_do
,
751 target_to_xtensa(target
));
754 COMMAND_HANDLER(esp_xtensa_smp_cmd_tracestop
)
756 struct target
*target
= get_current_target(CMD_CTX
);
758 struct target_list
*head
;
760 foreach_smp_target(head
, target
->smp_targets
) {
762 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_tracestop_do
,
763 target_to_xtensa(curr
));
769 return CALL_COMMAND_HANDLER(xtensa_cmd_tracestop_do
,
770 target_to_xtensa(target
));
773 COMMAND_HANDLER(esp_xtensa_smp_cmd_tracedump
)
775 struct target
*target
= get_current_target(CMD_CTX
);
777 struct target_list
*head
;
779 int32_t cores_max_id
= 0;
780 /* assume that core IDs are assigned to SMP targets sequentially: 0,1,2... */
781 foreach_smp_target(head
, target
->smp_targets
) {
783 if (cores_max_id
< curr
->coreid
)
784 cores_max_id
= curr
->coreid
;
786 if (CMD_ARGC
< ((uint32_t)cores_max_id
+ 1)) {
788 "Need %d filenames to dump to as output!",
792 foreach_smp_target(head
, target
->smp_targets
) {
794 int ret
= CALL_COMMAND_HANDLER(xtensa_cmd_tracedump_do
,
795 target_to_xtensa(curr
), CMD_ARGV
[curr
->coreid
]);
801 return CALL_COMMAND_HANDLER(xtensa_cmd_tracedump_do
,
802 target_to_xtensa(target
), CMD_ARGV
[0]);
805 const struct command_registration esp_xtensa_smp_xtensa_command_handlers
[] = {
808 .handler
= esp_xtensa_smp_cmd_xtdef
,
809 .mode
= COMMAND_CONFIG
,
810 .help
= "Configure Xtensa core type",
815 .handler
= esp_xtensa_smp_cmd_xtopt
,
816 .mode
= COMMAND_CONFIG
,
817 .help
= "Configure Xtensa core option",
818 .usage
= "<name> <value>",
822 .handler
= esp_xtensa_smp_cmd_xtmem
,
823 .mode
= COMMAND_CONFIG
,
824 .help
= "Configure Xtensa memory/cache option",
825 .usage
= "<type> [parameters]",
829 .handler
= esp_xtensa_smp_cmd_xtmmu
,
830 .mode
= COMMAND_CONFIG
,
831 .help
= "Configure Xtensa MMU option",
832 .usage
= "<NIREFILLENTRIES> <NDREFILLENTRIES> <IVARWAY56> <DVARWAY56>",
836 .handler
= esp_xtensa_smp_cmd_xtmpu
,
837 .mode
= COMMAND_CONFIG
,
838 .help
= "Configure Xtensa MPU option",
839 .usage
= "<num FG seg> <min seg size> <lockable> <executeonly>",
843 .handler
= esp_xtensa_smp_cmd_xtreg
,
844 .mode
= COMMAND_CONFIG
,
845 .help
= "Configure Xtensa register",
846 .usage
= "<regname> <regnum>",
850 .handler
= esp_xtensa_smp_cmd_xtreg
,
851 .mode
= COMMAND_CONFIG
,
852 .help
= "Configure number of Xtensa registers",
853 .usage
= "<numregs>",
857 .handler
= esp_xtensa_smp_cmd_xtregfmt
,
858 .mode
= COMMAND_CONFIG
,
859 .help
= "Configure format of Xtensa register map",
860 .usage
= "<numgregs>",
863 .name
= "set_permissive",
864 .handler
= esp_xtensa_smp_cmd_permissive_mode
,
866 .help
= "When set to 1, enable Xtensa permissive mode (less client-side checks)",
871 .handler
= esp_xtensa_smp_cmd_mask_interrupts
,
873 .help
= "mask Xtensa interrupts at step",
874 .usage
= "['on'|'off']",
878 .handler
= esp_xtensa_smp_cmd_smpbreak
,
880 .help
= "Set the way the CPU chains OCD breaks",
882 "[none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]",
885 .name
= "perfmon_enable",
886 .handler
= esp_xtensa_smp_cmd_perfmon_enable
,
887 .mode
= COMMAND_EXEC
,
888 .help
= "Enable and start performance counter",
889 .usage
= "<counter_id> <select> [mask] [kernelcnt] [tracelevel]",
892 .name
= "perfmon_dump",
893 .handler
= esp_xtensa_smp_cmd_perfmon_dump
,
894 .mode
= COMMAND_EXEC
,
896 "Dump performance counter value. If no argument specified, dumps all counters.",
897 .usage
= "[counter_id]",
900 .name
= "tracestart",
901 .handler
= esp_xtensa_smp_cmd_tracestart
,
902 .mode
= COMMAND_EXEC
,
904 "Tracing: Set up and start a trace. Optionally set stop trigger address and amount of data captured after.",
905 .usage
= "[pc <pcval>/[maskbitcount]] [after <n> [ins|words]]",
909 .handler
= esp_xtensa_smp_cmd_tracestop
,
910 .mode
= COMMAND_EXEC
,
911 .help
= "Tracing: Stop current trace as started by the tracestart command",
916 .handler
= esp_xtensa_smp_cmd_tracedump
,
917 .mode
= COMMAND_EXEC
,
918 .help
= "Tracing: Dump trace memory to a files. One file per core.",
919 .usage
= "<outfile1> <outfile2>",
921 COMMAND_REGISTRATION_DONE
924 const struct command_registration esp_xtensa_smp_command_handlers
[] = {
928 .chain
= esp_xtensa_smp_xtensa_command_handlers
,
930 COMMAND_REGISTRATION_DONE
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