1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2018 by Square, Inc. *
5 * Steven Stallion <stallion@squareup.com> *
6 * James Zhao <hjz@squareup.com> *
7 ***************************************************************************/
13 #include <helper/binarybuffer.h>
14 #include <helper/command.h>
15 #include <helper/log.h>
16 #include <helper/time_support.h>
17 #include <helper/types.h>
18 #include <jtag/interface.h>
19 #include <target/breakpoints.h>
20 #include <target/register.h>
21 #include <target/target.h>
22 #include <target/target_type.h>
26 #define RESET_TIMEOUT 5000 /* 5s */
27 #define STEP_TIMEOUT 1000 /* 1s */
30 * eSi-RISC targets support a configurable number of interrupts;
31 * up to 32 interrupts are supported.
33 static const char * const esirisc_exception_strings
[] = {
34 [EID_RESET
] = "Reset",
35 [EID_HARDWARE_FAILURE
] = "HardwareFailure",
37 [EID_INST_BREAKPOINT
] = "InstBreakpoint",
38 [EID_DATA_BREAKPOINT
] = "DataBreakpoint",
39 [EID_UNSUPPORTED
] = "Unsupported",
40 [EID_PRIVILEGE_VIOLATION
] = "PrivilegeViolation",
41 [EID_INST_BUS_ERROR
] = "InstBusError",
42 [EID_DATA_BUS_ERROR
] = "DataBusError",
43 [EID_ALIGNMENT_ERROR
] = "AlignmentError",
44 [EID_ARITHMETIC_ERROR
] = "ArithmeticError",
45 [EID_SYSTEM_CALL
] = "SystemCall",
46 [EID_MEMORY_MANAGEMENT
] = "MemoryManagement",
47 [EID_UNRECOVERABLE
] = "Unrecoverable",
48 [EID_INTERRUPT_N
+0] = "Interrupt0",
49 [EID_INTERRUPT_N
+1] = "Interrupt1",
50 [EID_INTERRUPT_N
+2] = "Interrupt2",
51 [EID_INTERRUPT_N
+3] = "Interrupt3",
52 [EID_INTERRUPT_N
+4] = "Interrupt4",
53 [EID_INTERRUPT_N
+5] = "Interrupt5",
54 [EID_INTERRUPT_N
+6] = "Interrupt6",
55 [EID_INTERRUPT_N
+7] = "Interrupt7",
56 [EID_INTERRUPT_N
+8] = "Interrupt8",
57 [EID_INTERRUPT_N
+9] = "Interrupt9",
58 [EID_INTERRUPT_N
+10] = "Interrupt10",
59 [EID_INTERRUPT_N
+11] = "Interrupt11",
60 [EID_INTERRUPT_N
+12] = "Interrupt12",
61 [EID_INTERRUPT_N
+13] = "Interrupt13",
62 [EID_INTERRUPT_N
+14] = "Interrupt14",
63 [EID_INTERRUPT_N
+15] = "Interrupt15",
64 [EID_INTERRUPT_N
+16] = "Interrupt16",
65 [EID_INTERRUPT_N
+17] = "Interrupt17",
66 [EID_INTERRUPT_N
+18] = "Interrupt18",
67 [EID_INTERRUPT_N
+19] = "Interrupt19",
68 [EID_INTERRUPT_N
+20] = "Interrupt20",
69 [EID_INTERRUPT_N
+21] = "Interrupt21",
70 [EID_INTERRUPT_N
+22] = "Interrupt22",
71 [EID_INTERRUPT_N
+23] = "Interrupt23",
72 [EID_INTERRUPT_N
+24] = "Interrupt24",
73 [EID_INTERRUPT_N
+25] = "Interrupt25",
74 [EID_INTERRUPT_N
+26] = "Interrupt26",
75 [EID_INTERRUPT_N
+27] = "Interrupt27",
76 [EID_INTERRUPT_N
+28] = "Interrupt28",
77 [EID_INTERRUPT_N
+29] = "Interrupt29",
78 [EID_INTERRUPT_N
+30] = "Interrupt30",
79 [EID_INTERRUPT_N
+31] = "Interrupt31",
83 * eSi-RISC targets support a configurable number of general purpose
84 * registers; 8, 16, and 32 registers are supported.
87 enum esirisc_reg_num number
;
92 { ESIRISC_SP
, "sp", REG_TYPE_DATA_PTR
, "general" },
93 { ESIRISC_RA
, "ra", REG_TYPE_INT
, "general" },
94 { ESIRISC_R2
, "r2", REG_TYPE_INT
, "general" },
95 { ESIRISC_R3
, "r3", REG_TYPE_INT
, "general" },
96 { ESIRISC_R4
, "r4", REG_TYPE_INT
, "general" },
97 { ESIRISC_R5
, "r5", REG_TYPE_INT
, "general" },
98 { ESIRISC_R6
, "r6", REG_TYPE_INT
, "general" },
99 { ESIRISC_R7
, "r7", REG_TYPE_INT
, "general" },
100 { ESIRISC_R8
, "r8", REG_TYPE_INT
, "general" },
101 { ESIRISC_R9
, "r9", REG_TYPE_INT
, "general" },
102 { ESIRISC_R10
, "r10", REG_TYPE_INT
, "general" },
103 { ESIRISC_R11
, "r11", REG_TYPE_INT
, "general" },
104 { ESIRISC_R12
, "r12", REG_TYPE_INT
, "general" },
105 { ESIRISC_R13
, "r13", REG_TYPE_INT
, "general" },
106 { ESIRISC_R14
, "r14", REG_TYPE_INT
, "general" },
107 { ESIRISC_R15
, "r15", REG_TYPE_INT
, "general" },
108 { ESIRISC_R16
, "r16", REG_TYPE_INT
, "general" },
109 { ESIRISC_R17
, "r17", REG_TYPE_INT
, "general" },
110 { ESIRISC_R18
, "r18", REG_TYPE_INT
, "general" },
111 { ESIRISC_R19
, "r19", REG_TYPE_INT
, "general" },
112 { ESIRISC_R20
, "r20", REG_TYPE_INT
, "general" },
113 { ESIRISC_R21
, "r21", REG_TYPE_INT
, "general" },
114 { ESIRISC_R22
, "r22", REG_TYPE_INT
, "general" },
115 { ESIRISC_R23
, "r23", REG_TYPE_INT
, "general" },
116 { ESIRISC_R24
, "r24", REG_TYPE_INT
, "general" },
117 { ESIRISC_R25
, "r25", REG_TYPE_INT
, "general" },
118 { ESIRISC_R26
, "r26", REG_TYPE_INT
, "general" },
119 { ESIRISC_R27
, "r27", REG_TYPE_INT
, "general" },
120 { ESIRISC_R28
, "r28", REG_TYPE_INT
, "general" },
121 { ESIRISC_R29
, "r29", REG_TYPE_INT
, "general" },
122 { ESIRISC_R30
, "r30", REG_TYPE_INT
, "general" },
123 { ESIRISC_R31
, "r31", REG_TYPE_INT
, "general" },
127 * Control and Status Registers (CSRs) are largely defined as belonging
128 * to the system register group. The exception to this rule are the PC
129 * and CAS registers, which belong to the general group. While debug is
130 * active, EPC, ECAS, and ETC must be used to read and write the PC,
131 * CAS, and TC CSRs, respectively.
133 static const struct {
134 enum esirisc_reg_num number
;
141 { ESIRISC_PC
, CSR_THREAD
, CSR_THREAD_EPC
, "PC", REG_TYPE_CODE_PTR
, "general" }, /* PC -> EPC */
142 { ESIRISC_CAS
, CSR_THREAD
, CSR_THREAD_ECAS
, "CAS", REG_TYPE_INT
, "general" }, /* CAS -> ECAS */
143 { ESIRISC_TC
, CSR_THREAD
, CSR_THREAD_ETC
, "TC", REG_TYPE_INT
, "system" }, /* TC -> ETC */
144 { ESIRISC_ETA
, CSR_THREAD
, CSR_THREAD_ETA
, "ETA", REG_TYPE_INT
, "system" },
145 { ESIRISC_ETC
, CSR_THREAD
, CSR_THREAD_ETC
, "ETC", REG_TYPE_INT
, "system" },
146 { ESIRISC_EPC
, CSR_THREAD
, CSR_THREAD_EPC
, "EPC", REG_TYPE_CODE_PTR
, "system" },
147 { ESIRISC_ECAS
, CSR_THREAD
, CSR_THREAD_ECAS
, "ECAS", REG_TYPE_INT
, "system" },
148 { ESIRISC_EID
, CSR_THREAD
, CSR_THREAD_EID
, "EID", REG_TYPE_INT
, "system" },
149 { ESIRISC_ED
, CSR_THREAD
, CSR_THREAD_ED
, "ED", REG_TYPE_INT
, "system" },
150 { ESIRISC_IP
, CSR_INTERRUPT
, CSR_INTERRUPT_IP
, "IP", REG_TYPE_INT
, "system"},
151 { ESIRISC_IM
, CSR_INTERRUPT
, CSR_INTERRUPT_IM
, "IM", REG_TYPE_INT
, "system"},
152 { ESIRISC_IS
, CSR_INTERRUPT
, CSR_INTERRUPT_IS
, "IS", REG_TYPE_INT
, "system"},
153 { ESIRISC_IT
, CSR_INTERRUPT
, CSR_INTERRUPT_IT
, "IT", REG_TYPE_INT
, "system"},
156 static int esirisc_disable_interrupts(struct target
*target
)
158 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
159 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
165 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETC
, &etc
);
166 if (retval
!= ERROR_OK
) {
167 LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target
));
171 etc
&= ~(1<<0); /* TC.I */
173 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETC
, etc
);
174 if (retval
!= ERROR_OK
) {
175 LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target
));
183 static int esirisc_enable_interrupts(struct target
*target
)
185 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
186 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
192 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETC
, &etc
);
193 if (retval
!= ERROR_OK
) {
194 LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target
));
198 etc
|= (1<<0); /* TC.I */
200 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETC
, etc
);
201 if (retval
!= ERROR_OK
) {
202 LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target
));
210 static int esirisc_save_interrupts(struct target
*target
)
212 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
213 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
217 int retval
= esirisc_jtag_read_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETC
,
219 if (retval
!= ERROR_OK
) {
220 LOG_ERROR("%s: failed to read Thread CSR: ETC", target_name(target
));
227 static int esirisc_restore_interrupts(struct target
*target
)
229 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
230 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
234 int retval
= esirisc_jtag_write_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETC
,
236 if (retval
!= ERROR_OK
) {
237 LOG_ERROR("%s: failed to write Thread CSR: ETC", target_name(target
));
245 static int esirisc_save_hwdc(struct target
*target
)
247 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
248 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
252 int retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_HWDC
,
253 &esirisc
->hwdc_save
);
254 if (retval
!= ERROR_OK
) {
255 LOG_ERROR("%s: failed to read Thread CSR: HWDC", target_name(target
));
263 static int esirisc_restore_hwdc(struct target
*target
)
265 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
266 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
270 int retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_HWDC
,
272 if (retval
!= ERROR_OK
) {
273 LOG_ERROR("%s: failed to write Debug CSR: HWDC", target_name(target
));
280 static int esirisc_save_context(struct target
*target
)
282 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
286 for (unsigned i
= 0; i
< esirisc
->reg_cache
->num_regs
; ++i
) {
287 struct reg
*reg
= esirisc
->reg_cache
->reg_list
+ i
;
288 struct esirisc_reg
*reg_info
= reg
->arch_info
;
290 if (reg
->exist
&& !reg
->valid
)
297 static int esirisc_restore_context(struct target
*target
)
299 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
303 for (unsigned i
= 0; i
< esirisc
->reg_cache
->num_regs
; ++i
) {
304 struct reg
*reg
= esirisc
->reg_cache
->reg_list
+ i
;
305 struct esirisc_reg
*reg_info
= reg
->arch_info
;
307 if (reg
->exist
&& reg
->dirty
)
308 reg_info
->write(reg
);
314 static int esirisc_flush_caches(struct target
*target
)
316 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
317 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
321 if (target
->state
!= TARGET_HALTED
)
322 return ERROR_TARGET_NOT_HALTED
;
324 int retval
= esirisc_jtag_flush_caches(jtag_info
);
325 if (retval
!= ERROR_OK
) {
326 LOG_ERROR("%s: failed to flush caches", target_name(target
));
333 static int esirisc_wait_debug_active(struct esirisc_common
*esirisc
, int ms
)
335 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
342 int retval
= esirisc_jtag_enable_debug(jtag_info
);
343 if (retval
== ERROR_OK
&& esirisc_jtag_is_debug_active(jtag_info
))
346 if ((timeval_ms() - t
) > ms
)
347 return ERROR_TARGET_TIMEOUT
;
353 static int esirisc_read_memory(struct target
*target
, target_addr_t address
,
354 uint32_t size
, uint32_t count
, uint8_t *buffer
)
356 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
357 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
362 int num_bits
= 8 * size
;
363 for (uint32_t i
= 0; i
< count
; ++i
) {
364 union esirisc_memory value
;
368 case sizeof(value
.word
):
369 value_p
= &value
.word
;
370 retval
= esirisc_jtag_read_word(jtag_info
, address
, value_p
);
373 case sizeof(value
.hword
):
374 value_p
= &value
.hword
;
375 retval
= esirisc_jtag_read_hword(jtag_info
, address
, value_p
);
378 case sizeof(value
.byte
):
379 value_p
= &value
.byte
;
380 retval
= esirisc_jtag_read_byte(jtag_info
, address
, value_p
);
384 LOG_ERROR("%s: unsupported size: %" PRIu32
, target_name(target
), size
);
388 if (retval
!= ERROR_OK
) {
389 LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR
, target_name(target
),
394 buf_cpy(value_p
, buffer
, num_bits
);
402 static int esirisc_write_memory(struct target
*target
, target_addr_t address
,
403 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
405 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
406 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
411 int num_bits
= 8 * size
;
412 for (uint32_t i
= 0; i
< count
; ++i
) {
413 union esirisc_memory value
;
416 case sizeof(value
.word
):
417 value
.word
= buf_get_u32(buffer
, 0, num_bits
);
418 retval
= esirisc_jtag_write_word(jtag_info
, address
, value
.word
);
421 case sizeof(value
.hword
):
422 value
.hword
= buf_get_u32(buffer
, 0, num_bits
);
423 retval
= esirisc_jtag_write_hword(jtag_info
, address
, value
.hword
);
426 case sizeof(value
.byte
):
427 value
.byte
= buf_get_u32(buffer
, 0, num_bits
);
428 retval
= esirisc_jtag_write_byte(jtag_info
, address
, value
.byte
);
432 LOG_ERROR("%s: unsupported size: %" PRIu32
, target_name(target
), size
);
436 if (retval
!= ERROR_OK
) {
437 LOG_ERROR("%s: failed to write address: 0x%" TARGET_PRIxADDR
, target_name(target
),
449 static int esirisc_checksum_memory(struct target
*target
, target_addr_t address
,
450 uint32_t count
, uint32_t *checksum
)
452 return ERROR_FAIL
; /* not supported */
455 static int esirisc_next_breakpoint(struct target
*target
)
457 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
458 struct breakpoint
**breakpoints_p
= esirisc
->breakpoints_p
;
459 struct breakpoint
**breakpoints_e
= breakpoints_p
+ esirisc
->num_breakpoints
;
463 for (int bp_index
= 0; breakpoints_p
< breakpoints_e
; ++breakpoints_p
, ++bp_index
)
470 static int esirisc_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
472 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
473 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
481 * The default linker scripts provided by the eSi-RISC toolchain do
482 * not specify attributes on memory regions, which results in
483 * incorrect application of software breakpoints by GDB. Targets
484 * must be configured with `gdb_breakpoint_override hard` as
485 * software breakpoints are not supported.
487 if (breakpoint
->type
!= BKPT_HARD
)
488 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
490 bp_index
= esirisc_next_breakpoint(target
);
492 LOG_ERROR("%s: out of hardware breakpoints", target_name(target
));
493 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
496 breakpoint_hw_set(breakpoint
, bp_index
);
497 esirisc
->breakpoints_p
[bp_index
] = breakpoint
;
499 /* specify instruction breakpoint address */
500 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_IBA_N
+ bp_index
,
501 breakpoint
->address
);
502 if (retval
!= ERROR_OK
) {
503 LOG_ERROR("%s: failed to write Debug CSR: IBA", target_name(target
));
507 /* enable instruction breakpoint */
508 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_IBC
, &ibc
);
509 if (retval
!= ERROR_OK
) {
510 LOG_ERROR("%s: failed to read Debug CSR: IBC", target_name(target
));
514 ibc
|= (1 << bp_index
); /* IBC.In */
516 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_IBC
, ibc
);
517 if (retval
!= ERROR_OK
) {
518 LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target
));
525 static int esirisc_add_breakpoints(struct target
*target
)
527 struct breakpoint
*breakpoint
= target
->breakpoints
;
532 if (!breakpoint
->is_set
)
533 esirisc_add_breakpoint(target
, breakpoint
);
535 breakpoint
= breakpoint
->next
;
541 static int esirisc_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
543 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
544 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
545 unsigned int bp_index
= breakpoint
->number
;
551 /* disable instruction breakpoint */
552 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_IBC
, &ibc
);
553 if (retval
!= ERROR_OK
) {
554 LOG_ERROR("%s: failed to read Debug CSR: IBC", target_name(target
));
558 ibc
&= ~(1 << bp_index
); /* IBC.In */
560 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_IBC
, ibc
);
561 if (retval
!= ERROR_OK
) {
562 LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target
));
566 esirisc
->breakpoints_p
[bp_index
] = NULL
;
567 breakpoint
->is_set
= false;
572 static int esirisc_remove_breakpoints(struct target
*target
)
574 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
575 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
579 /* clear instruction breakpoints */
580 int retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_IBC
, 0);
581 if (retval
!= ERROR_OK
) {
582 LOG_ERROR("%s: failed to write Debug CSR: IBC", target_name(target
));
586 memset(esirisc
->breakpoints_p
, 0, sizeof(esirisc
->breakpoints_p
));
591 static int esirisc_next_watchpoint(struct target
*target
)
593 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
594 struct watchpoint
**watchpoints_p
= esirisc
->watchpoints_p
;
595 struct watchpoint
**watchpoints_e
= watchpoints_p
+ esirisc
->num_watchpoints
;
599 for (int wp_index
= 0; watchpoints_p
< watchpoints_e
; ++watchpoints_p
, ++wp_index
)
606 static int esirisc_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
608 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
609 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
616 wp_index
= esirisc_next_watchpoint(target
);
618 LOG_ERROR("%s: out of hardware watchpoints", target_name(target
));
622 watchpoint_set(watchpoint
, wp_index
);
623 esirisc
->watchpoints_p
[wp_index
] = watchpoint
;
625 /* specify data breakpoint address */
626 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBA_N
+ wp_index
,
627 watchpoint
->address
);
628 if (retval
!= ERROR_OK
) {
629 LOG_ERROR("%s: failed to write Debug CSR: DBA", target_name(target
));
633 /* specify data breakpoint size */
634 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBS
, &dbs
);
635 if (retval
!= ERROR_OK
) {
636 LOG_ERROR("%s: failed to read Debug CSR: DBS", target_name(target
));
641 switch (watchpoint
->length
) {
642 case sizeof(uint64_t):
645 case sizeof(uint32_t):
649 case sizeof(uint16_t):
653 case sizeof(uint8_t):
658 LOG_ERROR("%s: unsupported length: %" PRIu32
, target_name(target
),
663 dbs
|= (sn
<< (2 * wp_index
)); /* DBS.Sn */
665 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBS
, dbs
);
666 if (retval
!= ERROR_OK
) {
667 LOG_ERROR("%s: failed to write Debug CSR: DBS", target_name(target
));
671 /* enable data breakpoint */
672 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBC
, &dbc
);
673 if (retval
!= ERROR_OK
) {
674 LOG_ERROR("%s: failed to read Debug CSR: DBC", target_name(target
));
679 switch (watchpoint
->rw
) {
693 LOG_ERROR("%s: unsupported rw: %" PRId32
, target_name(target
),
698 dbc
|= (dn
<< (2 * wp_index
)); /* DBC.Dn */
700 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBC
, dbc
);
701 if (retval
!= ERROR_OK
) {
702 LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target
));
709 static int esirisc_add_watchpoints(struct target
*target
)
711 struct watchpoint
*watchpoint
= target
->watchpoints
;
716 if (!watchpoint
->is_set
)
717 esirisc_add_watchpoint(target
, watchpoint
);
719 watchpoint
= watchpoint
->next
;
725 static int esirisc_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
727 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
728 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
729 unsigned int wp_index
= watchpoint
->number
;
735 /* disable data breakpoint */
736 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBC
, &dbc
);
737 if (retval
!= ERROR_OK
) {
738 LOG_ERROR("%s: failed to read Debug CSR: DBC", target_name(target
));
742 dbc
&= ~(0x3 << (2 * wp_index
)); /* DBC.Dn */
744 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBC
, dbc
);
745 if (retval
!= ERROR_OK
) {
746 LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target
));
750 esirisc
->watchpoints_p
[wp_index
] = NULL
;
751 watchpoint
->is_set
= false;
756 static int esirisc_remove_watchpoints(struct target
*target
)
758 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
759 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
763 /* clear data breakpoints */
764 int retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DBC
, 0);
765 if (retval
!= ERROR_OK
) {
766 LOG_ERROR("%s: failed to write Debug CSR: DBC", target_name(target
));
770 memset(esirisc
->watchpoints_p
, 0, sizeof(esirisc
->watchpoints_p
));
775 static int esirisc_halt(struct target
*target
)
777 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
778 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
782 if (target
->state
== TARGET_HALTED
)
785 int retval
= esirisc_jtag_break(jtag_info
);
786 if (retval
!= ERROR_OK
) {
787 LOG_ERROR("%s: failed to halt target", target_name(target
));
791 target
->debug_reason
= DBG_REASON_DBGRQ
;
796 static int esirisc_disable_step(struct target
*target
)
798 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
799 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
805 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DC
, &dc
);
806 if (retval
!= ERROR_OK
) {
807 LOG_ERROR("%s: failed to read Debug CSR: DC", target_name(target
));
811 dc
&= ~(1<<0); /* DC.S */
813 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DC
, dc
);
814 if (retval
!= ERROR_OK
) {
815 LOG_ERROR("%s: failed to write Debug CSR: DC", target_name(target
));
822 static int esirisc_enable_step(struct target
*target
)
824 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
825 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
831 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DC
, &dc
);
832 if (retval
!= ERROR_OK
) {
833 LOG_ERROR("%s: failed to read Debug CSR: DC", target_name(target
));
837 dc
|= (1<<0); /* DC.S */
839 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_DEBUG
, CSR_DEBUG_DC
, dc
);
840 if (retval
!= ERROR_OK
) {
841 LOG_ERROR("%s: failed to write Debug CSR: DC", target_name(target
));
848 static int esirisc_resume_or_step(struct target
*target
, int current
, target_addr_t address
,
849 int handle_breakpoints
, int debug_execution
, bool step
)
851 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
852 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
853 struct breakpoint
*breakpoint
= NULL
;
858 if (target
->state
!= TARGET_HALTED
)
859 return ERROR_TARGET_NOT_HALTED
;
861 if (!debug_execution
) {
862 target_free_all_working_areas(target
);
863 esirisc_add_breakpoints(target
);
864 esirisc_add_watchpoints(target
);
868 address
= buf_get_u32(esirisc
->epc
->value
, 0, esirisc
->epc
->size
);
870 buf_set_u32(esirisc
->epc
->value
, 0, esirisc
->epc
->size
, address
);
871 esirisc
->epc
->dirty
= true;
872 esirisc
->epc
->valid
= true;
875 esirisc_restore_context(target
);
877 if (esirisc_has_cache(esirisc
))
878 esirisc_flush_caches(target
);
880 if (handle_breakpoints
) {
881 breakpoint
= breakpoint_find(target
, address
);
883 esirisc_remove_breakpoint(target
, breakpoint
);
887 esirisc_disable_interrupts(target
);
888 esirisc_enable_step(target
);
889 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
891 esirisc_disable_step(target
);
892 esirisc_restore_interrupts(target
);
893 target
->debug_reason
= DBG_REASON_NOTHALTED
;
896 esirisc_restore_hwdc(target
);
898 retval
= esirisc_jtag_continue(jtag_info
);
899 if (retval
!= ERROR_OK
) {
900 LOG_ERROR("%s: failed to resume target", target_name(target
));
904 register_cache_invalidate(esirisc
->reg_cache
);
906 if (!debug_execution
) {
907 target
->state
= TARGET_RUNNING
;
908 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
910 target
->state
= TARGET_DEBUG_RUNNING
;
911 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
917 static int esirisc_resume(struct target
*target
, int current
, target_addr_t address
,
918 int handle_breakpoints
, int debug_execution
)
922 return esirisc_resume_or_step(target
, current
, address
,
923 handle_breakpoints
, debug_execution
, false);
926 static int esirisc_step(struct target
*target
, int current
, target_addr_t address
,
927 int handle_breakpoints
)
931 return esirisc_resume_or_step(target
, current
, address
,
932 handle_breakpoints
, 0, true);
935 static int esirisc_debug_step(struct target
*target
)
937 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
938 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
943 esirisc_disable_interrupts(target
);
944 esirisc_enable_step(target
);
946 retval
= esirisc_jtag_continue(jtag_info
);
947 if (retval
!= ERROR_OK
) {
948 LOG_ERROR("%s: failed to resume target", target_name(target
));
952 retval
= esirisc_wait_debug_active(esirisc
, STEP_TIMEOUT
);
953 if (retval
!= ERROR_OK
) {
954 LOG_ERROR("%s: step timed out", target_name(target
));
958 esirisc_disable_step(target
);
959 esirisc_restore_interrupts(target
);
964 static int esirisc_debug_reset(struct target
*target
)
966 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
967 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
972 retval
= esirisc_jtag_assert_reset(jtag_info
);
973 if (retval
!= ERROR_OK
) {
974 LOG_ERROR("%s: failed to assert reset", target_name(target
));
978 retval
= esirisc_jtag_deassert_reset(jtag_info
);
979 if (retval
!= ERROR_OK
) {
980 LOG_ERROR("%s: failed to deassert reset", target_name(target
));
984 retval
= esirisc_wait_debug_active(esirisc
, RESET_TIMEOUT
);
985 if (retval
!= ERROR_OK
) {
986 LOG_ERROR("%s: reset timed out", target_name(target
));
993 static int esirisc_debug_enable(struct target
*target
)
995 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
996 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1001 retval
= esirisc_jtag_enable_debug(jtag_info
);
1002 if (retval
!= ERROR_OK
) {
1003 LOG_ERROR("%s: failed to enable debug mode", target_name(target
));
1008 * The debug clock is inactive until the first command is sent.
1009 * If the target is stopped, we must first issue a reset before
1010 * attempting further communication. This also handles unpowered
1011 * targets, which will respond with all ones and appear active.
1013 if (esirisc_jtag_is_stopped(jtag_info
)) {
1014 LOG_INFO("%s: debug clock inactive; attempting debug reset", target_name(target
));
1015 retval
= esirisc_debug_reset(target
);
1016 if (retval
!= ERROR_OK
)
1019 if (esirisc_jtag_is_stopped(jtag_info
)) {
1020 LOG_ERROR("%s: target unresponsive; giving up", target_name(target
));
1028 static int esirisc_debug_entry(struct target
*target
)
1030 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1031 struct breakpoint
*breakpoint
;
1035 esirisc_save_context(target
);
1037 if (esirisc_has_cache(esirisc
))
1038 esirisc_flush_caches(target
);
1040 if (target
->debug_reason
!= DBG_REASON_SINGLESTEP
) {
1041 esirisc_save_interrupts(target
);
1043 uint32_t eid
= buf_get_u32(esirisc
->eid
->value
, 0, esirisc
->eid
->size
);
1046 * InstBreakpoint exceptions are also raised when a core is
1047 * halted for debugging. The following is required to
1048 * determine if a breakpoint was encountered.
1050 case EID_INST_BREAKPOINT
:
1051 breakpoint
= breakpoint_find(target
,
1052 buf_get_u32(esirisc
->epc
->value
, 0, esirisc
->epc
->size
));
1053 target
->debug_reason
= (breakpoint
) ?
1054 DBG_REASON_BREAKPOINT
: DBG_REASON_DBGRQ
;
1058 * eSi-RISC treats watchpoints similarly to breakpoints,
1059 * however GDB will not request to step over the current
1060 * instruction when a watchpoint fires. The following is
1061 * required to resume the target.
1063 case EID_DATA_BREAKPOINT
:
1064 esirisc_remove_watchpoints(target
);
1065 esirisc_debug_step(target
);
1066 esirisc_add_watchpoints(target
);
1067 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
1071 target
->debug_reason
= DBG_REASON_DBGRQ
;
1078 static int esirisc_poll(struct target
*target
)
1080 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1081 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1084 retval
= esirisc_jtag_enable_debug(jtag_info
);
1085 if (retval
!= ERROR_OK
) {
1086 LOG_ERROR("%s: failed to poll target", target_name(target
));
1090 if (esirisc_jtag_is_stopped(jtag_info
)) {
1091 LOG_ERROR("%s: target has stopped; reset required", target_name(target
));
1092 target
->state
= TARGET_UNKNOWN
;
1093 return ERROR_TARGET_FAILURE
;
1096 if (esirisc_jtag_is_debug_active(jtag_info
)) {
1097 if (target
->state
== TARGET_RUNNING
|| target
->state
== TARGET_RESET
) {
1098 target
->state
= TARGET_HALTED
;
1100 retval
= esirisc_debug_entry(target
);
1101 if (retval
!= ERROR_OK
)
1104 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1107 } else if (target
->state
== TARGET_HALTED
|| target
->state
== TARGET_RESET
) {
1108 target
->state
= TARGET_RUNNING
;
1109 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1115 static int esirisc_assert_reset(struct target
*target
)
1117 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1118 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1123 if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1124 jtag_add_reset(1, 1);
1125 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) == 0)
1126 jtag_add_reset(0, 1);
1128 esirisc_remove_breakpoints(target
);
1129 esirisc_remove_watchpoints(target
);
1131 retval
= esirisc_jtag_assert_reset(jtag_info
);
1132 if (retval
!= ERROR_OK
) {
1133 LOG_ERROR("%s: failed to assert reset", target_name(target
));
1138 target
->state
= TARGET_RESET
;
1140 register_cache_invalidate(esirisc
->reg_cache
);
1145 static int esirisc_reset_entry(struct target
*target
)
1147 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1148 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1154 /* read exception table address */
1155 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_ETA
, &eta
);
1156 if (retval
!= ERROR_OK
) {
1157 LOG_ERROR("%s: failed to read Thread CSR: ETA", target_name(target
));
1161 /* read reset entry point */
1162 retval
= esirisc_jtag_read_word(jtag_info
, eta
+ ENTRY_RESET
, &epc
);
1163 if (retval
!= ERROR_OK
) {
1164 LOG_ERROR("%s: failed to read address: 0x%" TARGET_PRIxADDR
, target_name(target
),
1165 (target_addr_t
)epc
);
1169 /* write reset entry point */
1170 retval
= esirisc_jtag_write_csr(jtag_info
, CSR_THREAD
, CSR_THREAD_EPC
, epc
);
1171 if (retval
!= ERROR_OK
) {
1172 LOG_ERROR("%s: failed to write Thread CSR: EPC", target_name(target
));
1179 static int esirisc_deassert_reset(struct target
*target
)
1181 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1182 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1187 if (jtag_get_reset_config() & RESET_HAS_SRST
) {
1188 jtag_add_reset(0, 0);
1190 retval
= esirisc_debug_enable(target
);
1191 if (retval
!= ERROR_OK
)
1194 retval
= esirisc_debug_reset(target
);
1195 if (retval
!= ERROR_OK
)
1199 retval
= esirisc_jtag_deassert_reset(jtag_info
);
1200 if (retval
!= ERROR_OK
) {
1201 LOG_ERROR("%s: failed to deassert reset", target_name(target
));
1206 retval
= esirisc_wait_debug_active(esirisc
, RESET_TIMEOUT
);
1207 if (retval
!= ERROR_OK
) {
1208 LOG_ERROR("%s: reset timed out", target_name(target
));
1212 retval
= esirisc_reset_entry(target
);
1213 if (retval
!= ERROR_OK
)
1216 esirisc_add_breakpoints(target
);
1217 esirisc_add_watchpoints(target
);
1219 esirisc_restore_hwdc(target
);
1221 if (!target
->reset_halt
) {
1222 retval
= esirisc_jtag_continue(jtag_info
);
1223 if (retval
!= ERROR_OK
) {
1224 LOG_ERROR("%s: failed to resume target", target_name(target
));
1232 static int esirisc_arch_state(struct target
*target
)
1234 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1235 uint32_t epc
= buf_get_u32(esirisc
->epc
->value
, 0, esirisc
->epc
->size
);
1236 uint32_t ecas
= buf_get_u32(esirisc
->ecas
->value
, 0, esirisc
->ecas
->size
);
1237 uint32_t eid
= buf_get_u32(esirisc
->eid
->value
, 0, esirisc
->eid
->size
);
1238 uint32_t ed
= buf_get_u32(esirisc
->ed
->value
, 0, esirisc
->ed
->size
);
1240 LOG_USER("target halted due to %s, exception: %s\n"
1241 "EPC: 0x%" PRIx32
", ECAS: 0x%" PRIx32
", EID: 0x%" PRIx32
", ED: 0x%" PRIx32
,
1242 debug_reason_name(target
), esirisc_exception_strings
[eid
], epc
, ecas
, eid
, ed
);
1247 static const char *esirisc_get_gdb_arch(struct target
*target
)
1249 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1254 * Targets with the UNIFIED_ADDRESS_SPACE option disabled employ a
1255 * Harvard architecture. This option is not exposed in a CSR, which
1256 * requires additional configuration to properly interact with these
1257 * targets in GDB (also see: `esirisc cache_arch`).
1259 if (!esirisc
->gdb_arch
&& target_was_examined(target
))
1260 esirisc
->gdb_arch
= alloc_printf("esirisc:%d_bit_%d_reg_%s",
1261 esirisc
->num_bits
, esirisc
->num_regs
, esirisc_cache_arch_name(esirisc
));
1263 return esirisc
->gdb_arch
;
1266 static int esirisc_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[],
1267 int *reg_list_size
, enum target_register_class reg_class
)
1269 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1273 *reg_list_size
= ESIRISC_NUM_REGS
;
1275 *reg_list
= calloc(*reg_list_size
, sizeof(struct reg
*));
1279 if (reg_class
== REG_CLASS_ALL
)
1280 for (int i
= 0; i
< *reg_list_size
; ++i
)
1281 (*reg_list
)[i
] = esirisc
->reg_cache
->reg_list
+ i
;
1283 for (int i
= 0; i
< esirisc
->num_regs
; ++i
)
1284 (*reg_list
)[i
] = esirisc
->reg_cache
->reg_list
+ i
;
1286 (*reg_list
)[ESIRISC_PC
] = esirisc
->reg_cache
->reg_list
+ ESIRISC_PC
;
1287 (*reg_list
)[ESIRISC_CAS
] = esirisc
->reg_cache
->reg_list
+ ESIRISC_CAS
;
1293 static int esirisc_read_reg(struct reg
*reg
)
1295 struct esirisc_reg
*reg_info
= reg
->arch_info
;
1296 struct esirisc_common
*esirisc
= reg_info
->esirisc
;
1297 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1298 struct target
*target
= esirisc
->target
;
1303 int retval
= esirisc_jtag_read_reg(jtag_info
, reg
->number
, &data
);
1304 if (retval
!= ERROR_OK
) {
1305 LOG_ERROR("%s: failed to read register: %s", target_name(target
), reg
->name
);
1309 buf_set_u32(reg
->value
, 0, reg
->size
, data
);
1316 static int esirisc_write_reg(struct reg
*reg
)
1318 struct esirisc_reg
*reg_info
= reg
->arch_info
;
1319 struct esirisc_common
*esirisc
= reg_info
->esirisc
;
1320 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1321 struct target
*target
= esirisc
->target
;
1322 uint32_t data
= buf_get_u32(reg
->value
, 0, reg
->size
);
1326 int retval
= esirisc_jtag_write_reg(jtag_info
, reg
->number
, data
);
1327 if (retval
!= ERROR_OK
) {
1328 LOG_ERROR("%s: failed to write register: %s", target_name(target
), reg
->name
);
1338 static int esirisc_read_csr(struct reg
*reg
)
1340 struct esirisc_reg
*reg_info
= reg
->arch_info
;
1341 struct esirisc_common
*esirisc
= reg_info
->esirisc
;
1342 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1343 struct target
*target
= esirisc
->target
;
1348 int retval
= esirisc_jtag_read_csr(jtag_info
, reg_info
->bank
, reg_info
->csr
, &data
);
1349 if (retval
!= ERROR_OK
) {
1350 LOG_ERROR("%s: failed to read CSR: %s", target_name(target
), reg
->name
);
1354 buf_set_u32(reg
->value
, 0, reg
->size
, data
);
1361 static int esirisc_write_csr(struct reg
*reg
)
1363 struct esirisc_reg
*reg_info
= reg
->arch_info
;
1364 struct esirisc_common
*esirisc
= reg_info
->esirisc
;
1365 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1366 struct target
*target
= esirisc
->target
;
1367 uint32_t data
= buf_get_u32(reg
->value
, 0, reg
->size
);
1371 int retval
= esirisc_jtag_write_csr(jtag_info
, reg_info
->bank
, reg_info
->csr
, data
);
1372 if (retval
!= ERROR_OK
) {
1373 LOG_ERROR("%s: failed to write CSR: %s", target_name(target
), reg
->name
);
1383 static int esirisc_get_reg(struct reg
*reg
)
1385 struct esirisc_reg
*reg_info
= reg
->arch_info
;
1386 struct esirisc_common
*esirisc
= reg_info
->esirisc
;
1387 struct target
*target
= esirisc
->target
;
1391 if (target
->state
!= TARGET_HALTED
)
1392 return ERROR_TARGET_NOT_HALTED
;
1394 return reg_info
->read(reg
);
1397 static int esirisc_set_reg(struct reg
*reg
, uint8_t *buf
)
1399 struct esirisc_reg
*reg_info
= reg
->arch_info
;
1400 struct esirisc_common
*esirisc
= reg_info
->esirisc
;
1401 struct target
*target
= esirisc
->target
;
1402 uint32_t value
= buf_get_u32(buf
, 0, reg
->size
);
1406 if (target
->state
!= TARGET_HALTED
)
1407 return ERROR_TARGET_NOT_HALTED
;
1409 buf_set_u32(reg
->value
, 0, reg
->size
, value
);
1416 static const struct reg_arch_type esirisc_reg_type
= {
1417 .get
= esirisc_get_reg
,
1418 .set
= esirisc_set_reg
,
1421 static struct reg_cache
*esirisc_build_reg_cache(struct target
*target
)
1423 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1424 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
1425 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
1426 struct reg
*reg_list
= calloc(ESIRISC_NUM_REGS
, sizeof(struct reg
));
1430 cache
->name
= "eSi-RISC registers";
1432 cache
->reg_list
= reg_list
;
1433 cache
->num_regs
= ESIRISC_NUM_REGS
;
1436 esirisc
->reg_cache
= cache
;
1437 esirisc
->epc
= reg_list
+ ESIRISC_EPC
;
1438 esirisc
->ecas
= reg_list
+ ESIRISC_ECAS
;
1439 esirisc
->eid
= reg_list
+ ESIRISC_EID
;
1440 esirisc
->ed
= reg_list
+ ESIRISC_ED
;
1442 for (int i
= 0; i
< esirisc
->num_regs
; ++i
) {
1443 struct reg
*reg
= reg_list
+ esirisc_regs
[i
].number
;
1444 struct esirisc_reg
*reg_info
= calloc(1, sizeof(struct esirisc_reg
));
1446 reg
->name
= esirisc_regs
[i
].name
;
1447 reg
->number
= esirisc_regs
[i
].number
;
1448 reg
->value
= calloc(1, DIV_ROUND_UP(esirisc
->num_bits
, 8));
1449 reg
->size
= esirisc
->num_bits
;
1450 reg
->reg_data_type
= calloc(1, sizeof(struct reg_data_type
));
1451 reg
->reg_data_type
->type
= esirisc_regs
[i
].type
;
1452 reg
->group
= esirisc_regs
[i
].group
;
1453 reg_info
->esirisc
= esirisc
;
1454 reg_info
->read
= esirisc_read_reg
;
1455 reg_info
->write
= esirisc_write_reg
;
1456 reg
->arch_info
= reg_info
;
1457 reg
->type
= &esirisc_reg_type
;
1461 for (size_t i
= 0; i
< ARRAY_SIZE(esirisc_csrs
); ++i
) {
1462 struct reg
*reg
= reg_list
+ esirisc_csrs
[i
].number
;
1463 struct esirisc_reg
*reg_info
= calloc(1, sizeof(struct esirisc_reg
));
1465 reg
->name
= esirisc_csrs
[i
].name
;
1466 reg
->number
= esirisc_csrs
[i
].number
;
1467 reg
->value
= calloc(1, DIV_ROUND_UP(esirisc
->num_bits
, 8));
1468 reg
->size
= esirisc
->num_bits
;
1469 reg
->reg_data_type
= calloc(1, sizeof(struct reg_data_type
));
1470 reg
->reg_data_type
->type
= esirisc_csrs
[i
].type
;
1471 reg
->group
= esirisc_csrs
[i
].group
;
1472 reg_info
->esirisc
= esirisc
;
1473 reg_info
->bank
= esirisc_csrs
[i
].bank
;
1474 reg_info
->csr
= esirisc_csrs
[i
].csr
;
1475 reg_info
->read
= esirisc_read_csr
;
1476 reg_info
->write
= esirisc_write_csr
;
1477 reg
->arch_info
= reg_info
;
1478 reg
->type
= &esirisc_reg_type
;
1485 static int esirisc_identify(struct target
*target
)
1487 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1488 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1494 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_CONFIG
, CSR_CONFIG_ARCH0
, &csr
);
1495 if (retval
!= ERROR_OK
) {
1496 LOG_ERROR("%s: failed to read Configuration CSR: ARCH0", target_name(target
));
1500 esirisc
->num_bits
= (csr
>> 0) & 0x3f; /* ARCH0.B */
1501 esirisc
->num_regs
= (csr
>> 10) & 0x3f; /* ARCH0.R */
1503 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_CONFIG
, CSR_CONFIG_MEM
, &csr
);
1504 if (retval
!= ERROR_OK
) {
1505 LOG_ERROR("%s: failed to read Configuration CSR: MEM", target_name(target
));
1509 target
->endianness
= (csr
& 1<<0) ? /* MEM.E */
1510 TARGET_BIG_ENDIAN
: TARGET_LITTLE_ENDIAN
;
1512 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_CONFIG
, CSR_CONFIG_IC
, &csr
);
1513 if (retval
!= ERROR_OK
) {
1514 LOG_ERROR("%s: failed to read Configuration CSR: IC", target_name(target
));
1518 esirisc
->has_icache
= !!(csr
& 1<<0); /* IC.E */
1520 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_CONFIG
, CSR_CONFIG_DC
, &csr
);
1521 if (retval
!= ERROR_OK
) {
1522 LOG_ERROR("%s: failed to read Configuration CSR: DC", target_name(target
));
1526 esirisc
->has_dcache
= !!(csr
& 1<<0); /* DC.E */
1528 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_CONFIG
, CSR_CONFIG_DBG
, &csr
);
1529 if (retval
!= ERROR_OK
) {
1530 LOG_ERROR("%s: failed to read Configuration CSR: DBG", target_name(target
));
1534 esirisc
->num_breakpoints
= (csr
>> 7) & 0xf; /* DBG.BP */
1535 esirisc
->num_watchpoints
= (csr
>> 12) & 0xf; /* DBG.WP */
1537 retval
= esirisc_jtag_read_csr(jtag_info
, CSR_CONFIG
, CSR_CONFIG_TRACE
, &csr
);
1538 if (retval
!= ERROR_OK
) {
1539 LOG_ERROR("%s: failed to read Configuration CSR: TRACE", target_name(target
));
1543 esirisc
->has_trace
= !!(csr
& 1<<0); /* TRACE.T */
1548 static int esirisc_target_create(struct target
*target
, Jim_Interp
*interp
)
1550 struct jtag_tap
*tap
= target
->tap
;
1551 struct esirisc_common
*esirisc
;
1556 if (tap
->ir_length
!= INSTR_LENGTH
) {
1557 LOG_ERROR("%s: invalid IR length; expected %d", target_name(target
),
1562 esirisc
= calloc(1, sizeof(struct esirisc_common
));
1566 esirisc
->target
= target
;
1567 esirisc
->jtag_info
.tap
= tap
;
1568 target
->arch_info
= esirisc
;
1573 static int esirisc_init_target(struct command_context
*cmd_ctx
, struct target
*target
)
1575 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1577 /* trap reset, error, and debug exceptions */
1578 esirisc
->hwdc_save
= HWDC_R
| HWDC_E
| HWDC_D
;
1583 static int esirisc_examine(struct target
*target
)
1585 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1586 struct esirisc_jtag
*jtag_info
= &esirisc
->jtag_info
;
1591 if (!target_was_examined(target
)) {
1592 retval
= esirisc_debug_enable(target
);
1593 if (retval
!= ERROR_OK
)
1597 * In order to identify the target we must first halt the core.
1598 * We quietly resume once identification has completed for those
1599 * targets that were running when target_examine was called.
1601 if (esirisc_jtag_is_debug_active(jtag_info
)) {
1602 if (target
->state
== TARGET_UNKNOWN
)
1603 target
->debug_reason
= DBG_REASON_DBGRQ
;
1605 target
->state
= TARGET_HALTED
;
1607 retval
= esirisc_jtag_break(jtag_info
);
1608 if (retval
!= ERROR_OK
) {
1609 LOG_ERROR("%s: failed to halt target", target_name(target
));
1613 target
->state
= TARGET_RUNNING
;
1616 retval
= esirisc_identify(target
);
1617 if (retval
!= ERROR_OK
) {
1618 LOG_ERROR("%s: failed to identify target", target_name(target
));
1622 esirisc_build_reg_cache(target
);
1624 esirisc_remove_breakpoints(target
);
1625 esirisc_remove_watchpoints(target
);
1627 esirisc_disable_step(target
);
1628 esirisc_restore_hwdc(target
);
1630 if (target
->state
== TARGET_HALTED
)
1631 esirisc_save_interrupts(target
);
1633 retval
= esirisc_jtag_continue(jtag_info
);
1634 if (retval
!= ERROR_OK
) {
1635 LOG_ERROR("%s: failed to resume target", target_name(target
));
1640 target_set_examined(target
);
1642 LOG_INFO("%s: %d bit, %d registers, %s%s%s", target_name(target
),
1643 esirisc
->num_bits
, esirisc
->num_regs
,
1644 target_endianness(target
),
1645 esirisc
->has_icache
? ", icache" : "",
1646 esirisc
->has_dcache
? ", dcache" : "");
1648 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints%s", target_name(target
),
1649 esirisc
->num_breakpoints
, esirisc
->num_watchpoints
,
1650 esirisc
->has_trace
? ", trace" : "");
1656 COMMAND_HANDLER(handle_esirisc_cache_arch_command
)
1658 struct target
*target
= get_current_target(CMD_CTX
);
1659 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1662 if (strcmp(*CMD_ARGV
, "harvard") == 0)
1663 esirisc
->cache_arch
= ESIRISC_CACHE_HARVARD
;
1664 else if (strcmp(*CMD_ARGV
, "von_neumann") == 0)
1665 esirisc
->cache_arch
= ESIRISC_CACHE_VON_NEUMANN
;
1667 LOG_ERROR("invalid cache_arch: %s", *CMD_ARGV
);
1668 return ERROR_COMMAND_SYNTAX_ERROR
;
1672 command_print(CMD
, "esirisc cache_arch %s", esirisc_cache_arch_name(esirisc
));
1677 COMMAND_HANDLER(handle_esirisc_flush_caches_command
)
1679 struct target
*target
= get_current_target(CMD_CTX
);
1680 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1683 if (!esirisc_has_cache(esirisc
)) {
1684 LOG_ERROR("target does not support caching");
1688 retval
= esirisc_flush_caches(target
);
1690 command_print(CMD
, "cache flush %s",
1691 (retval
== ERROR_OK
) ? "successful" : "failed");
1696 static const struct {
1699 } esirisc_hwdc_masks
[] = {
1700 { "reset", HWDC_R
},
1701 { "interrupt", HWDC_I
},
1702 { "syscall", HWDC_S
},
1703 { "error", HWDC_E
},
1704 { "debug", HWDC_D
},
1707 static int esirisc_find_hwdc_mask(const char *name
)
1709 for (size_t i
= 0; i
< ARRAY_SIZE(esirisc_hwdc_masks
); ++i
)
1710 if (strcmp(esirisc_hwdc_masks
[i
].name
, name
) == 0)
1711 return esirisc_hwdc_masks
[i
].mask
;
1716 COMMAND_HANDLER(handle_esirisc_hwdc_command
)
1718 struct target
*target
= get_current_target(CMD_CTX
);
1719 struct esirisc_common
*esirisc
= target_to_esirisc(target
);
1722 if (strcmp(CMD_ARGV
[0], "all") == 0)
1723 esirisc
->hwdc_save
= HWDC_R
| HWDC_I
| HWDC_S
| HWDC_E
| HWDC_D
;
1725 esirisc
->hwdc_save
= 0;
1726 if (strcmp(CMD_ARGV
[0], "none") != 0) {
1727 while (CMD_ARGC
-- > 0) {
1728 int mask
= esirisc_find_hwdc_mask(CMD_ARGV
[CMD_ARGC
]);
1730 LOG_ERROR("invalid mask: %s", CMD_ARGV
[CMD_ARGC
]);
1731 return ERROR_COMMAND_SYNTAX_ERROR
;
1733 esirisc
->hwdc_save
|= mask
;
1739 for (size_t i
= 0; i
< ARRAY_SIZE(esirisc_hwdc_masks
); ++i
)
1740 command_print(CMD
, "%9s: %s", esirisc_hwdc_masks
[i
].name
,
1741 (esirisc
->hwdc_save
& esirisc_hwdc_masks
[i
].mask
) ? "enabled" : "disabled");
1746 static const struct command_registration esirisc_exec_command_handlers
[] = {
1748 .name
= "flush_caches",
1749 .handler
= handle_esirisc_flush_caches_command
,
1750 .mode
= COMMAND_EXEC
,
1751 .help
= "flush instruction and data caches",
1754 COMMAND_REGISTRATION_DONE
1757 static const struct command_registration esirisc_any_command_handlers
[] = {
1759 .name
= "cache_arch",
1760 .handler
= handle_esirisc_cache_arch_command
,
1761 .mode
= COMMAND_ANY
,
1762 .help
= "configure cache architecture",
1763 .usage
= "['harvard'|'von_neumann']",
1767 .handler
= handle_esirisc_hwdc_command
,
1768 .mode
= COMMAND_ANY
,
1769 .help
= "configure hardware debug control",
1770 .usage
= "['all'|'none'|mask ...]",
1773 .chain
= esirisc_exec_command_handlers
1776 .chain
= esirisc_trace_command_handlers
1778 COMMAND_REGISTRATION_DONE
1781 static const struct command_registration esirisc_command_handlers
[] = {
1784 .mode
= COMMAND_ANY
,
1785 .help
= "eSi-RISC command group",
1787 .chain
= esirisc_any_command_handlers
,
1789 COMMAND_REGISTRATION_DONE
1792 struct target_type esirisc_target
= {
1795 .poll
= esirisc_poll
,
1796 .arch_state
= esirisc_arch_state
,
1798 .halt
= esirisc_halt
,
1799 .resume
= esirisc_resume
,
1800 .step
= esirisc_step
,
1802 .assert_reset
= esirisc_assert_reset
,
1803 .deassert_reset
= esirisc_deassert_reset
,
1805 .get_gdb_arch
= esirisc_get_gdb_arch
,
1806 .get_gdb_reg_list
= esirisc_get_gdb_reg_list
,
1808 .read_memory
= esirisc_read_memory
,
1809 .write_memory
= esirisc_write_memory
,
1810 .checksum_memory
= esirisc_checksum_memory
,
1812 .add_breakpoint
= esirisc_add_breakpoint
,
1813 .remove_breakpoint
= esirisc_remove_breakpoint
,
1814 .add_watchpoint
= esirisc_add_watchpoint
,
1815 .remove_watchpoint
= esirisc_remove_watchpoint
,
1817 .commands
= esirisc_command_handlers
,
1819 .target_create
= esirisc_target_create
,
1820 .init_target
= esirisc_init_target
,
1821 .examine
= esirisc_examine
,
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)