1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
7 * Copyright (C) 2006 by Magnus Lundin *
10 * Copyright (C) 2008 by Spencer Oliver *
11 * spen@spen-soft.co.uk *
12 ***************************************************************************/
14 #ifndef OPENOCD_TARGET_CORTEX_M_H
15 #define OPENOCD_TARGET_CORTEX_M_H
18 #include "helper/bits.h"
20 #define CORTEX_M_COMMON_MAGIC 0x1A451A45U
22 #define SYSTEM_CONTROL_BASE 0x400FE000
24 #define ITM_TER0 0xE0000E00
25 #define ITM_TPR 0xE0000E40
26 #define ITM_TCR 0xE0000E80
27 #define ITM_TCR_ITMENA_BIT BIT(0)
28 #define ITM_TCR_BUSY_BIT BIT(23)
29 #define ITM_LAR 0xE0000FB0
30 #define ITM_LAR_KEY 0xC5ACCE55
32 #define CPUID 0xE000ED00
34 #define ARM_CPUID_PARTNO_POS 4
35 #define ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS)
37 enum cortex_m_partno
{
38 CORTEX_M_PARTNO_INVALID
,
39 CORTEX_M0_PARTNO
= 0xC20,
40 CORTEX_M1_PARTNO
= 0xC21,
41 CORTEX_M3_PARTNO
= 0xC23,
42 CORTEX_M4_PARTNO
= 0xC24,
43 CORTEX_M7_PARTNO
= 0xC27,
44 CORTEX_M0P_PARTNO
= 0xC60,
45 CORTEX_M23_PARTNO
= 0xD20,
46 CORTEX_M33_PARTNO
= 0xD21,
47 CORTEX_M35P_PARTNO
= 0xD31,
48 CORTEX_M55_PARTNO
= 0xD22,
51 /* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */
52 #define CORTEX_M_F_HAS_FPV4 BIT(0)
53 #define CORTEX_M_F_HAS_FPV5 BIT(1)
54 #define CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K BIT(2)
56 struct cortex_m_part_info
{
57 enum cortex_m_partno partno
;
63 /* Debug Control Block */
64 #define DCB_DHCSR 0xE000EDF0
65 #define DCB_DCRSR 0xE000EDF4
66 #define DCB_DCRDR 0xE000EDF8
67 #define DCB_DEMCR 0xE000EDFC
68 #define DCB_DSCSR 0xE000EE08
70 #define DCRSR_WNR BIT(16)
72 #define DWT_CTRL 0xE0001000
73 #define DWT_CYCCNT 0xE0001004
74 #define DWT_PCSR 0xE000101C
75 #define DWT_COMP0 0xE0001020
76 #define DWT_MASK0 0xE0001024
77 #define DWT_FUNCTION0 0xE0001028
78 #define DWT_DEVARCH 0xE0001FBC
80 #define DWT_DEVARCH_ARMV8M 0x101A02
82 #define FP_CTRL 0xE0002000
83 #define FP_REMAP 0xE0002004
84 #define FP_COMP0 0xE0002008
85 #define FP_COMP1 0xE000200C
86 #define FP_COMP2 0xE0002010
87 #define FP_COMP3 0xE0002014
88 #define FP_COMP4 0xE0002018
89 #define FP_COMP5 0xE000201C
90 #define FP_COMP6 0xE0002020
91 #define FP_COMP7 0xE0002024
93 #define FPU_CPACR 0xE000ED88
94 #define FPU_FPCCR 0xE000EF34
95 #define FPU_FPCAR 0xE000EF38
96 #define FPU_FPDSCR 0xE000EF3C
98 #define TPIU_SSPSR 0xE0040000
99 #define TPIU_CSPSR 0xE0040004
100 #define TPIU_ACPR 0xE0040010
101 #define TPIU_SPPR 0xE00400F0
102 #define TPIU_FFSR 0xE0040300
103 #define TPIU_FFCR 0xE0040304
104 #define TPIU_FSCR 0xE0040308
106 /* Maximum SWO prescaler value. */
107 #define TPIU_ACPR_MAX_SWOSCALER 0x1fff
109 /* DCB_DHCSR bit and field definitions */
110 #define DBGKEY (0xA05Ful << 16)
111 #define C_DEBUGEN BIT(0)
112 #define C_HALT BIT(1)
113 #define C_STEP BIT(2)
114 #define C_MASKINTS BIT(3)
115 #define S_REGRDY BIT(16)
116 #define S_HALT BIT(17)
117 #define S_SLEEP BIT(18)
118 #define S_LOCKUP BIT(19)
119 #define S_RETIRE_ST BIT(24)
120 #define S_RESET_ST BIT(25)
122 /* DCB_DEMCR bit and field definitions */
123 #define TRCENA BIT(24)
124 #define VC_HARDERR BIT(10)
125 #define VC_INTERR BIT(9)
126 #define VC_BUSERR BIT(8)
127 #define VC_STATERR BIT(7)
128 #define VC_CHKERR BIT(6)
129 #define VC_NOCPERR BIT(5)
130 #define VC_MMERR BIT(4)
131 #define VC_CORERESET BIT(0)
133 /* DCB_DSCSR bit and field definitions */
134 #define DSCSR_CDS BIT(16)
137 #define NVIC_ICTR 0xE000E004
138 #define NVIC_ISE0 0xE000E100
139 #define NVIC_ICSR 0xE000ED04
140 #define NVIC_AIRCR 0xE000ED0C
141 #define NVIC_SHCSR 0xE000ED24
142 #define NVIC_CFSR 0xE000ED28
143 #define NVIC_MMFSRB 0xE000ED28
144 #define NVIC_BFSRB 0xE000ED29
145 #define NVIC_USFSRH 0xE000ED2A
146 #define NVIC_HFSR 0xE000ED2C
147 #define NVIC_DFSR 0xE000ED30
148 #define NVIC_MMFAR 0xE000ED34
149 #define NVIC_BFAR 0xE000ED38
150 #define NVIC_SFSR 0xE000EDE4
151 #define NVIC_SFAR 0xE000EDE8
153 /* NVIC_AIRCR bits */
154 #define AIRCR_VECTKEY (0x5FAul << 16)
155 #define AIRCR_SYSRESETREQ BIT(2)
156 #define AIRCR_VECTCLRACTIVE BIT(1)
157 #define AIRCR_VECTRESET BIT(0)
158 /* NVIC_SHCSR bits */
159 #define SHCSR_BUSFAULTENA BIT(17)
161 #define DFSR_HALTED 1
163 #define DFSR_DWTTRAP 4
164 #define DFSR_VCATCH 8
165 #define DFSR_EXTERNAL 16
168 #define FPCR_LITERAL 1
169 #define FPCR_REPLACE_REMAP (0ul << 30)
170 #define FPCR_REPLACE_BKPT_LOW (1ul << 30)
171 #define FPCR_REPLACE_BKPT_HIGH (2ul << 30)
172 #define FPCR_REPLACE_BKPT_BOTH (3ul << 30)
174 struct cortex_m_fp_comparator
{
178 uint32_t fpcr_address
;
181 struct cortex_m_dwt_comparator
{
186 uint32_t dwt_comparator_address
;
189 enum cortex_m_soft_reset_config
{
190 CORTEX_M_RESET_SYSRESETREQ
,
191 CORTEX_M_RESET_VECTRESET
,
194 enum cortex_m_isrmasking_mode
{
195 CORTEX_M_ISRMASK_AUTO
,
196 CORTEX_M_ISRMASK_OFF
,
198 CORTEX_M_ISRMASK_STEPONLY
,
201 struct cortex_m_common
{
202 unsigned int common_magic
;
204 struct armv7m_common armv7m
;
206 /* Context information */
208 uint32_t dcb_dhcsr_cumulated_sticky
;
209 uint32_t nvic_dfsr
; /* Debug Fault Status Register - shows reason for debug halt */
210 uint32_t nvic_icsr
; /* Interrupt Control State Register - shows active and pending IRQ */
212 /* Flash Patch and Breakpoint (FPB) */
213 unsigned int fp_num_lit
;
214 unsigned int fp_num_code
;
217 struct cortex_m_fp_comparator
*fp_comparator_list
;
219 /* Data Watchpoint and Trace (DWT) */
220 unsigned int dwt_num_comp
;
221 unsigned int dwt_comp_available
;
222 uint32_t dwt_devarch
;
223 struct cortex_m_dwt_comparator
*dwt_comparator_list
;
224 struct reg_cache
*dwt_cache
;
226 enum cortex_m_soft_reset_config soft_reset_config
;
227 bool vectreset_supported
;
228 enum cortex_m_isrmasking_mode isrmasking_mode
;
230 const struct cortex_m_part_info
*core_info
;
232 bool slow_register_read
; /* A register has not been ready, poll S_REGRDY */
236 /* Whether this target has the erratum that makes C_MASKINTS not apply to
237 * already pending interrupts */
238 bool maskints_erratum
;
241 static inline bool is_cortex_m_or_hla(const struct cortex_m_common
*cortex_m
)
243 return cortex_m
->common_magic
== CORTEX_M_COMMON_MAGIC
;
246 static inline bool is_cortex_m_with_dap_access(const struct cortex_m_common
*cortex_m
)
248 if (!is_cortex_m_or_hla(cortex_m
))
251 return !cortex_m
->armv7m
.is_hla_target
;
255 * @returns the pointer to the target specific struct
256 * without matching a magic number.
257 * Use in target specific service routines, where the correct
258 * type of arch_info is certain.
260 static inline struct cortex_m_common
*
261 target_to_cm(struct target
*target
)
263 return container_of(target
->arch_info
,
264 struct cortex_m_common
, armv7m
.arm
);
268 * @returns the pointer to the target specific struct
269 * or NULL if the magic number does not match.
270 * Use in a flash driver or any place where mismatch of the arch_info
273 static inline struct cortex_m_common
*
274 target_to_cortex_m_safe(struct target
*target
)
276 /* Check the parent types first to prevent peeking memory too far
277 * from arch_info pointer */
278 if (!target_to_armv7m_safe(target
))
281 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
282 if (!is_cortex_m_or_hla(cortex_m
))
289 * @returns cached value of Cortex-M part number
290 * or CORTEX_M_PARTNO_INVALID if the magic number does not match
291 * or core_info is not initialised.
293 static inline enum cortex_m_partno
cortex_m_get_partno_safe(struct target
*target
)
295 struct cortex_m_common
*cortex_m
= target_to_cortex_m_safe(target
);
297 return CORTEX_M_PARTNO_INVALID
;
299 if (!cortex_m
->core_info
)
300 return CORTEX_M_PARTNO_INVALID
;
302 return cortex_m
->core_info
->partno
;
305 int cortex_m_examine(struct target
*target
);
306 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
307 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
308 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
309 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
);
310 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
);
311 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
);
312 void cortex_m_enable_breakpoints(struct target
*target
);
313 void cortex_m_enable_watchpoints(struct target
*target
);
314 void cortex_m_deinit_target(struct target
*target
);
315 int cortex_m_profiling(struct target
*target
, uint32_t *samples
,
316 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
);
318 #endif /* OPENOCD_TARGET_CORTEX_M_H */
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