1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
27 ***************************************************************************/
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
43 /* NOTE: most of this should work fine for the Cortex-M1 and
44 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
45 * Some differences: M0/M1 doesn't have FPB remapping or the
46 * DWT tracing/profiling support. (So the cycle counter will
47 * not be usable; the other stuff isn't currently used here.)
49 * Although there are some workarounds for errata seen only in r0p0
50 * silicon, such old parts are hard to find and thus not much tested
54 /* forward declarations */
55 static int cortex_m_store_core_reg_u32(struct target
*target
,
56 uint32_t num
, uint32_t value
);
57 static void cortex_m_dwt_free(struct target
*target
);
59 static int cortexm_dap_read_coreregister_u32(struct target
*target
,
60 uint32_t *value
, int regnum
)
62 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
66 /* because the DCB_DCRDR is used for the emulated dcc channel
67 * we have to save/restore the DCB_DCRDR when used */
68 if (target
->dbg_msg_enabled
) {
69 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
70 if (retval
!= ERROR_OK
)
74 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
);
75 if (retval
!= ERROR_OK
)
78 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
79 if (retval
!= ERROR_OK
)
82 if (target
->dbg_msg_enabled
) {
83 /* restore DCB_DCRDR - this needs to be in a separate
84 * transaction otherwise the emulated DCC channel breaks */
85 if (retval
== ERROR_OK
)
86 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
92 static int cortexm_dap_write_coreregister_u32(struct target
*target
,
93 uint32_t value
, int regnum
)
95 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
99 /* because the DCB_DCRDR is used for the emulated dcc channel
100 * we have to save/restore the DCB_DCRDR when used */
101 if (target
->dbg_msg_enabled
) {
102 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
103 if (retval
!= ERROR_OK
)
107 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
108 if (retval
!= ERROR_OK
)
111 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRSR
, regnum
| DCRSR_WnR
);
112 if (retval
!= ERROR_OK
)
115 if (target
->dbg_msg_enabled
) {
116 /* restore DCB_DCRDR - this needs to be in a seperate
117 * transaction otherwise the emulated DCC channel breaks */
118 if (retval
== ERROR_OK
)
119 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
125 static int cortex_m_write_debug_halt_mask(struct target
*target
,
126 uint32_t mask_on
, uint32_t mask_off
)
128 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
129 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
131 /* mask off status bits */
132 cortex_m
->dcb_dhcsr
&= ~((0xFFFF << 16) | mask_off
);
133 /* create new register mask */
134 cortex_m
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
136 return mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, cortex_m
->dcb_dhcsr
);
139 static int cortex_m_set_maskints(struct target
*target
, bool mask
)
141 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
142 if (!!(cortex_m
->dcb_dhcsr
& C_MASKINTS
) != mask
)
143 return cortex_m_write_debug_halt_mask(target
, mask
? C_MASKINTS
: 0, mask
? 0 : C_MASKINTS
);
148 static int cortex_m_set_maskints_for_halt(struct target
*target
)
150 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
151 switch (cortex_m
->isrmasking_mode
) {
152 case CORTEX_M_ISRMASK_AUTO
:
153 /* interrupts taken at resume, whether for step or run -> no mask */
154 return cortex_m_set_maskints(target
, false);
156 case CORTEX_M_ISRMASK_OFF
:
157 /* interrupts never masked */
158 return cortex_m_set_maskints(target
, false);
160 case CORTEX_M_ISRMASK_ON
:
161 /* interrupts always masked */
162 return cortex_m_set_maskints(target
, true);
164 case CORTEX_M_ISRMASK_STEPONLY
:
165 /* interrupts masked for single step only -> mask now if MASKINTS
166 * erratum, otherwise only mask before stepping */
167 return cortex_m_set_maskints(target
, cortex_m
->maskints_erratum
);
172 static int cortex_m_set_maskints_for_run(struct target
*target
)
174 switch (target_to_cm(target
)->isrmasking_mode
) {
175 case CORTEX_M_ISRMASK_AUTO
:
176 /* interrupts taken at resume, whether for step or run -> no mask */
177 return cortex_m_set_maskints(target
, false);
179 case CORTEX_M_ISRMASK_OFF
:
180 /* interrupts never masked */
181 return cortex_m_set_maskints(target
, false);
183 case CORTEX_M_ISRMASK_ON
:
184 /* interrupts always masked */
185 return cortex_m_set_maskints(target
, true);
187 case CORTEX_M_ISRMASK_STEPONLY
:
188 /* interrupts masked for single step only -> no mask */
189 return cortex_m_set_maskints(target
, false);
194 static int cortex_m_set_maskints_for_step(struct target
*target
)
196 switch (target_to_cm(target
)->isrmasking_mode
) {
197 case CORTEX_M_ISRMASK_AUTO
:
198 /* the auto-interrupt should already be done -> mask */
199 return cortex_m_set_maskints(target
, true);
201 case CORTEX_M_ISRMASK_OFF
:
202 /* interrupts never masked */
203 return cortex_m_set_maskints(target
, false);
205 case CORTEX_M_ISRMASK_ON
:
206 /* interrupts always masked */
207 return cortex_m_set_maskints(target
, true);
209 case CORTEX_M_ISRMASK_STEPONLY
:
210 /* interrupts masked for single step only -> mask */
211 return cortex_m_set_maskints(target
, true);
216 static int cortex_m_clear_halt(struct target
*target
)
218 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
219 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
222 /* clear step if any */
223 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
225 /* Read Debug Fault Status Register */
226 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, &cortex_m
->nvic_dfsr
);
227 if (retval
!= ERROR_OK
)
230 /* Clear Debug Fault Status */
231 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, cortex_m
->nvic_dfsr
);
232 if (retval
!= ERROR_OK
)
234 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m
->nvic_dfsr
);
239 static int cortex_m_single_step_core(struct target
*target
)
241 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
242 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
245 /* Mask interrupts before clearing halt, if not done already. This avoids
246 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
247 * HALT can put the core into an unknown state.
249 if (!(cortex_m
->dcb_dhcsr
& C_MASKINTS
)) {
250 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
251 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
252 if (retval
!= ERROR_OK
)
255 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
256 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
257 if (retval
!= ERROR_OK
)
261 /* restore dhcsr reg */
262 cortex_m_clear_halt(target
);
267 static int cortex_m_enable_fpb(struct target
*target
)
269 int retval
= target_write_u32(target
, FP_CTRL
, 3);
270 if (retval
!= ERROR_OK
)
273 /* check the fpb is actually enabled */
275 retval
= target_read_u32(target
, FP_CTRL
, &fpctrl
);
276 if (retval
!= ERROR_OK
)
285 static int cortex_m_endreset_event(struct target
*target
)
290 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
291 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
292 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
293 struct cortex_m_fp_comparator
*fp_list
= cortex_m
->fp_comparator_list
;
294 struct cortex_m_dwt_comparator
*dwt_list
= cortex_m
->dwt_comparator_list
;
296 /* REVISIT The four debug monitor bits are currently ignored... */
297 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &dcb_demcr
);
298 if (retval
!= ERROR_OK
)
300 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
302 /* this register is used for emulated dcc channel */
303 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
304 if (retval
!= ERROR_OK
)
307 /* Enable debug requests */
308 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
309 if (retval
!= ERROR_OK
)
311 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
312 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
313 if (retval
!= ERROR_OK
)
317 /* Restore proper interrupt masking setting for running CPU. */
318 cortex_m_set_maskints_for_run(target
);
320 /* Enable features controlled by ITM and DWT blocks, and catch only
321 * the vectors we were told to pay attention to.
323 * Target firmware is responsible for all fault handling policy
324 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
325 * or manual updates to the NVIC SHCSR and CCR registers.
327 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
328 if (retval
!= ERROR_OK
)
331 /* Paranoia: evidently some (early?) chips don't preserve all the
332 * debug state (including FPB, DWT, etc) across reset...
336 retval
= cortex_m_enable_fpb(target
);
337 if (retval
!= ERROR_OK
) {
338 LOG_ERROR("Failed to enable the FPB");
342 cortex_m
->fpb_enabled
= true;
344 /* Restore FPB registers */
345 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
346 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
347 if (retval
!= ERROR_OK
)
351 /* Restore DWT registers */
352 for (i
= 0; i
< cortex_m
->dwt_num_comp
; i
++) {
353 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
355 if (retval
!= ERROR_OK
)
357 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
359 if (retval
!= ERROR_OK
)
361 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
362 dwt_list
[i
].function
);
363 if (retval
!= ERROR_OK
)
366 retval
= dap_run(swjdp
);
367 if (retval
!= ERROR_OK
)
370 register_cache_invalidate(armv7m
->arm
.core_cache
);
372 /* make sure we have latest dhcsr flags */
373 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
378 static int cortex_m_examine_debug_reason(struct target
*target
)
380 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
382 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
383 * only check the debug reason if we don't know it already */
385 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
386 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
387 if (cortex_m
->nvic_dfsr
& DFSR_BKPT
) {
388 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
389 if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
390 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
391 } else if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
392 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
393 else if (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)
394 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
395 else if (cortex_m
->nvic_dfsr
& DFSR_EXTERNAL
)
396 target
->debug_reason
= DBG_REASON_DBGRQ
;
398 target
->debug_reason
= DBG_REASON_UNDEFINED
;
404 static int cortex_m_examine_exception_reason(struct target
*target
)
406 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
407 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
408 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
411 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SHCSR
, &shcsr
);
412 if (retval
!= ERROR_OK
)
414 switch (armv7m
->exception_number
) {
417 case 3: /* Hard Fault */
418 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_HFSR
, &except_sr
);
419 if (retval
!= ERROR_OK
)
421 if (except_sr
& 0x40000000) {
422 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &cfsr
);
423 if (retval
!= ERROR_OK
)
427 case 4: /* Memory Management */
428 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
429 if (retval
!= ERROR_OK
)
431 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_MMFAR
, &except_ar
);
432 if (retval
!= ERROR_OK
)
435 case 5: /* Bus Fault */
436 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
437 if (retval
!= ERROR_OK
)
439 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_BFAR
, &except_ar
);
440 if (retval
!= ERROR_OK
)
443 case 6: /* Usage Fault */
444 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
445 if (retval
!= ERROR_OK
)
448 case 11: /* SVCall */
450 case 12: /* Debug Monitor */
451 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_DFSR
, &except_sr
);
452 if (retval
!= ERROR_OK
)
455 case 14: /* PendSV */
457 case 15: /* SysTick */
463 retval
= dap_run(swjdp
);
464 if (retval
== ERROR_OK
)
465 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
466 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
467 armv7m_exception_string(armv7m
->exception_number
),
468 shcsr
, except_sr
, cfsr
, except_ar
);
472 static int cortex_m_debug_entry(struct target
*target
)
477 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
478 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
479 struct arm
*arm
= &armv7m
->arm
;
484 /* Do this really early to minimize the window where the MASKINTS erratum
485 * can pile up pending interrupts. */
486 cortex_m_set_maskints_for_halt(target
);
488 cortex_m_clear_halt(target
);
489 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
490 if (retval
!= ERROR_OK
)
493 retval
= armv7m
->examine_debug_reason(target
);
494 if (retval
!= ERROR_OK
)
497 /* Examine target state and mode
498 * First load register accessible through core debug port */
499 int num_regs
= arm
->core_cache
->num_regs
;
501 for (i
= 0; i
< num_regs
; i
++) {
502 r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
504 arm
->read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
508 xPSR
= buf_get_u32(r
->value
, 0, 32);
510 /* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
513 cortex_m_store_core_reg_u32(target
, 16, xPSR
& ~0xff);
516 /* Are we in an exception handler */
518 armv7m
->exception_number
= (xPSR
& 0x1FF);
520 arm
->core_mode
= ARM_MODE_HANDLER
;
521 arm
->map
= armv7m_msp_reg_map
;
523 unsigned control
= buf_get_u32(arm
->core_cache
524 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 2);
526 /* is this thread privileged? */
527 arm
->core_mode
= control
& 1
528 ? ARM_MODE_USER_THREAD
531 /* which stack is it using? */
533 arm
->map
= armv7m_psp_reg_map
;
535 arm
->map
= armv7m_msp_reg_map
;
537 armv7m
->exception_number
= 0;
540 if (armv7m
->exception_number
)
541 cortex_m_examine_exception_reason(target
);
543 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", target->state: %s",
544 arm_mode_name(arm
->core_mode
),
545 buf_get_u32(arm
->pc
->value
, 0, 32),
546 target_state_name(target
));
548 if (armv7m
->post_debug_entry
) {
549 retval
= armv7m
->post_debug_entry(target
);
550 if (retval
!= ERROR_OK
)
557 static int cortex_m_poll(struct target
*target
)
559 int detected_failure
= ERROR_OK
;
560 int retval
= ERROR_OK
;
561 enum target_state prev_target_state
= target
->state
;
562 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
563 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
565 /* Read from Debug Halting Control and Status Register */
566 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
567 if (retval
!= ERROR_OK
) {
568 target
->state
= TARGET_UNKNOWN
;
572 /* Recover from lockup. See ARMv7-M architecture spec,
573 * section B1.5.15 "Unrecoverable exception cases".
575 if (cortex_m
->dcb_dhcsr
& S_LOCKUP
) {
576 LOG_ERROR("%s -- clearing lockup after double fault",
577 target_name(target
));
578 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
579 target
->debug_reason
= DBG_REASON_DBGRQ
;
581 /* We have to execute the rest (the "finally" equivalent, but
582 * still throw this exception again).
584 detected_failure
= ERROR_FAIL
;
586 /* refresh status bits */
587 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
588 if (retval
!= ERROR_OK
)
592 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
593 if (target
->state
!= TARGET_RESET
) {
594 target
->state
= TARGET_RESET
;
595 LOG_INFO("%s: external reset detected", target_name(target
));
600 if (target
->state
== TARGET_RESET
) {
601 /* Cannot switch context while running so endreset is
602 * called with target->state == TARGET_RESET
604 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
605 cortex_m
->dcb_dhcsr
);
606 retval
= cortex_m_endreset_event(target
);
607 if (retval
!= ERROR_OK
) {
608 target
->state
= TARGET_UNKNOWN
;
611 target
->state
= TARGET_RUNNING
;
612 prev_target_state
= TARGET_RUNNING
;
615 if (cortex_m
->dcb_dhcsr
& S_HALT
) {
616 target
->state
= TARGET_HALTED
;
618 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
619 retval
= cortex_m_debug_entry(target
);
620 if (retval
!= ERROR_OK
)
623 if (arm_semihosting(target
, &retval
) != 0)
626 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
628 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
630 retval
= cortex_m_debug_entry(target
);
631 if (retval
!= ERROR_OK
)
634 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
638 /* REVISIT when S_SLEEP is set, it's in a Sleep or DeepSleep state.
639 * How best to model low power modes?
642 if (target
->state
== TARGET_UNKNOWN
) {
643 /* check if processor is retiring instructions */
644 if (cortex_m
->dcb_dhcsr
& S_RETIRE_ST
) {
645 target
->state
= TARGET_RUNNING
;
650 /* Check that target is truly halted, since the target could be resumed externally */
651 if ((prev_target_state
== TARGET_HALTED
) && !(cortex_m
->dcb_dhcsr
& S_HALT
)) {
652 /* registers are now invalid */
653 register_cache_invalidate(armv7m
->arm
.core_cache
);
655 target
->state
= TARGET_RUNNING
;
656 LOG_WARNING("%s: external resume detected", target_name(target
));
657 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
661 /* Did we detect a failure condition that we cleared? */
662 if (detected_failure
!= ERROR_OK
)
663 retval
= detected_failure
;
667 static int cortex_m_halt(struct target
*target
)
669 LOG_DEBUG("target->state: %s",
670 target_state_name(target
));
672 if (target
->state
== TARGET_HALTED
) {
673 LOG_DEBUG("target was already halted");
677 if (target
->state
== TARGET_UNKNOWN
)
678 LOG_WARNING("target was in unknown state when halt was requested");
680 if (target
->state
== TARGET_RESET
) {
681 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
682 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
683 return ERROR_TARGET_FAILURE
;
685 /* we came here in a reset_halt or reset_init sequence
686 * debug entry was already prepared in cortex_m3_assert_reset()
688 target
->debug_reason
= DBG_REASON_DBGRQ
;
694 /* Write to Debug Halting Control and Status Register */
695 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
697 /* Do this really early to minimize the window where the MASKINTS erratum
698 * can pile up pending interrupts. */
699 cortex_m_set_maskints_for_halt(target
);
701 target
->debug_reason
= DBG_REASON_DBGRQ
;
706 static int cortex_m_soft_reset_halt(struct target
*target
)
708 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
709 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
710 uint32_t dcb_dhcsr
= 0;
711 int retval
, timeout
= 0;
713 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
714 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
715 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
716 * core, not the peripherals */
717 LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
720 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_STEP
| C_MASKINTS
);
721 if (retval
!= ERROR_OK
)
724 /* Enter debug state on reset; restore DEMCR in endreset_event() */
725 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
,
726 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
727 if (retval
!= ERROR_OK
)
730 /* Request a core-only reset */
731 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
732 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
733 if (retval
!= ERROR_OK
)
735 target
->state
= TARGET_RESET
;
737 /* registers are now invalid */
738 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
740 while (timeout
< 100) {
741 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &dcb_dhcsr
);
742 if (retval
== ERROR_OK
) {
743 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
,
744 &cortex_m
->nvic_dfsr
);
745 if (retval
!= ERROR_OK
)
747 if ((dcb_dhcsr
& S_HALT
)
748 && (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)) {
749 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
751 (unsigned) dcb_dhcsr
,
752 (unsigned) cortex_m
->nvic_dfsr
);
753 cortex_m_poll(target
);
754 /* FIXME restore user's vector catch config */
757 LOG_DEBUG("waiting for system reset-halt, "
758 "DHCSR 0x%08x, %d ms",
759 (unsigned) dcb_dhcsr
, timeout
);
768 void cortex_m_enable_breakpoints(struct target
*target
)
770 struct breakpoint
*breakpoint
= target
->breakpoints
;
772 /* set any pending breakpoints */
774 if (!breakpoint
->set
)
775 cortex_m_set_breakpoint(target
, breakpoint
);
776 breakpoint
= breakpoint
->next
;
780 static int cortex_m_resume(struct target
*target
, int current
,
781 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
783 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
784 struct breakpoint
*breakpoint
= NULL
;
788 if (target
->state
!= TARGET_HALTED
) {
789 LOG_WARNING("target not halted");
790 return ERROR_TARGET_NOT_HALTED
;
793 if (!debug_execution
) {
794 target_free_all_working_areas(target
);
795 cortex_m_enable_breakpoints(target
);
796 cortex_m_enable_watchpoints(target
);
799 if (debug_execution
) {
800 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
802 /* Disable interrupts */
803 /* We disable interrupts in the PRIMASK register instead of
804 * masking with C_MASKINTS. This is probably the same issue
805 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
806 * in parallel with disabled interrupts can cause local faults
809 * REVISIT this clearly breaks non-debug execution, since the
810 * PRIMASK register state isn't saved/restored... workaround
811 * by never resuming app code after debug execution.
813 buf_set_u32(r
->value
, 0, 1, 1);
817 /* Make sure we are in Thumb mode */
818 r
= armv7m
->arm
.cpsr
;
819 buf_set_u32(r
->value
, 24, 1, 1);
824 /* current = 1: continue on current pc, otherwise continue at <address> */
827 buf_set_u32(r
->value
, 0, 32, address
);
832 /* if we halted last time due to a bkpt instruction
833 * then we have to manually step over it, otherwise
834 * the core will break again */
836 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
838 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
840 resume_pc
= buf_get_u32(r
->value
, 0, 32);
842 armv7m_restore_context(target
);
844 /* the front-end may request us not to handle breakpoints */
845 if (handle_breakpoints
) {
846 /* Single step past breakpoint at current address */
847 breakpoint
= breakpoint_find(target
, resume_pc
);
849 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT
" (ID: %" PRIu32
")",
851 breakpoint
->unique_id
);
852 cortex_m_unset_breakpoint(target
, breakpoint
);
853 cortex_m_single_step_core(target
);
854 cortex_m_set_breakpoint(target
, breakpoint
);
859 cortex_m_set_maskints_for_run(target
);
860 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
862 target
->debug_reason
= DBG_REASON_NOTHALTED
;
864 /* registers are now invalid */
865 register_cache_invalidate(armv7m
->arm
.core_cache
);
867 if (!debug_execution
) {
868 target
->state
= TARGET_RUNNING
;
869 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
870 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
872 target
->state
= TARGET_DEBUG_RUNNING
;
873 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
874 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
880 /* int irqstepcount = 0; */
881 static int cortex_m_step(struct target
*target
, int current
,
882 target_addr_t address
, int handle_breakpoints
)
884 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
885 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
886 struct breakpoint
*breakpoint
= NULL
;
887 struct reg
*pc
= armv7m
->arm
.pc
;
888 bool bkpt_inst_found
= false;
890 bool isr_timed_out
= false;
892 if (target
->state
!= TARGET_HALTED
) {
893 LOG_WARNING("target not halted");
894 return ERROR_TARGET_NOT_HALTED
;
897 /* current = 1: continue on current pc, otherwise continue at <address> */
899 buf_set_u32(pc
->value
, 0, 32, address
);
901 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
903 /* the front-end may request us not to handle breakpoints */
904 if (handle_breakpoints
) {
905 breakpoint
= breakpoint_find(target
, pc_value
);
907 cortex_m_unset_breakpoint(target
, breakpoint
);
910 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
912 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
914 armv7m_restore_context(target
);
916 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
918 /* if no bkpt instruction is found at pc then we can perform
919 * a normal step, otherwise we have to manually step over the bkpt
920 * instruction - as such simulate a step */
921 if (bkpt_inst_found
== false) {
922 if (cortex_m
->isrmasking_mode
!= CORTEX_M_ISRMASK_AUTO
) {
923 /* Automatic ISR masking mode off: Just step over the next
924 * instruction, with interrupts on or off as appropriate. */
925 cortex_m_set_maskints_for_step(target
);
926 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
928 /* Process interrupts during stepping in a way they don't interfere
933 * Set a temporary break point at the current pc and let the core run
934 * with interrupts enabled. Pending interrupts get served and we run
935 * into the breakpoint again afterwards. Then we step over the next
936 * instruction with interrupts disabled.
938 * If the pending interrupts don't complete within time, we leave the
939 * core running. This may happen if the interrupts trigger faster
940 * than the core can process them or the handler doesn't return.
942 * If no more breakpoints are available we simply do a step with
943 * interrupts enabled.
949 * If a break point is already set on the lower half word then a break point on
950 * the upper half word will not break again when the core is restarted. So we
951 * just step over the instruction with interrupts disabled.
953 * The documentation has no information about this, it was found by observation
954 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
955 * suffer from this problem.
957 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
958 * address has it always cleared. The former is done to indicate thumb mode
962 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
963 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
964 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
965 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
966 /* Re-enable interrupts if appropriate */
967 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
968 cortex_m_set_maskints_for_halt(target
);
972 /* Set a temporary break point */
974 retval
= cortex_m_set_breakpoint(target
, breakpoint
);
976 enum breakpoint_type type
= BKPT_HARD
;
977 if (cortex_m
->fp_rev
== 0 && pc_value
> 0x1FFFFFFF) {
978 /* FPB rev.1 cannot handle such addr, try BKPT instr */
981 retval
= breakpoint_add(target
, pc_value
, 2, type
);
984 bool tmp_bp_set
= (retval
== ERROR_OK
);
986 /* No more breakpoints left, just do a step */
988 cortex_m_set_maskints_for_step(target
);
989 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
990 /* Re-enable interrupts if appropriate */
991 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
992 cortex_m_set_maskints_for_halt(target
);
995 LOG_DEBUG("Starting core to serve pending interrupts");
996 int64_t t_start
= timeval_ms();
997 cortex_m_set_maskints_for_run(target
);
998 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
1000 /* Wait for pending handlers to complete or timeout */
1002 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
,
1004 &cortex_m
->dcb_dhcsr
);
1005 if (retval
!= ERROR_OK
) {
1006 target
->state
= TARGET_UNKNOWN
;
1009 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
1010 } while (!((cortex_m
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
1012 /* only remove breakpoint if we created it */
1014 cortex_m_unset_breakpoint(target
, breakpoint
);
1016 /* Remove the temporary breakpoint */
1017 breakpoint_remove(target
, pc_value
);
1020 if (isr_timed_out
) {
1021 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1022 "leaving target running");
1024 /* Step over next instruction with interrupts disabled */
1025 cortex_m_set_maskints_for_step(target
);
1026 cortex_m_write_debug_halt_mask(target
,
1027 C_HALT
| C_MASKINTS
,
1029 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1030 /* Re-enable interrupts if appropriate */
1031 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1032 cortex_m_set_maskints_for_halt(target
);
1039 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1040 if (retval
!= ERROR_OK
)
1043 /* registers are now invalid */
1044 register_cache_invalidate(armv7m
->arm
.core_cache
);
1047 cortex_m_set_breakpoint(target
, breakpoint
);
1049 if (isr_timed_out
) {
1050 /* Leave the core running. The user has to stop execution manually. */
1051 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1052 target
->state
= TARGET_RUNNING
;
1056 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1057 " nvic_icsr = 0x%" PRIx32
,
1058 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1060 retval
= cortex_m_debug_entry(target
);
1061 if (retval
!= ERROR_OK
)
1063 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1065 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1066 " nvic_icsr = 0x%" PRIx32
,
1067 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1072 static int cortex_m_assert_reset(struct target
*target
)
1074 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1075 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1076 enum cortex_m_soft_reset_config reset_config
= cortex_m
->soft_reset_config
;
1078 LOG_DEBUG("target->state: %s",
1079 target_state_name(target
));
1081 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1083 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
1084 /* allow scripts to override the reset event */
1086 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1087 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1088 target
->state
= TARGET_RESET
;
1093 /* some cores support connecting while srst is asserted
1094 * use that mode is it has been configured */
1096 bool srst_asserted
= false;
1098 if (!target_was_examined(target
)) {
1099 if (jtag_reset_config
& RESET_HAS_SRST
) {
1100 adapter_assert_reset();
1101 if (target
->reset_halt
)
1102 LOG_ERROR("Target not examined, will not halt after reset!");
1105 LOG_ERROR("Target not examined, reset NOT asserted!");
1110 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1111 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1112 adapter_assert_reset();
1113 srst_asserted
= true;
1116 /* Enable debug requests */
1118 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1119 /* Store important errors instead of failing and proceed to reset assert */
1121 if (retval
!= ERROR_OK
|| !(cortex_m
->dcb_dhcsr
& C_DEBUGEN
))
1122 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
1124 /* If the processor is sleeping in a WFI or WFE instruction, the
1125 * C_HALT bit must be asserted to regain control */
1126 if (retval
== ERROR_OK
&& (cortex_m
->dcb_dhcsr
& S_SLEEP
))
1127 retval
= cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1129 mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
1130 /* Ignore less important errors */
1132 if (!target
->reset_halt
) {
1133 /* Set/Clear C_MASKINTS in a separate operation */
1134 cortex_m_set_maskints_for_run(target
);
1136 /* clear any debug flags before resuming */
1137 cortex_m_clear_halt(target
);
1139 /* clear C_HALT in dhcsr reg */
1140 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1142 /* Halt in debug on reset; endreset_event() restores DEMCR.
1144 * REVISIT catching BUSERR presumably helps to defend against
1145 * bad vector table entries. Should this include MMERR or
1149 retval2
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
,
1150 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1151 if (retval
!= ERROR_OK
|| retval2
!= ERROR_OK
)
1152 LOG_INFO("AP write error, reset will not halt");
1155 if (jtag_reset_config
& RESET_HAS_SRST
) {
1156 /* default to asserting srst */
1158 adapter_assert_reset();
1160 /* srst is asserted, ignore AP access errors */
1163 /* Use a standard Cortex-M3 software reset mechanism.
1164 * We default to using VECRESET as it is supported on all current cores
1165 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1166 * This has the disadvantage of not resetting the peripherals, so a
1167 * reset-init event handler is needed to perform any peripheral resets.
1169 if (!cortex_m
->vectreset_supported
1170 && reset_config
== CORTEX_M_RESET_VECTRESET
) {
1171 reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
1172 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1173 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1176 LOG_DEBUG("Using Cortex-M %s", (reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1177 ? "SYSRESETREQ" : "VECTRESET");
1179 if (reset_config
== CORTEX_M_RESET_VECTRESET
) {
1180 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1181 "handler to reset any peripherals or configure hardware srst support.");
1185 retval3
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
1186 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1187 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1188 if (retval3
!= ERROR_OK
)
1189 LOG_DEBUG("Ignoring AP write error right after reset");
1191 retval3
= dap_dp_init(armv7m
->debug_ap
->dap
);
1192 if (retval3
!= ERROR_OK
)
1193 LOG_ERROR("DP initialisation failed");
1196 /* I do not know why this is necessary, but it
1197 * fixes strange effects (step/resume cause NMI
1198 * after reset) on LM3S6918 -- Michael Schwingen
1201 mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
, &tmp
);
1205 target
->state
= TARGET_RESET
;
1208 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1210 /* now return stored error code if any */
1211 if (retval
!= ERROR_OK
)
1214 if (target
->reset_halt
) {
1215 retval
= target_halt(target
);
1216 if (retval
!= ERROR_OK
)
1223 static int cortex_m_deassert_reset(struct target
*target
)
1225 struct armv7m_common
*armv7m
= &target_to_cm(target
)->armv7m
;
1227 LOG_DEBUG("target->state: %s",
1228 target_state_name(target
));
1230 /* deassert reset lines */
1231 adapter_deassert_reset();
1233 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1235 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1236 !(jtag_reset_config
& RESET_SRST_NO_GATING
) &&
1237 target_was_examined(target
)) {
1238 int retval
= dap_dp_init(armv7m
->debug_ap
->dap
);
1239 if (retval
!= ERROR_OK
) {
1240 LOG_ERROR("DP initialisation failed");
1248 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1252 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1253 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1255 if (breakpoint
->set
) {
1256 LOG_WARNING("breakpoint (BPID: %" PRIu32
") already set", breakpoint
->unique_id
);
1260 if (breakpoint
->type
== BKPT_HARD
) {
1261 uint32_t fpcr_value
;
1262 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m
->fp_num_code
))
1264 if (fp_num
>= cortex_m
->fp_num_code
) {
1265 LOG_ERROR("Can not find free FPB Comparator!");
1266 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1268 breakpoint
->set
= fp_num
+ 1;
1269 fpcr_value
= breakpoint
->address
| 1;
1270 if (cortex_m
->fp_rev
== 0) {
1271 if (breakpoint
->address
> 0x1FFFFFFF) {
1272 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1276 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1277 fpcr_value
= (fpcr_value
& 0x1FFFFFFC) | hilo
| 1;
1278 } else if (cortex_m
->fp_rev
> 1) {
1279 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1282 comparator_list
[fp_num
].used
= true;
1283 comparator_list
[fp_num
].fpcr_value
= fpcr_value
;
1284 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1285 comparator_list
[fp_num
].fpcr_value
);
1286 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1288 comparator_list
[fp_num
].fpcr_value
);
1289 if (!cortex_m
->fpb_enabled
) {
1290 LOG_DEBUG("FPB wasn't enabled, do it now");
1291 retval
= cortex_m_enable_fpb(target
);
1292 if (retval
!= ERROR_OK
) {
1293 LOG_ERROR("Failed to enable the FPB");
1297 cortex_m
->fpb_enabled
= true;
1299 } else if (breakpoint
->type
== BKPT_SOFT
) {
1302 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1303 * semihosting; don't use that. Otherwise the BKPT
1304 * parameter is arbitrary.
1306 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1307 retval
= target_read_memory(target
,
1308 breakpoint
->address
& 0xFFFFFFFE,
1309 breakpoint
->length
, 1,
1310 breakpoint
->orig_instr
);
1311 if (retval
!= ERROR_OK
)
1313 retval
= target_write_memory(target
,
1314 breakpoint
->address
& 0xFFFFFFFE,
1315 breakpoint
->length
, 1,
1317 if (retval
!= ERROR_OK
)
1319 breakpoint
->set
= true;
1322 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1323 breakpoint
->unique_id
,
1324 (int)(breakpoint
->type
),
1325 breakpoint
->address
,
1332 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1335 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1336 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1338 if (!breakpoint
->set
) {
1339 LOG_WARNING("breakpoint not set");
1343 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1344 breakpoint
->unique_id
,
1345 (int)(breakpoint
->type
),
1346 breakpoint
->address
,
1350 if (breakpoint
->type
== BKPT_HARD
) {
1351 int fp_num
= breakpoint
->set
- 1;
1352 if ((fp_num
< 0) || (fp_num
>= cortex_m
->fp_num_code
)) {
1353 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1356 comparator_list
[fp_num
].used
= false;
1357 comparator_list
[fp_num
].fpcr_value
= 0;
1358 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1359 comparator_list
[fp_num
].fpcr_value
);
1361 /* restore original instruction (kept in target endianness) */
1362 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE,
1363 breakpoint
->length
, 1,
1364 breakpoint
->orig_instr
);
1365 if (retval
!= ERROR_OK
)
1368 breakpoint
->set
= false;
1373 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1375 if (breakpoint
->length
== 3) {
1376 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1377 breakpoint
->length
= 2;
1380 if ((breakpoint
->length
!= 2)) {
1381 LOG_INFO("only breakpoints of two bytes length supported");
1382 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1385 return cortex_m_set_breakpoint(target
, breakpoint
);
1388 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1390 if (!breakpoint
->set
)
1393 return cortex_m_unset_breakpoint(target
, breakpoint
);
1396 int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1399 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1401 /* REVISIT Don't fully trust these "not used" records ... users
1402 * may set up breakpoints by hand, e.g. dual-address data value
1403 * watchpoint using comparator #1; comparator #0 matching cycle
1404 * count; send data trace info through ITM and TPIU; etc
1406 struct cortex_m_dwt_comparator
*comparator
;
1408 for (comparator
= cortex_m
->dwt_comparator_list
;
1409 comparator
->used
&& dwt_num
< cortex_m
->dwt_num_comp
;
1410 comparator
++, dwt_num
++)
1412 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
1413 LOG_ERROR("Can not find free DWT Comparator");
1416 comparator
->used
= true;
1417 watchpoint
->set
= dwt_num
+ 1;
1419 comparator
->comp
= watchpoint
->address
;
1420 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1423 if ((cortex_m
->dwt_devarch
& 0x1FFFFF) != DWT_DEVARCH_ARMV8M
) {
1424 uint32_t mask
= 0, temp
;
1426 /* watchpoint params were validated earlier */
1427 temp
= watchpoint
->length
;
1434 comparator
->mask
= mask
;
1435 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1438 switch (watchpoint
->rw
) {
1440 comparator
->function
= 5;
1443 comparator
->function
= 6;
1446 comparator
->function
= 7;
1450 uint32_t data_size
= watchpoint
->length
>> 1;
1451 comparator
->mask
= (watchpoint
->length
>> 1) | 1;
1453 switch (watchpoint
->rw
) {
1455 comparator
->function
= 4;
1458 comparator
->function
= 5;
1461 comparator
->function
= 6;
1464 comparator
->function
= comparator
->function
| (1 << 4) |
1468 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1469 comparator
->function
);
1471 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1472 watchpoint
->unique_id
, dwt_num
,
1473 (unsigned) comparator
->comp
,
1474 (unsigned) comparator
->mask
,
1475 (unsigned) comparator
->function
);
1479 int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1481 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1482 struct cortex_m_dwt_comparator
*comparator
;
1485 if (!watchpoint
->set
) {
1486 LOG_WARNING("watchpoint (wpid: %d) not set",
1487 watchpoint
->unique_id
);
1491 dwt_num
= watchpoint
->set
- 1;
1493 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1494 watchpoint
->unique_id
, dwt_num
,
1495 (unsigned) watchpoint
->address
);
1497 if ((dwt_num
< 0) || (dwt_num
>= cortex_m
->dwt_num_comp
)) {
1498 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1502 comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
1503 comparator
->used
= false;
1504 comparator
->function
= 0;
1505 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1506 comparator
->function
);
1508 watchpoint
->set
= false;
1513 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1515 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1517 if (cortex_m
->dwt_comp_available
< 1) {
1518 LOG_DEBUG("no comparators?");
1519 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1522 /* hardware doesn't support data value masking */
1523 if (watchpoint
->mask
!= ~(uint32_t)0) {
1524 LOG_DEBUG("watchpoint value masks not supported");
1525 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1528 /* hardware allows address masks of up to 32K */
1531 for (mask
= 0; mask
< 16; mask
++) {
1532 if ((1u << mask
) == watchpoint
->length
)
1536 LOG_DEBUG("unsupported watchpoint length");
1537 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1539 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1540 LOG_DEBUG("watchpoint address is unaligned");
1541 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1544 /* Caller doesn't seem to be able to describe watching for data
1545 * values of zero; that flags "no value".
1547 * REVISIT This DWT may well be able to watch for specific data
1548 * values. Requires comparator #1 to set DATAVMATCH and match
1549 * the data, and another comparator (DATAVADDR0) matching addr.
1551 if (watchpoint
->value
) {
1552 LOG_DEBUG("data value watchpoint not YET supported");
1553 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1556 cortex_m
->dwt_comp_available
--;
1557 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1562 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1564 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1566 /* REVISIT why check? DWT can be updated with core running ... */
1567 if (target
->state
!= TARGET_HALTED
) {
1568 LOG_WARNING("target not halted");
1569 return ERROR_TARGET_NOT_HALTED
;
1572 if (watchpoint
->set
)
1573 cortex_m_unset_watchpoint(target
, watchpoint
);
1575 cortex_m
->dwt_comp_available
++;
1576 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1581 void cortex_m_enable_watchpoints(struct target
*target
)
1583 struct watchpoint
*watchpoint
= target
->watchpoints
;
1585 /* set any pending watchpoints */
1586 while (watchpoint
) {
1587 if (!watchpoint
->set
)
1588 cortex_m_set_watchpoint(target
, watchpoint
);
1589 watchpoint
= watchpoint
->next
;
1593 static int cortex_m_load_core_reg_u32(struct target
*target
,
1594 uint32_t num
, uint32_t *value
)
1598 /* NOTE: we "know" here that the register identifiers used
1599 * in the v7m header match the Cortex-M3 Debug Core Register
1600 * Selector values for R0..R15, xPSR, MSP, and PSP.
1604 /* read a normal core register */
1605 retval
= cortexm_dap_read_coreregister_u32(target
, value
, num
);
1607 if (retval
!= ERROR_OK
) {
1608 LOG_ERROR("JTAG failure %i", retval
);
1609 return ERROR_JTAG_DEVICE_ERROR
;
1611 LOG_DEBUG("load from core reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1615 /* Floating-point Status and Registers */
1616 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21);
1617 if (retval
!= ERROR_OK
)
1619 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1620 if (retval
!= ERROR_OK
)
1622 LOG_DEBUG("load from FPSCR value 0x%" PRIx32
, *value
);
1625 case ARMV7M_S0
... ARMV7M_S31
:
1626 /* Floating-point Status and Registers */
1627 retval
= target_write_u32(target
, DCB_DCRSR
, num
- ARMV7M_S0
+ 0x40);
1628 if (retval
!= ERROR_OK
)
1630 retval
= target_read_u32(target
, DCB_DCRDR
, value
);
1631 if (retval
!= ERROR_OK
)
1633 LOG_DEBUG("load from FPU reg S%d value 0x%" PRIx32
,
1634 (int)(num
- ARMV7M_S0
), *value
);
1637 case ARMV7M_PRIMASK
:
1638 case ARMV7M_BASEPRI
:
1639 case ARMV7M_FAULTMASK
:
1640 case ARMV7M_CONTROL
:
1641 /* Cortex-M3 packages these four registers as bitfields
1642 * in one Debug Core register. So say r0 and r2 docs;
1643 * it was removed from r1 docs, but still works.
1645 cortexm_dap_read_coreregister_u32(target
, value
, 20);
1648 case ARMV7M_PRIMASK
:
1649 *value
= buf_get_u32((uint8_t *)value
, 0, 1);
1652 case ARMV7M_BASEPRI
:
1653 *value
= buf_get_u32((uint8_t *)value
, 8, 8);
1656 case ARMV7M_FAULTMASK
:
1657 *value
= buf_get_u32((uint8_t *)value
, 16, 1);
1660 case ARMV7M_CONTROL
:
1661 *value
= buf_get_u32((uint8_t *)value
, 24, 2);
1665 LOG_DEBUG("load from special reg %i value 0x%" PRIx32
"", (int)num
, *value
);
1669 return ERROR_COMMAND_SYNTAX_ERROR
;
1675 static int cortex_m_store_core_reg_u32(struct target
*target
,
1676 uint32_t num
, uint32_t value
)
1680 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1682 /* NOTE: we "know" here that the register identifiers used
1683 * in the v7m header match the Cortex-M3 Debug Core Register
1684 * Selector values for R0..R15, xPSR, MSP, and PSP.
1688 retval
= cortexm_dap_write_coreregister_u32(target
, value
, num
);
1689 if (retval
!= ERROR_OK
) {
1692 LOG_ERROR("JTAG failure");
1693 r
= armv7m
->arm
.core_cache
->reg_list
+ num
;
1694 r
->dirty
= r
->valid
;
1695 return ERROR_JTAG_DEVICE_ERROR
;
1697 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", (int)num
, value
);
1701 /* Floating-point Status and Registers */
1702 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1703 if (retval
!= ERROR_OK
)
1705 retval
= target_write_u32(target
, DCB_DCRSR
, 0x21 | (1<<16));
1706 if (retval
!= ERROR_OK
)
1708 LOG_DEBUG("write FPSCR value 0x%" PRIx32
, value
);
1711 case ARMV7M_S0
... ARMV7M_S31
:
1712 /* Floating-point Status and Registers */
1713 retval
= target_write_u32(target
, DCB_DCRDR
, value
);
1714 if (retval
!= ERROR_OK
)
1716 retval
= target_write_u32(target
, DCB_DCRSR
, (num
- ARMV7M_S0
+ 0x40) | (1<<16));
1717 if (retval
!= ERROR_OK
)
1719 LOG_DEBUG("write FPU reg S%d value 0x%" PRIx32
,
1720 (int)(num
- ARMV7M_S0
), value
);
1723 case ARMV7M_PRIMASK
:
1724 case ARMV7M_BASEPRI
:
1725 case ARMV7M_FAULTMASK
:
1726 case ARMV7M_CONTROL
:
1727 /* Cortex-M3 packages these four registers as bitfields
1728 * in one Debug Core register. So say r0 and r2 docs;
1729 * it was removed from r1 docs, but still works.
1731 cortexm_dap_read_coreregister_u32(target
, ®
, 20);
1734 case ARMV7M_PRIMASK
:
1735 buf_set_u32((uint8_t *)®
, 0, 1, value
);
1738 case ARMV7M_BASEPRI
:
1739 buf_set_u32((uint8_t *)®
, 8, 8, value
);
1742 case ARMV7M_FAULTMASK
:
1743 buf_set_u32((uint8_t *)®
, 16, 1, value
);
1746 case ARMV7M_CONTROL
:
1747 buf_set_u32((uint8_t *)®
, 24, 2, value
);
1751 cortexm_dap_write_coreregister_u32(target
, reg
, 20);
1753 LOG_DEBUG("write special reg %i value 0x%" PRIx32
" ", (int)num
, value
);
1757 return ERROR_COMMAND_SYNTAX_ERROR
;
1763 static int cortex_m_read_memory(struct target
*target
, target_addr_t address
,
1764 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1766 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1768 if (armv7m
->arm
.is_armv6m
) {
1769 /* armv6m does not handle unaligned memory access */
1770 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1771 return ERROR_TARGET_UNALIGNED_ACCESS
;
1774 return mem_ap_read_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1777 static int cortex_m_write_memory(struct target
*target
, target_addr_t address
,
1778 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1780 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1782 if (armv7m
->arm
.is_armv6m
) {
1783 /* armv6m does not handle unaligned memory access */
1784 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1785 return ERROR_TARGET_UNALIGNED_ACCESS
;
1788 return mem_ap_write_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1791 static int cortex_m_init_target(struct command_context
*cmd_ctx
,
1792 struct target
*target
)
1794 armv7m_build_reg_cache(target
);
1795 arm_semihosting_init(target
);
1799 void cortex_m_deinit_target(struct target
*target
)
1801 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1803 free(cortex_m
->fp_comparator_list
);
1805 cortex_m_dwt_free(target
);
1806 armv7m_free_reg_cache(target
);
1808 free(target
->private_config
);
1812 int cortex_m_profiling(struct target
*target
, uint32_t *samples
,
1813 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
)
1815 struct timeval timeout
, now
;
1816 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1818 bool use_pcsr
= false;
1819 int retval
= ERROR_OK
;
1822 gettimeofday(&timeout
, NULL
);
1823 timeval_add_time(&timeout
, seconds
, 0);
1825 retval
= target_read_u32(target
, DWT_PCSR
, ®_value
);
1826 if (retval
!= ERROR_OK
) {
1827 LOG_ERROR("Error while reading PCSR");
1831 if (reg_value
!= 0) {
1833 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1835 LOG_INFO("Starting profiling. Halting and resuming the"
1836 " target as often as we can...");
1837 reg
= register_get_by_name(target
->reg_cache
, "pc", 1);
1840 /* Make sure the target is running */
1841 target_poll(target
);
1842 if (target
->state
== TARGET_HALTED
)
1843 retval
= target_resume(target
, 1, 0, 0, 0);
1845 if (retval
!= ERROR_OK
) {
1846 LOG_ERROR("Error while resuming target");
1850 uint32_t sample_count
= 0;
1854 if (armv7m
&& armv7m
->debug_ap
) {
1855 uint32_t read_count
= max_num_samples
- sample_count
;
1856 if (read_count
> 1024)
1859 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
,
1860 (void *)&samples
[sample_count
],
1861 4, read_count
, DWT_PCSR
);
1862 sample_count
+= read_count
;
1864 target_read_u32(target
, DWT_PCSR
, &samples
[sample_count
++]);
1867 target_poll(target
);
1868 if (target
->state
== TARGET_HALTED
) {
1869 reg_value
= buf_get_u32(reg
->value
, 0, 32);
1870 /* current pc, addr = 0, do not handle breakpoints, not debugging */
1871 retval
= target_resume(target
, 1, 0, 0, 0);
1872 samples
[sample_count
++] = reg_value
;
1873 target_poll(target
);
1874 alive_sleep(10); /* sleep 10ms, i.e. <100 samples/second. */
1875 } else if (target
->state
== TARGET_RUNNING
) {
1876 /* We want to quickly sample the PC. */
1877 retval
= target_halt(target
);
1879 LOG_INFO("Target not halted or running");
1885 if (retval
!= ERROR_OK
) {
1886 LOG_ERROR("Error while reading %s", use_pcsr
? "PCSR" : "target pc");
1891 gettimeofday(&now
, NULL
);
1892 if (sample_count
>= max_num_samples
|| timeval_compare(&now
, &timeout
) > 0) {
1893 LOG_INFO("Profiling completed. %" PRIu32
" samples.", sample_count
);
1898 *num_samples
= sample_count
;
1903 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1904 * on r/w if the core is not running, and clear on resume or reset ... or
1905 * at least, in a post_restore_context() method.
1908 struct dwt_reg_state
{
1909 struct target
*target
;
1911 uint8_t value
[4]; /* scratch/cache */
1914 static int cortex_m_dwt_get_reg(struct reg
*reg
)
1916 struct dwt_reg_state
*state
= reg
->arch_info
;
1919 int retval
= target_read_u32(state
->target
, state
->addr
, &tmp
);
1920 if (retval
!= ERROR_OK
)
1923 buf_set_u32(state
->value
, 0, 32, tmp
);
1927 static int cortex_m_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1929 struct dwt_reg_state
*state
= reg
->arch_info
;
1931 return target_write_u32(state
->target
, state
->addr
,
1932 buf_get_u32(buf
, 0, reg
->size
));
1941 static const struct dwt_reg dwt_base_regs
[] = {
1942 { DWT_CTRL
, "dwt_ctrl", 32, },
1943 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1944 * increments while the core is asleep.
1946 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1947 /* plus some 8 bit counters, useful for profiling with TPIU */
1950 static const struct dwt_reg dwt_comp
[] = {
1951 #define DWT_COMPARATOR(i) \
1952 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1953 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1954 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1971 #undef DWT_COMPARATOR
1974 static const struct reg_arch_type dwt_reg_type
= {
1975 .get
= cortex_m_dwt_get_reg
,
1976 .set
= cortex_m_dwt_set_reg
,
1979 static void cortex_m_dwt_addreg(struct target
*t
, struct reg
*r
, const struct dwt_reg
*d
)
1981 struct dwt_reg_state
*state
;
1983 state
= calloc(1, sizeof(*state
));
1986 state
->addr
= d
->addr
;
1991 r
->value
= state
->value
;
1992 r
->arch_info
= state
;
1993 r
->type
= &dwt_reg_type
;
1996 void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
)
1999 struct reg_cache
*cache
;
2000 struct cortex_m_dwt_comparator
*comparator
;
2003 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
2004 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32
, dwtcr
);
2006 LOG_DEBUG("no DWT");
2010 target_read_u32(target
, DWT_DEVARCH
, &cm
->dwt_devarch
);
2011 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32
, cm
->dwt_devarch
);
2013 cm
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
2014 cm
->dwt_comp_available
= cm
->dwt_num_comp
;
2015 cm
->dwt_comparator_list
= calloc(cm
->dwt_num_comp
,
2016 sizeof(struct cortex_m_dwt_comparator
));
2017 if (!cm
->dwt_comparator_list
) {
2019 cm
->dwt_num_comp
= 0;
2020 LOG_ERROR("out of mem");
2024 cache
= calloc(1, sizeof(*cache
));
2027 free(cm
->dwt_comparator_list
);
2030 cache
->name
= "Cortex-M DWT registers";
2031 cache
->num_regs
= 2 + cm
->dwt_num_comp
* 3;
2032 cache
->reg_list
= calloc(cache
->num_regs
, sizeof(*cache
->reg_list
));
2033 if (!cache
->reg_list
) {
2038 for (reg
= 0; reg
< 2; reg
++)
2039 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2040 dwt_base_regs
+ reg
);
2042 comparator
= cm
->dwt_comparator_list
;
2043 for (i
= 0; i
< cm
->dwt_num_comp
; i
++, comparator
++) {
2046 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
2047 for (j
= 0; j
< 3; j
++, reg
++)
2048 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2049 dwt_comp
+ 3 * i
+ j
);
2051 /* make sure we clear any watchpoints enabled on the target */
2052 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
2055 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
2056 cm
->dwt_cache
= cache
;
2058 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
2059 dwtcr
, cm
->dwt_num_comp
,
2060 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
2062 /* REVISIT: if num_comp > 1, check whether comparator #1 can
2063 * implement single-address data value watchpoints ... so we
2064 * won't need to check it later, when asked to set one up.
2068 static void cortex_m_dwt_free(struct target
*target
)
2070 struct cortex_m_common
*cm
= target_to_cm(target
);
2071 struct reg_cache
*cache
= cm
->dwt_cache
;
2073 free(cm
->dwt_comparator_list
);
2074 cm
->dwt_comparator_list
= NULL
;
2075 cm
->dwt_num_comp
= 0;
2078 register_unlink_cache(&target
->reg_cache
, cache
);
2080 if (cache
->reg_list
) {
2081 for (size_t i
= 0; i
< cache
->num_regs
; i
++)
2082 free(cache
->reg_list
[i
].arch_info
);
2083 free(cache
->reg_list
);
2087 cm
->dwt_cache
= NULL
;
2090 #define MVFR0 0xe000ef40
2091 #define MVFR1 0xe000ef44
2093 #define MVFR0_DEFAULT_M4 0x10110021
2094 #define MVFR1_DEFAULT_M4 0x11000011
2096 #define MVFR0_DEFAULT_M7_SP 0x10110021
2097 #define MVFR0_DEFAULT_M7_DP 0x10110221
2098 #define MVFR1_DEFAULT_M7_SP 0x11000011
2099 #define MVFR1_DEFAULT_M7_DP 0x12000011
2101 static int cortex_m_find_mem_ap(struct adiv5_dap
*swjdp
,
2102 struct adiv5_ap
**debug_ap
)
2104 if (dap_find_ap(swjdp
, AP_TYPE_AHB3_AP
, debug_ap
) == ERROR_OK
)
2107 return dap_find_ap(swjdp
, AP_TYPE_AHB5_AP
, debug_ap
);
2110 int cortex_m_examine(struct target
*target
)
2113 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
2115 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2116 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
2117 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2119 /* stlink shares the examine handler but does not support
2121 if (!armv7m
->stlink
) {
2122 if (cortex_m
->apsel
== DP_APSEL_INVALID
) {
2123 /* Search for the MEM-AP */
2124 retval
= cortex_m_find_mem_ap(swjdp
, &armv7m
->debug_ap
);
2125 if (retval
!= ERROR_OK
) {
2126 LOG_ERROR("Could not find MEM-AP to control the core");
2130 armv7m
->debug_ap
= dap_ap(swjdp
, cortex_m
->apsel
);
2133 /* Leave (only) generic DAP stuff for debugport_init(); */
2134 armv7m
->debug_ap
->memaccess_tck
= 8;
2136 retval
= mem_ap_init(armv7m
->debug_ap
);
2137 if (retval
!= ERROR_OK
)
2141 if (!target_was_examined(target
)) {
2142 target_set_examined(target
);
2144 /* Read from Device Identification Registers */
2145 retval
= target_read_u32(target
, CPUID
, &cpuid
);
2146 if (retval
!= ERROR_OK
)
2150 i
= (cpuid
>> 4) & 0xf;
2152 switch (cpuid
& ARM_CPUID_PARTNO_MASK
) {
2153 case CORTEX_M23_PARTNO
:
2157 case CORTEX_M33_PARTNO
:
2166 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
2167 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
2168 cortex_m
->maskints_erratum
= false;
2171 rev
= (cpuid
>> 20) & 0xf;
2172 patch
= (cpuid
>> 0) & 0xf;
2173 if ((rev
== 0) && (patch
< 2)) {
2174 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2175 cortex_m
->maskints_erratum
= true;
2178 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
2180 /* VECTRESET is not supported on Cortex-M0, M0+ and M1 */
2181 cortex_m
->vectreset_supported
= i
> 1;
2184 target_read_u32(target
, MVFR0
, &mvfr0
);
2185 target_read_u32(target
, MVFR1
, &mvfr1
);
2187 /* test for floating point feature on Cortex-M4 */
2188 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
2189 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
2190 armv7m
->fp_feature
= FPv4_SP
;
2192 } else if (i
== 7 || i
== 33) {
2193 target_read_u32(target
, MVFR0
, &mvfr0
);
2194 target_read_u32(target
, MVFR1
, &mvfr1
);
2196 /* test for floating point features on Cortex-M7 */
2197 if ((mvfr0
== MVFR0_DEFAULT_M7_SP
) && (mvfr1
== MVFR1_DEFAULT_M7_SP
)) {
2198 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i
);
2199 armv7m
->fp_feature
= FPv5_SP
;
2200 } else if ((mvfr0
== MVFR0_DEFAULT_M7_DP
) && (mvfr1
== MVFR1_DEFAULT_M7_DP
)) {
2201 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i
);
2202 armv7m
->fp_feature
= FPv5_DP
;
2204 } else if (i
== 0) {
2205 /* Cortex-M0 does not support unaligned memory access */
2206 armv7m
->arm
.is_armv6m
= true;
2209 if (armv7m
->fp_feature
== FP_NONE
&&
2210 armv7m
->arm
.core_cache
->num_regs
> ARMV7M_NUM_CORE_REGS_NOFP
) {
2211 /* free unavailable FPU registers */
2214 for (idx
= ARMV7M_NUM_CORE_REGS_NOFP
;
2215 idx
< armv7m
->arm
.core_cache
->num_regs
;
2217 free(armv7m
->arm
.core_cache
->reg_list
[idx
].value
);
2218 free(armv7m
->arm
.core_cache
->reg_list
[idx
].feature
);
2219 free(armv7m
->arm
.core_cache
->reg_list
[idx
].reg_data_type
);
2221 armv7m
->arm
.core_cache
->num_regs
= ARMV7M_NUM_CORE_REGS_NOFP
;
2224 if (!armv7m
->stlink
) {
2225 if (i
== 3 || i
== 4)
2226 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2227 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2228 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 12);
2230 /* Cortex-M7 has only 1024 bytes autoincrement range */
2231 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 10);
2234 /* Configure trace modules */
2235 retval
= target_write_u32(target
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
2236 if (retval
!= ERROR_OK
)
2239 if (armv7m
->trace_config
.config_type
!= TRACE_CONFIG_TYPE_DISABLED
) {
2240 armv7m_trace_tpiu_config(target
);
2241 armv7m_trace_itm_config(target
);
2244 /* NOTE: FPB and DWT are both optional. */
2247 target_read_u32(target
, FP_CTRL
, &fpcr
);
2248 /* bits [14:12] and [7:4] */
2249 cortex_m
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF);
2250 cortex_m
->fp_num_lit
= (fpcr
>> 8) & 0xF;
2251 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2252 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2253 cortex_m
->fp_rev
= (fpcr
>> 28) & 0xf;
2254 free(cortex_m
->fp_comparator_list
);
2255 cortex_m
->fp_comparator_list
= calloc(
2256 cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
,
2257 sizeof(struct cortex_m_fp_comparator
));
2258 cortex_m
->fpb_enabled
= fpcr
& 1;
2259 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
2260 cortex_m
->fp_comparator_list
[i
].type
=
2261 (i
< cortex_m
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
2262 cortex_m
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
2264 /* make sure we clear any breakpoints enabled on the target */
2265 target_write_u32(target
, cortex_m
->fp_comparator_list
[i
].fpcr_address
, 0);
2267 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
2269 cortex_m
->fp_num_code
,
2270 cortex_m
->fp_num_lit
);
2273 cortex_m_dwt_free(target
);
2274 cortex_m_dwt_setup(cortex_m
, target
);
2276 /* These hardware breakpoints only work for code in flash! */
2277 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2278 target_name(target
),
2279 cortex_m
->fp_num_code
,
2280 cortex_m
->dwt_num_comp
);
2286 static int cortex_m_dcc_read(struct target
*target
, uint8_t *value
, uint8_t *ctrl
)
2288 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2293 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2294 if (retval
!= ERROR_OK
)
2297 dcrdr
= target_buffer_get_u16(target
, buf
);
2298 *ctrl
= (uint8_t)dcrdr
;
2299 *value
= (uint8_t)(dcrdr
>> 8);
2301 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
2303 /* write ack back to software dcc register
2304 * signify we have read data */
2305 if (dcrdr
& (1 << 0)) {
2306 target_buffer_set_u16(target
, buf
, 0);
2307 retval
= mem_ap_write_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2308 if (retval
!= ERROR_OK
)
2315 static int cortex_m_target_request_data(struct target
*target
,
2316 uint32_t size
, uint8_t *buffer
)
2322 for (i
= 0; i
< (size
* 4); i
++) {
2323 int retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2324 if (retval
!= ERROR_OK
)
2332 static int cortex_m_handle_target_request(void *priv
)
2334 struct target
*target
= priv
;
2335 if (!target_was_examined(target
))
2338 if (!target
->dbg_msg_enabled
)
2341 if (target
->state
== TARGET_RUNNING
) {
2346 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2347 if (retval
!= ERROR_OK
)
2350 /* check if we have data */
2351 if (ctrl
& (1 << 0)) {
2354 /* we assume target is quick enough */
2356 for (int i
= 1; i
<= 3; i
++) {
2357 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2358 if (retval
!= ERROR_OK
)
2360 request
|= ((uint32_t)data
<< (i
* 8));
2362 target_request(target
, request
);
2369 static int cortex_m_init_arch_info(struct target
*target
,
2370 struct cortex_m_common
*cortex_m
, struct adiv5_dap
*dap
)
2372 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2374 armv7m_init_arch_info(target
, armv7m
);
2376 /* default reset mode is to use srst if fitted
2377 * if not it will use CORTEX_M3_RESET_VECTRESET */
2378 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2380 armv7m
->arm
.dap
= dap
;
2382 /* register arch-specific functions */
2383 armv7m
->examine_debug_reason
= cortex_m_examine_debug_reason
;
2385 armv7m
->post_debug_entry
= NULL
;
2387 armv7m
->pre_restore_context
= NULL
;
2389 armv7m
->load_core_reg_u32
= cortex_m_load_core_reg_u32
;
2390 armv7m
->store_core_reg_u32
= cortex_m_store_core_reg_u32
;
2392 target_register_timer_callback(cortex_m_handle_target_request
, 1,
2393 TARGET_TIMER_TYPE_PERIODIC
, target
);
2398 static int cortex_m_target_create(struct target
*target
, Jim_Interp
*interp
)
2400 struct adiv5_private_config
*pc
;
2402 pc
= (struct adiv5_private_config
*)target
->private_config
;
2403 if (adiv5_verify_config(pc
) != ERROR_OK
)
2406 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
2407 if (cortex_m
== NULL
) {
2408 LOG_ERROR("No memory creating target");
2412 cortex_m
->common_magic
= CORTEX_M_COMMON_MAGIC
;
2413 cortex_m
->apsel
= pc
->ap_num
;
2415 cortex_m_init_arch_info(target
, cortex_m
, pc
->dap
);
2420 /*--------------------------------------------------------------------------*/
2422 static int cortex_m_verify_pointer(struct command_invocation
*cmd
,
2423 struct cortex_m_common
*cm
)
2425 if (cm
->common_magic
!= CORTEX_M_COMMON_MAGIC
) {
2426 command_print(cmd
, "target is not a Cortex-M");
2427 return ERROR_TARGET_INVALID
;
2433 * Only stuff below this line should need to verify that its target
2434 * is a Cortex-M3. Everything else should have indirected through the
2435 * cortexm3_target structure, which is only used with CM3 targets.
2438 COMMAND_HANDLER(handle_cortex_m_vector_catch_command
)
2440 struct target
*target
= get_current_target(CMD_CTX
);
2441 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2442 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2446 static const struct {
2450 { "hard_err", VC_HARDERR
, },
2451 { "int_err", VC_INTERR
, },
2452 { "bus_err", VC_BUSERR
, },
2453 { "state_err", VC_STATERR
, },
2454 { "chk_err", VC_CHKERR
, },
2455 { "nocp_err", VC_NOCPERR
, },
2456 { "mm_err", VC_MMERR
, },
2457 { "reset", VC_CORERESET
, },
2460 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2461 if (retval
!= ERROR_OK
)
2464 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2465 if (retval
!= ERROR_OK
)
2471 if (CMD_ARGC
== 1) {
2472 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2473 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2474 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2475 | VC_MMERR
| VC_CORERESET
;
2477 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2480 while (CMD_ARGC
-- > 0) {
2482 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2483 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2485 catch |= vec_ids
[i
].mask
;
2488 if (i
== ARRAY_SIZE(vec_ids
)) {
2489 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2490 return ERROR_COMMAND_SYNTAX_ERROR
;
2494 /* For now, armv7m->demcr only stores vector catch flags. */
2495 armv7m
->demcr
= catch;
2500 /* write, but don't assume it stuck (why not??) */
2501 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, demcr
);
2502 if (retval
!= ERROR_OK
)
2504 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2505 if (retval
!= ERROR_OK
)
2508 /* FIXME be sure to clear DEMCR on clean server shutdown.
2509 * Otherwise the vector catch hardware could fire when there's
2510 * no debugger hooked up, causing much confusion...
2514 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2515 command_print(CMD
, "%9s: %s", vec_ids
[i
].name
,
2516 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2522 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command
)
2524 struct target
*target
= get_current_target(CMD_CTX
);
2525 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2528 static const Jim_Nvp nvp_maskisr_modes
[] = {
2529 { .name
= "auto", .value
= CORTEX_M_ISRMASK_AUTO
},
2530 { .name
= "off", .value
= CORTEX_M_ISRMASK_OFF
},
2531 { .name
= "on", .value
= CORTEX_M_ISRMASK_ON
},
2532 { .name
= "steponly", .value
= CORTEX_M_ISRMASK_STEPONLY
},
2533 { .name
= NULL
, .value
= -1 },
2538 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2539 if (retval
!= ERROR_OK
)
2542 if (target
->state
!= TARGET_HALTED
) {
2543 command_print(CMD
, "target must be stopped for \"%s\" command", CMD_NAME
);
2548 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2549 if (n
->name
== NULL
)
2550 return ERROR_COMMAND_SYNTAX_ERROR
;
2551 cortex_m
->isrmasking_mode
= n
->value
;
2552 cortex_m_set_maskints_for_halt(target
);
2555 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m
->isrmasking_mode
);
2556 command_print(CMD
, "cortex_m interrupt mask %s", n
->name
);
2561 COMMAND_HANDLER(handle_cortex_m_reset_config_command
)
2563 struct target
*target
= get_current_target(CMD_CTX
);
2564 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2568 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2569 if (retval
!= ERROR_OK
)
2573 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2574 cortex_m
->soft_reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
2576 else if (strcmp(*CMD_ARGV
, "vectreset") == 0) {
2577 if (target_was_examined(target
)
2578 && !cortex_m
->vectreset_supported
)
2579 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2581 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2584 return ERROR_COMMAND_SYNTAX_ERROR
;
2587 switch (cortex_m
->soft_reset_config
) {
2588 case CORTEX_M_RESET_SYSRESETREQ
:
2589 reset_config
= "sysresetreq";
2592 case CORTEX_M_RESET_VECTRESET
:
2593 reset_config
= "vectreset";
2597 reset_config
= "unknown";
2601 command_print(CMD
, "cortex_m reset_config %s", reset_config
);
2606 static const struct command_registration cortex_m_exec_command_handlers
[] = {
2609 .handler
= handle_cortex_m_mask_interrupts_command
,
2610 .mode
= COMMAND_EXEC
,
2611 .help
= "mask cortex_m interrupts",
2612 .usage
= "['auto'|'on'|'off'|'steponly']",
2615 .name
= "vector_catch",
2616 .handler
= handle_cortex_m_vector_catch_command
,
2617 .mode
= COMMAND_EXEC
,
2618 .help
= "configure hardware vectors to trigger debug entry",
2619 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2622 .name
= "reset_config",
2623 .handler
= handle_cortex_m_reset_config_command
,
2624 .mode
= COMMAND_ANY
,
2625 .help
= "configure software reset handling",
2626 .usage
= "['sysresetreq'|'vectreset']",
2628 COMMAND_REGISTRATION_DONE
2630 static const struct command_registration cortex_m_command_handlers
[] = {
2632 .chain
= armv7m_command_handlers
,
2635 .chain
= armv7m_trace_command_handlers
,
2639 .mode
= COMMAND_EXEC
,
2640 .help
= "Cortex-M command group",
2642 .chain
= cortex_m_exec_command_handlers
,
2644 COMMAND_REGISTRATION_DONE
2647 struct target_type cortexm_target
= {
2649 .deprecated_name
= "cortex_m3",
2651 .poll
= cortex_m_poll
,
2652 .arch_state
= armv7m_arch_state
,
2654 .target_request_data
= cortex_m_target_request_data
,
2656 .halt
= cortex_m_halt
,
2657 .resume
= cortex_m_resume
,
2658 .step
= cortex_m_step
,
2660 .assert_reset
= cortex_m_assert_reset
,
2661 .deassert_reset
= cortex_m_deassert_reset
,
2662 .soft_reset_halt
= cortex_m_soft_reset_halt
,
2664 .get_gdb_arch
= arm_get_gdb_arch
,
2665 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2667 .read_memory
= cortex_m_read_memory
,
2668 .write_memory
= cortex_m_write_memory
,
2669 .checksum_memory
= armv7m_checksum_memory
,
2670 .blank_check_memory
= armv7m_blank_check_memory
,
2672 .run_algorithm
= armv7m_run_algorithm
,
2673 .start_algorithm
= armv7m_start_algorithm
,
2674 .wait_algorithm
= armv7m_wait_algorithm
,
2676 .add_breakpoint
= cortex_m_add_breakpoint
,
2677 .remove_breakpoint
= cortex_m_remove_breakpoint
,
2678 .add_watchpoint
= cortex_m_add_watchpoint
,
2679 .remove_watchpoint
= cortex_m_remove_watchpoint
,
2681 .commands
= cortex_m_command_handlers
,
2682 .target_create
= cortex_m_target_create
,
2683 .target_jim_configure
= adiv5_jim_configure
,
2684 .init_target
= cortex_m_init_target
,
2685 .examine
= cortex_m_examine
,
2686 .deinit_target
= cortex_m_deinit_target
,
2688 .profiling
= cortex_m_profiling
,
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