1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
25 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
27 ***************************************************************************/
32 #include "jtag/interface.h"
33 #include "breakpoints.h"
35 #include "target_request.h"
36 #include "target_type.h"
37 #include "arm_disassembler.h"
39 #include "arm_opcodes.h"
40 #include "arm_semihosting.h"
41 #include <helper/time_support.h>
44 /* NOTE: most of this should work fine for the Cortex-M1 and
45 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
46 * Some differences: M0/M1 doesn't have FPB remapping or the
47 * DWT tracing/profiling support. (So the cycle counter will
48 * not be usable; the other stuff isn't currently used here.)
50 * Although there are some workarounds for errata seen only in r0p0
51 * silicon, such old parts are hard to find and thus not much tested
55 /* forward declarations */
56 static int cortex_m_store_core_reg_u32(struct target
*target
,
57 uint32_t num
, uint32_t value
);
58 static void cortex_m_dwt_free(struct target
*target
);
60 static int cortex_m_load_core_reg_u32(struct target
*target
,
61 uint32_t regsel
, uint32_t *value
)
63 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
67 /* because the DCB_DCRDR is used for the emulated dcc channel
68 * we have to save/restore the DCB_DCRDR when used */
69 if (target
->dbg_msg_enabled
) {
70 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
71 if (retval
!= ERROR_OK
)
75 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regsel
);
76 if (retval
!= ERROR_OK
)
79 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
80 if (retval
!= ERROR_OK
)
83 if (target
->dbg_msg_enabled
) {
84 /* restore DCB_DCRDR - this needs to be in a separate
85 * transaction otherwise the emulated DCC channel breaks */
86 if (retval
== ERROR_OK
)
87 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
93 static int cortex_m_store_core_reg_u32(struct target
*target
,
94 uint32_t regsel
, uint32_t value
)
96 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
100 /* because the DCB_DCRDR is used for the emulated dcc channel
101 * we have to save/restore the DCB_DCRDR when used */
102 if (target
->dbg_msg_enabled
) {
103 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
104 if (retval
!= ERROR_OK
)
108 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
109 if (retval
!= ERROR_OK
)
112 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRSR
, regsel
| DCRSR_WnR
);
113 if (retval
!= ERROR_OK
)
116 if (target
->dbg_msg_enabled
) {
117 /* restore DCB_DCRDR - this needs to be in a separate
118 * transaction otherwise the emulated DCC channel breaks */
119 if (retval
== ERROR_OK
)
120 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
126 static int cortex_m_write_debug_halt_mask(struct target
*target
,
127 uint32_t mask_on
, uint32_t mask_off
)
129 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
130 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
132 /* mask off status bits */
133 cortex_m
->dcb_dhcsr
&= ~((0xFFFFul
<< 16) | mask_off
);
134 /* create new register mask */
135 cortex_m
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
137 return mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, cortex_m
->dcb_dhcsr
);
140 static int cortex_m_set_maskints(struct target
*target
, bool mask
)
142 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
143 if (!!(cortex_m
->dcb_dhcsr
& C_MASKINTS
) != mask
)
144 return cortex_m_write_debug_halt_mask(target
, mask
? C_MASKINTS
: 0, mask
? 0 : C_MASKINTS
);
149 static int cortex_m_set_maskints_for_halt(struct target
*target
)
151 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
152 switch (cortex_m
->isrmasking_mode
) {
153 case CORTEX_M_ISRMASK_AUTO
:
154 /* interrupts taken at resume, whether for step or run -> no mask */
155 return cortex_m_set_maskints(target
, false);
157 case CORTEX_M_ISRMASK_OFF
:
158 /* interrupts never masked */
159 return cortex_m_set_maskints(target
, false);
161 case CORTEX_M_ISRMASK_ON
:
162 /* interrupts always masked */
163 return cortex_m_set_maskints(target
, true);
165 case CORTEX_M_ISRMASK_STEPONLY
:
166 /* interrupts masked for single step only -> mask now if MASKINTS
167 * erratum, otherwise only mask before stepping */
168 return cortex_m_set_maskints(target
, cortex_m
->maskints_erratum
);
173 static int cortex_m_set_maskints_for_run(struct target
*target
)
175 switch (target_to_cm(target
)->isrmasking_mode
) {
176 case CORTEX_M_ISRMASK_AUTO
:
177 /* interrupts taken at resume, whether for step or run -> no mask */
178 return cortex_m_set_maskints(target
, false);
180 case CORTEX_M_ISRMASK_OFF
:
181 /* interrupts never masked */
182 return cortex_m_set_maskints(target
, false);
184 case CORTEX_M_ISRMASK_ON
:
185 /* interrupts always masked */
186 return cortex_m_set_maskints(target
, true);
188 case CORTEX_M_ISRMASK_STEPONLY
:
189 /* interrupts masked for single step only -> no mask */
190 return cortex_m_set_maskints(target
, false);
195 static int cortex_m_set_maskints_for_step(struct target
*target
)
197 switch (target_to_cm(target
)->isrmasking_mode
) {
198 case CORTEX_M_ISRMASK_AUTO
:
199 /* the auto-interrupt should already be done -> mask */
200 return cortex_m_set_maskints(target
, true);
202 case CORTEX_M_ISRMASK_OFF
:
203 /* interrupts never masked */
204 return cortex_m_set_maskints(target
, false);
206 case CORTEX_M_ISRMASK_ON
:
207 /* interrupts always masked */
208 return cortex_m_set_maskints(target
, true);
210 case CORTEX_M_ISRMASK_STEPONLY
:
211 /* interrupts masked for single step only -> mask */
212 return cortex_m_set_maskints(target
, true);
217 static int cortex_m_clear_halt(struct target
*target
)
219 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
220 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
223 /* clear step if any */
224 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
226 /* Read Debug Fault Status Register */
227 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, &cortex_m
->nvic_dfsr
);
228 if (retval
!= ERROR_OK
)
231 /* Clear Debug Fault Status */
232 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, cortex_m
->nvic_dfsr
);
233 if (retval
!= ERROR_OK
)
235 LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32
"", cortex_m
->nvic_dfsr
);
240 static int cortex_m_single_step_core(struct target
*target
)
242 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
243 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
246 /* Mask interrupts before clearing halt, if not done already. This avoids
247 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
248 * HALT can put the core into an unknown state.
250 if (!(cortex_m
->dcb_dhcsr
& C_MASKINTS
)) {
251 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
252 DBGKEY
| C_MASKINTS
| C_HALT
| C_DEBUGEN
);
253 if (retval
!= ERROR_OK
)
256 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
257 DBGKEY
| C_MASKINTS
| C_STEP
| C_DEBUGEN
);
258 if (retval
!= ERROR_OK
)
262 /* restore dhcsr reg */
263 cortex_m_clear_halt(target
);
268 static int cortex_m_enable_fpb(struct target
*target
)
270 int retval
= target_write_u32(target
, FP_CTRL
, 3);
271 if (retval
!= ERROR_OK
)
274 /* check the fpb is actually enabled */
276 retval
= target_read_u32(target
, FP_CTRL
, &fpctrl
);
277 if (retval
!= ERROR_OK
)
286 static int cortex_m_endreset_event(struct target
*target
)
291 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
292 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
293 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
294 struct cortex_m_fp_comparator
*fp_list
= cortex_m
->fp_comparator_list
;
295 struct cortex_m_dwt_comparator
*dwt_list
= cortex_m
->dwt_comparator_list
;
297 /* REVISIT The four debug monitor bits are currently ignored... */
298 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &dcb_demcr
);
299 if (retval
!= ERROR_OK
)
301 LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
303 /* this register is used for emulated dcc channel */
304 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
305 if (retval
!= ERROR_OK
)
308 /* Enable debug requests */
309 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
310 if (retval
!= ERROR_OK
)
312 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
313 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
314 if (retval
!= ERROR_OK
)
318 /* Restore proper interrupt masking setting for running CPU. */
319 cortex_m_set_maskints_for_run(target
);
321 /* Enable features controlled by ITM and DWT blocks, and catch only
322 * the vectors we were told to pay attention to.
324 * Target firmware is responsible for all fault handling policy
325 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
326 * or manual updates to the NVIC SHCSR and CCR registers.
328 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
329 if (retval
!= ERROR_OK
)
332 /* Paranoia: evidently some (early?) chips don't preserve all the
333 * debug state (including FPB, DWT, etc) across reset...
337 retval
= cortex_m_enable_fpb(target
);
338 if (retval
!= ERROR_OK
) {
339 LOG_ERROR("Failed to enable the FPB");
343 cortex_m
->fpb_enabled
= true;
345 /* Restore FPB registers */
346 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
347 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
348 if (retval
!= ERROR_OK
)
352 /* Restore DWT registers */
353 for (i
= 0; i
< cortex_m
->dwt_num_comp
; i
++) {
354 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
356 if (retval
!= ERROR_OK
)
358 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
360 if (retval
!= ERROR_OK
)
362 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
363 dwt_list
[i
].function
);
364 if (retval
!= ERROR_OK
)
367 retval
= dap_run(swjdp
);
368 if (retval
!= ERROR_OK
)
371 register_cache_invalidate(armv7m
->arm
.core_cache
);
373 /* make sure we have latest dhcsr flags */
374 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
379 static int cortex_m_examine_debug_reason(struct target
*target
)
381 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
383 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
384 * only check the debug reason if we don't know it already */
386 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
387 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
388 if (cortex_m
->nvic_dfsr
& DFSR_BKPT
) {
389 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
390 if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
391 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
392 } else if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
393 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
394 else if (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)
395 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
396 else if (cortex_m
->nvic_dfsr
& DFSR_EXTERNAL
)
397 target
->debug_reason
= DBG_REASON_DBGRQ
;
399 target
->debug_reason
= DBG_REASON_UNDEFINED
;
405 static int cortex_m_examine_exception_reason(struct target
*target
)
407 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
408 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
409 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
412 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SHCSR
, &shcsr
);
413 if (retval
!= ERROR_OK
)
415 switch (armv7m
->exception_number
) {
418 case 3: /* Hard Fault */
419 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_HFSR
, &except_sr
);
420 if (retval
!= ERROR_OK
)
422 if (except_sr
& 0x40000000) {
423 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &cfsr
);
424 if (retval
!= ERROR_OK
)
428 case 4: /* Memory Management */
429 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
430 if (retval
!= ERROR_OK
)
432 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_MMFAR
, &except_ar
);
433 if (retval
!= ERROR_OK
)
436 case 5: /* Bus Fault */
437 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
438 if (retval
!= ERROR_OK
)
440 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_BFAR
, &except_ar
);
441 if (retval
!= ERROR_OK
)
444 case 6: /* Usage Fault */
445 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
446 if (retval
!= ERROR_OK
)
449 case 7: /* Secure Fault */
450 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SFSR
, &except_sr
);
451 if (retval
!= ERROR_OK
)
453 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SFAR
, &except_ar
);
454 if (retval
!= ERROR_OK
)
457 case 11: /* SVCall */
459 case 12: /* Debug Monitor */
460 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_DFSR
, &except_sr
);
461 if (retval
!= ERROR_OK
)
464 case 14: /* PendSV */
466 case 15: /* SysTick */
472 retval
= dap_run(swjdp
);
473 if (retval
== ERROR_OK
)
474 LOG_DEBUG("%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
475 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
476 armv7m_exception_string(armv7m
->exception_number
),
477 shcsr
, except_sr
, cfsr
, except_ar
);
481 static int cortex_m_debug_entry(struct target
*target
)
486 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
487 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
488 struct arm
*arm
= &armv7m
->arm
;
493 /* Do this really early to minimize the window where the MASKINTS erratum
494 * can pile up pending interrupts. */
495 cortex_m_set_maskints_for_halt(target
);
497 cortex_m_clear_halt(target
);
498 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
499 if (retval
!= ERROR_OK
)
502 retval
= armv7m
->examine_debug_reason(target
);
503 if (retval
!= ERROR_OK
)
506 /* examine PE security state */
507 bool secure_state
= false;
508 if (armv7m
->arm
.is_armv8m
) {
511 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DSCSR
, &dscsr
);
512 if (retval
!= ERROR_OK
)
515 secure_state
= (dscsr
& DSCSR_CDS
) == DSCSR_CDS
;
518 /* Examine target state and mode
519 * First load register accessible through core debug port */
520 int num_regs
= arm
->core_cache
->num_regs
;
522 for (i
= 0; i
< num_regs
; i
++) {
523 r
= &armv7m
->arm
.core_cache
->reg_list
[i
];
525 arm
->read_core_reg(target
, r
, i
, ARM_MODE_ANY
);
529 xPSR
= buf_get_u32(r
->value
, 0, 32);
531 /* Are we in an exception handler */
533 armv7m
->exception_number
= (xPSR
& 0x1FF);
535 arm
->core_mode
= ARM_MODE_HANDLER
;
536 arm
->map
= armv7m_msp_reg_map
;
538 unsigned control
= buf_get_u32(arm
->core_cache
539 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 3);
541 /* is this thread privileged? */
542 arm
->core_mode
= control
& 1
543 ? ARM_MODE_USER_THREAD
546 /* which stack is it using? */
548 arm
->map
= armv7m_psp_reg_map
;
550 arm
->map
= armv7m_msp_reg_map
;
552 armv7m
->exception_number
= 0;
555 if (armv7m
->exception_number
)
556 cortex_m_examine_exception_reason(target
);
558 LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32
", cpu in %s state, target->state: %s",
559 arm_mode_name(arm
->core_mode
),
560 buf_get_u32(arm
->pc
->value
, 0, 32),
561 secure_state
? "Secure" : "Non-Secure",
562 target_state_name(target
));
564 if (armv7m
->post_debug_entry
) {
565 retval
= armv7m
->post_debug_entry(target
);
566 if (retval
!= ERROR_OK
)
573 static int cortex_m_poll(struct target
*target
)
575 int detected_failure
= ERROR_OK
;
576 int retval
= ERROR_OK
;
577 enum target_state prev_target_state
= target
->state
;
578 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
579 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
581 /* Read from Debug Halting Control and Status Register */
582 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
583 if (retval
!= ERROR_OK
) {
584 target
->state
= TARGET_UNKNOWN
;
588 /* Recover from lockup. See ARMv7-M architecture spec,
589 * section B1.5.15 "Unrecoverable exception cases".
591 if (cortex_m
->dcb_dhcsr
& S_LOCKUP
) {
592 LOG_ERROR("%s -- clearing lockup after double fault",
593 target_name(target
));
594 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
595 target
->debug_reason
= DBG_REASON_DBGRQ
;
597 /* We have to execute the rest (the "finally" equivalent, but
598 * still throw this exception again).
600 detected_failure
= ERROR_FAIL
;
602 /* refresh status bits */
603 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
604 if (retval
!= ERROR_OK
)
608 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
609 if (target
->state
!= TARGET_RESET
) {
610 target
->state
= TARGET_RESET
;
611 LOG_INFO("%s: external reset detected", target_name(target
));
616 if (target
->state
== TARGET_RESET
) {
617 /* Cannot switch context while running so endreset is
618 * called with target->state == TARGET_RESET
620 LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32
,
621 cortex_m
->dcb_dhcsr
);
622 retval
= cortex_m_endreset_event(target
);
623 if (retval
!= ERROR_OK
) {
624 target
->state
= TARGET_UNKNOWN
;
627 target
->state
= TARGET_RUNNING
;
628 prev_target_state
= TARGET_RUNNING
;
631 if (cortex_m
->dcb_dhcsr
& S_HALT
) {
632 target
->state
= TARGET_HALTED
;
634 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
635 retval
= cortex_m_debug_entry(target
);
636 if (retval
!= ERROR_OK
)
639 if (arm_semihosting(target
, &retval
) != 0)
642 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
644 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
646 retval
= cortex_m_debug_entry(target
);
647 if (retval
!= ERROR_OK
)
650 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
654 if (target
->state
== TARGET_UNKNOWN
) {
655 /* check if processor is retiring instructions or sleeping */
656 if (cortex_m
->dcb_dhcsr
& S_RETIRE_ST
|| cortex_m
->dcb_dhcsr
& S_SLEEP
) {
657 target
->state
= TARGET_RUNNING
;
662 /* Check that target is truly halted, since the target could be resumed externally */
663 if ((prev_target_state
== TARGET_HALTED
) && !(cortex_m
->dcb_dhcsr
& S_HALT
)) {
664 /* registers are now invalid */
665 register_cache_invalidate(armv7m
->arm
.core_cache
);
667 target
->state
= TARGET_RUNNING
;
668 LOG_WARNING("%s: external resume detected", target_name(target
));
669 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
673 /* Did we detect a failure condition that we cleared? */
674 if (detected_failure
!= ERROR_OK
)
675 retval
= detected_failure
;
679 static int cortex_m_halt(struct target
*target
)
681 LOG_DEBUG("target->state: %s",
682 target_state_name(target
));
684 if (target
->state
== TARGET_HALTED
) {
685 LOG_DEBUG("target was already halted");
689 if (target
->state
== TARGET_UNKNOWN
)
690 LOG_WARNING("target was in unknown state when halt was requested");
692 if (target
->state
== TARGET_RESET
) {
693 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
694 LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
695 return ERROR_TARGET_FAILURE
;
697 /* we came here in a reset_halt or reset_init sequence
698 * debug entry was already prepared in cortex_m3_assert_reset()
700 target
->debug_reason
= DBG_REASON_DBGRQ
;
706 /* Write to Debug Halting Control and Status Register */
707 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
709 /* Do this really early to minimize the window where the MASKINTS erratum
710 * can pile up pending interrupts. */
711 cortex_m_set_maskints_for_halt(target
);
713 target
->debug_reason
= DBG_REASON_DBGRQ
;
718 static int cortex_m_soft_reset_halt(struct target
*target
)
720 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
721 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
722 uint32_t dcb_dhcsr
= 0;
723 int retval
, timeout
= 0;
725 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
726 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
727 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
728 * core, not the peripherals */
729 LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
732 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_STEP
| C_MASKINTS
);
733 if (retval
!= ERROR_OK
)
736 /* Enter debug state on reset; restore DEMCR in endreset_event() */
737 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
,
738 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
739 if (retval
!= ERROR_OK
)
742 /* Request a core-only reset */
743 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
744 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
745 if (retval
!= ERROR_OK
)
747 target
->state
= TARGET_RESET
;
749 /* registers are now invalid */
750 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
752 while (timeout
< 100) {
753 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &dcb_dhcsr
);
754 if (retval
== ERROR_OK
) {
755 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
,
756 &cortex_m
->nvic_dfsr
);
757 if (retval
!= ERROR_OK
)
759 if ((dcb_dhcsr
& S_HALT
)
760 && (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)) {
761 LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
763 (unsigned) dcb_dhcsr
,
764 (unsigned) cortex_m
->nvic_dfsr
);
765 cortex_m_poll(target
);
766 /* FIXME restore user's vector catch config */
769 LOG_DEBUG("waiting for system reset-halt, "
770 "DHCSR 0x%08x, %d ms",
771 (unsigned) dcb_dhcsr
, timeout
);
780 void cortex_m_enable_breakpoints(struct target
*target
)
782 struct breakpoint
*breakpoint
= target
->breakpoints
;
784 /* set any pending breakpoints */
786 if (!breakpoint
->set
)
787 cortex_m_set_breakpoint(target
, breakpoint
);
788 breakpoint
= breakpoint
->next
;
792 static int cortex_m_resume(struct target
*target
, int current
,
793 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
795 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
796 struct breakpoint
*breakpoint
= NULL
;
800 if (target
->state
!= TARGET_HALTED
) {
801 LOG_WARNING("target not halted");
802 return ERROR_TARGET_NOT_HALTED
;
805 if (!debug_execution
) {
806 target_free_all_working_areas(target
);
807 cortex_m_enable_breakpoints(target
);
808 cortex_m_enable_watchpoints(target
);
811 if (debug_execution
) {
812 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
814 /* Disable interrupts */
815 /* We disable interrupts in the PRIMASK register instead of
816 * masking with C_MASKINTS. This is probably the same issue
817 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
818 * in parallel with disabled interrupts can cause local faults
821 * This breaks non-debug (application) execution if not
822 * called from armv7m_start_algorithm() which saves registers.
824 buf_set_u32(r
->value
, 0, 1, 1);
828 /* Make sure we are in Thumb mode, set xPSR.T bit */
829 /* armv7m_start_algorithm() initializes entire xPSR register.
830 * This duplicity handles the case when cortex_m_resume()
831 * is used with the debug_execution flag directly,
832 * not called through armv7m_start_algorithm().
834 r
= armv7m
->arm
.cpsr
;
835 buf_set_u32(r
->value
, 24, 1, 1);
840 /* current = 1: continue on current pc, otherwise continue at <address> */
843 buf_set_u32(r
->value
, 0, 32, address
);
848 /* if we halted last time due to a bkpt instruction
849 * then we have to manually step over it, otherwise
850 * the core will break again */
852 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
854 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
856 resume_pc
= buf_get_u32(r
->value
, 0, 32);
858 armv7m_restore_context(target
);
860 /* the front-end may request us not to handle breakpoints */
861 if (handle_breakpoints
) {
862 /* Single step past breakpoint at current address */
863 breakpoint
= breakpoint_find(target
, resume_pc
);
865 LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT
" (ID: %" PRIu32
")",
867 breakpoint
->unique_id
);
868 cortex_m_unset_breakpoint(target
, breakpoint
);
869 cortex_m_single_step_core(target
);
870 cortex_m_set_breakpoint(target
, breakpoint
);
875 cortex_m_set_maskints_for_run(target
);
876 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
878 target
->debug_reason
= DBG_REASON_NOTHALTED
;
880 /* registers are now invalid */
881 register_cache_invalidate(armv7m
->arm
.core_cache
);
883 if (!debug_execution
) {
884 target
->state
= TARGET_RUNNING
;
885 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
886 LOG_DEBUG("target resumed at 0x%" PRIx32
"", resume_pc
);
888 target
->state
= TARGET_DEBUG_RUNNING
;
889 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
890 LOG_DEBUG("target debug resumed at 0x%" PRIx32
"", resume_pc
);
896 /* int irqstepcount = 0; */
897 static int cortex_m_step(struct target
*target
, int current
,
898 target_addr_t address
, int handle_breakpoints
)
900 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
901 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
902 struct breakpoint
*breakpoint
= NULL
;
903 struct reg
*pc
= armv7m
->arm
.pc
;
904 bool bkpt_inst_found
= false;
906 bool isr_timed_out
= false;
908 if (target
->state
!= TARGET_HALTED
) {
909 LOG_WARNING("target not halted");
910 return ERROR_TARGET_NOT_HALTED
;
913 /* current = 1: continue on current pc, otherwise continue at <address> */
915 buf_set_u32(pc
->value
, 0, 32, address
);
917 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
919 /* the front-end may request us not to handle breakpoints */
920 if (handle_breakpoints
) {
921 breakpoint
= breakpoint_find(target
, pc_value
);
923 cortex_m_unset_breakpoint(target
, breakpoint
);
926 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
928 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
930 armv7m_restore_context(target
);
932 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
934 /* if no bkpt instruction is found at pc then we can perform
935 * a normal step, otherwise we have to manually step over the bkpt
936 * instruction - as such simulate a step */
937 if (bkpt_inst_found
== false) {
938 if (cortex_m
->isrmasking_mode
!= CORTEX_M_ISRMASK_AUTO
) {
939 /* Automatic ISR masking mode off: Just step over the next
940 * instruction, with interrupts on or off as appropriate. */
941 cortex_m_set_maskints_for_step(target
);
942 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
944 /* Process interrupts during stepping in a way they don't interfere
949 * Set a temporary break point at the current pc and let the core run
950 * with interrupts enabled. Pending interrupts get served and we run
951 * into the breakpoint again afterwards. Then we step over the next
952 * instruction with interrupts disabled.
954 * If the pending interrupts don't complete within time, we leave the
955 * core running. This may happen if the interrupts trigger faster
956 * than the core can process them or the handler doesn't return.
958 * If no more breakpoints are available we simply do a step with
959 * interrupts enabled.
965 * If a break point is already set on the lower half word then a break point on
966 * the upper half word will not break again when the core is restarted. So we
967 * just step over the instruction with interrupts disabled.
969 * The documentation has no information about this, it was found by observation
970 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
971 * suffer from this problem.
973 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
974 * address has it always cleared. The former is done to indicate thumb mode
978 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
979 LOG_DEBUG("Stepping over next instruction with interrupts disabled");
980 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
981 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
982 /* Re-enable interrupts if appropriate */
983 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
984 cortex_m_set_maskints_for_halt(target
);
987 /* Set a temporary break point */
989 retval
= cortex_m_set_breakpoint(target
, breakpoint
);
991 enum breakpoint_type type
= BKPT_HARD
;
992 if (cortex_m
->fp_rev
== 0 && pc_value
> 0x1FFFFFFF) {
993 /* FPB rev.1 cannot handle such addr, try BKPT instr */
996 retval
= breakpoint_add(target
, pc_value
, 2, type
);
999 bool tmp_bp_set
= (retval
== ERROR_OK
);
1001 /* No more breakpoints left, just do a step */
1003 cortex_m_set_maskints_for_step(target
);
1004 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1005 /* Re-enable interrupts if appropriate */
1006 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1007 cortex_m_set_maskints_for_halt(target
);
1009 /* Start the core */
1010 LOG_DEBUG("Starting core to serve pending interrupts");
1011 int64_t t_start
= timeval_ms();
1012 cortex_m_set_maskints_for_run(target
);
1013 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
1015 /* Wait for pending handlers to complete or timeout */
1017 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
,
1019 &cortex_m
->dcb_dhcsr
);
1020 if (retval
!= ERROR_OK
) {
1021 target
->state
= TARGET_UNKNOWN
;
1024 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
1025 } while (!((cortex_m
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
1027 /* only remove breakpoint if we created it */
1029 cortex_m_unset_breakpoint(target
, breakpoint
);
1031 /* Remove the temporary breakpoint */
1032 breakpoint_remove(target
, pc_value
);
1035 if (isr_timed_out
) {
1036 LOG_DEBUG("Interrupt handlers didn't complete within time, "
1037 "leaving target running");
1039 /* Step over next instruction with interrupts disabled */
1040 cortex_m_set_maskints_for_step(target
);
1041 cortex_m_write_debug_halt_mask(target
,
1042 C_HALT
| C_MASKINTS
,
1044 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1045 /* Re-enable interrupts if appropriate */
1046 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1047 cortex_m_set_maskints_for_halt(target
);
1054 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1055 if (retval
!= ERROR_OK
)
1058 /* registers are now invalid */
1059 register_cache_invalidate(armv7m
->arm
.core_cache
);
1062 cortex_m_set_breakpoint(target
, breakpoint
);
1064 if (isr_timed_out
) {
1065 /* Leave the core running. The user has to stop execution manually. */
1066 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1067 target
->state
= TARGET_RUNNING
;
1071 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1072 " nvic_icsr = 0x%" PRIx32
,
1073 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1075 retval
= cortex_m_debug_entry(target
);
1076 if (retval
!= ERROR_OK
)
1078 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1080 LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
1081 " nvic_icsr = 0x%" PRIx32
,
1082 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1087 static int cortex_m_assert_reset(struct target
*target
)
1089 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1090 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1091 enum cortex_m_soft_reset_config reset_config
= cortex_m
->soft_reset_config
;
1093 LOG_DEBUG("target->state: %s",
1094 target_state_name(target
));
1096 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1098 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
1099 /* allow scripts to override the reset event */
1101 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1102 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1103 target
->state
= TARGET_RESET
;
1108 /* some cores support connecting while srst is asserted
1109 * use that mode is it has been configured */
1111 bool srst_asserted
= false;
1113 if (!target_was_examined(target
)) {
1114 if (jtag_reset_config
& RESET_HAS_SRST
) {
1115 adapter_assert_reset();
1116 if (target
->reset_halt
)
1117 LOG_ERROR("Target not examined, will not halt after reset!");
1120 LOG_ERROR("Target not examined, reset NOT asserted!");
1125 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1126 (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1127 adapter_assert_reset();
1128 srst_asserted
= true;
1131 /* Enable debug requests */
1133 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
1134 /* Store important errors instead of failing and proceed to reset assert */
1136 if (retval
!= ERROR_OK
|| !(cortex_m
->dcb_dhcsr
& C_DEBUGEN
))
1137 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
1139 /* If the processor is sleeping in a WFI or WFE instruction, the
1140 * C_HALT bit must be asserted to regain control */
1141 if (retval
== ERROR_OK
&& (cortex_m
->dcb_dhcsr
& S_SLEEP
))
1142 retval
= cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1144 mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
1145 /* Ignore less important errors */
1147 if (!target
->reset_halt
) {
1148 /* Set/Clear C_MASKINTS in a separate operation */
1149 cortex_m_set_maskints_for_run(target
);
1151 /* clear any debug flags before resuming */
1152 cortex_m_clear_halt(target
);
1154 /* clear C_HALT in dhcsr reg */
1155 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1157 /* Halt in debug on reset; endreset_event() restores DEMCR.
1159 * REVISIT catching BUSERR presumably helps to defend against
1160 * bad vector table entries. Should this include MMERR or
1164 retval2
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
,
1165 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1166 if (retval
!= ERROR_OK
|| retval2
!= ERROR_OK
)
1167 LOG_INFO("AP write error, reset will not halt");
1170 if (jtag_reset_config
& RESET_HAS_SRST
) {
1171 /* default to asserting srst */
1173 adapter_assert_reset();
1175 /* srst is asserted, ignore AP access errors */
1178 /* Use a standard Cortex-M3 software reset mechanism.
1179 * We default to using VECRESET as it is supported on all current cores
1180 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1181 * This has the disadvantage of not resetting the peripherals, so a
1182 * reset-init event handler is needed to perform any peripheral resets.
1184 if (!cortex_m
->vectreset_supported
1185 && reset_config
== CORTEX_M_RESET_VECTRESET
) {
1186 reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
1187 LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1188 LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
1191 LOG_DEBUG("Using Cortex-M %s", (reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1192 ? "SYSRESETREQ" : "VECTRESET");
1194 if (reset_config
== CORTEX_M_RESET_VECTRESET
) {
1195 LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
1196 "handler to reset any peripherals or configure hardware srst support.");
1200 retval3
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
1201 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1202 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1203 if (retval3
!= ERROR_OK
)
1204 LOG_DEBUG("Ignoring AP write error right after reset");
1206 retval3
= dap_dp_init_or_reconnect(armv7m
->debug_ap
->dap
);
1207 if (retval3
!= ERROR_OK
) {
1208 LOG_ERROR("DP initialisation failed");
1209 /* The error return value must not be propagated in this case.
1210 * SYSRESETREQ or VECTRESET have been possibly triggered
1211 * so reset processing should continue */
1213 /* I do not know why this is necessary, but it
1214 * fixes strange effects (step/resume cause NMI
1215 * after reset) on LM3S6918 -- Michael Schwingen
1218 mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
, &tmp
);
1222 target
->state
= TARGET_RESET
;
1225 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1227 /* now return stored error code if any */
1228 if (retval
!= ERROR_OK
)
1231 if (target
->reset_halt
) {
1232 retval
= target_halt(target
);
1233 if (retval
!= ERROR_OK
)
1240 static int cortex_m_deassert_reset(struct target
*target
)
1242 struct armv7m_common
*armv7m
= &target_to_cm(target
)->armv7m
;
1244 LOG_DEBUG("target->state: %s",
1245 target_state_name(target
));
1247 /* deassert reset lines */
1248 adapter_deassert_reset();
1250 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1252 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1253 !(jtag_reset_config
& RESET_SRST_NO_GATING
) &&
1254 target_was_examined(target
)) {
1256 int retval
= dap_dp_init_or_reconnect(armv7m
->debug_ap
->dap
);
1257 if (retval
!= ERROR_OK
) {
1258 LOG_ERROR("DP initialisation failed");
1266 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1270 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1271 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1273 if (breakpoint
->set
) {
1274 LOG_WARNING("breakpoint (BPID: %" PRIu32
") already set", breakpoint
->unique_id
);
1278 if (breakpoint
->type
== BKPT_HARD
) {
1279 uint32_t fpcr_value
;
1280 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m
->fp_num_code
))
1282 if (fp_num
>= cortex_m
->fp_num_code
) {
1283 LOG_ERROR("Can not find free FPB Comparator!");
1284 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1286 breakpoint
->set
= fp_num
+ 1;
1287 fpcr_value
= breakpoint
->address
| 1;
1288 if (cortex_m
->fp_rev
== 0) {
1289 if (breakpoint
->address
> 0x1FFFFFFF) {
1290 LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
1294 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1295 fpcr_value
= (fpcr_value
& 0x1FFFFFFC) | hilo
| 1;
1296 } else if (cortex_m
->fp_rev
> 1) {
1297 LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1300 comparator_list
[fp_num
].used
= true;
1301 comparator_list
[fp_num
].fpcr_value
= fpcr_value
;
1302 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1303 comparator_list
[fp_num
].fpcr_value
);
1304 LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32
"",
1306 comparator_list
[fp_num
].fpcr_value
);
1307 if (!cortex_m
->fpb_enabled
) {
1308 LOG_DEBUG("FPB wasn't enabled, do it now");
1309 retval
= cortex_m_enable_fpb(target
);
1310 if (retval
!= ERROR_OK
) {
1311 LOG_ERROR("Failed to enable the FPB");
1315 cortex_m
->fpb_enabled
= true;
1317 } else if (breakpoint
->type
== BKPT_SOFT
) {
1320 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1321 * semihosting; don't use that. Otherwise the BKPT
1322 * parameter is arbitrary.
1324 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1325 retval
= target_read_memory(target
,
1326 breakpoint
->address
& 0xFFFFFFFE,
1327 breakpoint
->length
, 1,
1328 breakpoint
->orig_instr
);
1329 if (retval
!= ERROR_OK
)
1331 retval
= target_write_memory(target
,
1332 breakpoint
->address
& 0xFFFFFFFE,
1333 breakpoint
->length
, 1,
1335 if (retval
!= ERROR_OK
)
1337 breakpoint
->set
= true;
1340 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1341 breakpoint
->unique_id
,
1342 (int)(breakpoint
->type
),
1343 breakpoint
->address
,
1350 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1353 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1354 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1356 if (!breakpoint
->set
) {
1357 LOG_WARNING("breakpoint not set");
1361 LOG_DEBUG("BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (set=%d)",
1362 breakpoint
->unique_id
,
1363 (int)(breakpoint
->type
),
1364 breakpoint
->address
,
1368 if (breakpoint
->type
== BKPT_HARD
) {
1369 int fp_num
= breakpoint
->set
- 1;
1370 if ((fp_num
< 0) || (fp_num
>= cortex_m
->fp_num_code
)) {
1371 LOG_DEBUG("Invalid FP Comparator number in breakpoint");
1374 comparator_list
[fp_num
].used
= false;
1375 comparator_list
[fp_num
].fpcr_value
= 0;
1376 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1377 comparator_list
[fp_num
].fpcr_value
);
1379 /* restore original instruction (kept in target endianness) */
1380 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE,
1381 breakpoint
->length
, 1,
1382 breakpoint
->orig_instr
);
1383 if (retval
!= ERROR_OK
)
1386 breakpoint
->set
= false;
1391 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1393 if (breakpoint
->length
== 3) {
1394 LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
1395 breakpoint
->length
= 2;
1398 if ((breakpoint
->length
!= 2)) {
1399 LOG_INFO("only breakpoints of two bytes length supported");
1400 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1403 return cortex_m_set_breakpoint(target
, breakpoint
);
1406 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1408 if (!breakpoint
->set
)
1411 return cortex_m_unset_breakpoint(target
, breakpoint
);
1414 static int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1417 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1419 /* REVISIT Don't fully trust these "not used" records ... users
1420 * may set up breakpoints by hand, e.g. dual-address data value
1421 * watchpoint using comparator #1; comparator #0 matching cycle
1422 * count; send data trace info through ITM and TPIU; etc
1424 struct cortex_m_dwt_comparator
*comparator
;
1426 for (comparator
= cortex_m
->dwt_comparator_list
;
1427 comparator
->used
&& dwt_num
< cortex_m
->dwt_num_comp
;
1428 comparator
++, dwt_num
++)
1430 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
1431 LOG_ERROR("Can not find free DWT Comparator");
1434 comparator
->used
= true;
1435 watchpoint
->set
= dwt_num
+ 1;
1437 comparator
->comp
= watchpoint
->address
;
1438 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1441 if ((cortex_m
->dwt_devarch
& 0x1FFFFF) != DWT_DEVARCH_ARMV8M
) {
1442 uint32_t mask
= 0, temp
;
1444 /* watchpoint params were validated earlier */
1445 temp
= watchpoint
->length
;
1452 comparator
->mask
= mask
;
1453 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1456 switch (watchpoint
->rw
) {
1458 comparator
->function
= 5;
1461 comparator
->function
= 6;
1464 comparator
->function
= 7;
1468 uint32_t data_size
= watchpoint
->length
>> 1;
1469 comparator
->mask
= (watchpoint
->length
>> 1) | 1;
1471 switch (watchpoint
->rw
) {
1473 comparator
->function
= 4;
1476 comparator
->function
= 5;
1479 comparator
->function
= 6;
1482 comparator
->function
= comparator
->function
| (1 << 4) |
1486 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1487 comparator
->function
);
1489 LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
1490 watchpoint
->unique_id
, dwt_num
,
1491 (unsigned) comparator
->comp
,
1492 (unsigned) comparator
->mask
,
1493 (unsigned) comparator
->function
);
1497 static int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1499 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1500 struct cortex_m_dwt_comparator
*comparator
;
1503 if (!watchpoint
->set
) {
1504 LOG_WARNING("watchpoint (wpid: %d) not set",
1505 watchpoint
->unique_id
);
1509 dwt_num
= watchpoint
->set
- 1;
1511 LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
1512 watchpoint
->unique_id
, dwt_num
,
1513 (unsigned) watchpoint
->address
);
1515 if ((dwt_num
< 0) || (dwt_num
>= cortex_m
->dwt_num_comp
)) {
1516 LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
1520 comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
1521 comparator
->used
= false;
1522 comparator
->function
= 0;
1523 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1524 comparator
->function
);
1526 watchpoint
->set
= false;
1531 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1533 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1535 if (cortex_m
->dwt_comp_available
< 1) {
1536 LOG_DEBUG("no comparators?");
1537 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1540 /* hardware doesn't support data value masking */
1541 if (watchpoint
->mask
!= ~(uint32_t)0) {
1542 LOG_DEBUG("watchpoint value masks not supported");
1543 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1546 /* hardware allows address masks of up to 32K */
1549 for (mask
= 0; mask
< 16; mask
++) {
1550 if ((1u << mask
) == watchpoint
->length
)
1554 LOG_DEBUG("unsupported watchpoint length");
1555 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1557 if (watchpoint
->address
& ((1 << mask
) - 1)) {
1558 LOG_DEBUG("watchpoint address is unaligned");
1559 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1562 /* Caller doesn't seem to be able to describe watching for data
1563 * values of zero; that flags "no value".
1565 * REVISIT This DWT may well be able to watch for specific data
1566 * values. Requires comparator #1 to set DATAVMATCH and match
1567 * the data, and another comparator (DATAVADDR0) matching addr.
1569 if (watchpoint
->value
) {
1570 LOG_DEBUG("data value watchpoint not YET supported");
1571 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1574 cortex_m
->dwt_comp_available
--;
1575 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1580 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1582 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1584 /* REVISIT why check? DWT can be updated with core running ... */
1585 if (target
->state
!= TARGET_HALTED
) {
1586 LOG_WARNING("target not halted");
1587 return ERROR_TARGET_NOT_HALTED
;
1590 if (watchpoint
->set
)
1591 cortex_m_unset_watchpoint(target
, watchpoint
);
1593 cortex_m
->dwt_comp_available
++;
1594 LOG_DEBUG("dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
1599 void cortex_m_enable_watchpoints(struct target
*target
)
1601 struct watchpoint
*watchpoint
= target
->watchpoints
;
1603 /* set any pending watchpoints */
1604 while (watchpoint
) {
1605 if (!watchpoint
->set
)
1606 cortex_m_set_watchpoint(target
, watchpoint
);
1607 watchpoint
= watchpoint
->next
;
1611 static int cortex_m_read_memory(struct target
*target
, target_addr_t address
,
1612 uint32_t size
, uint32_t count
, uint8_t *buffer
)
1614 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1616 if (armv7m
->arm
.is_armv6m
) {
1617 /* armv6m does not handle unaligned memory access */
1618 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1619 return ERROR_TARGET_UNALIGNED_ACCESS
;
1622 return mem_ap_read_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1625 static int cortex_m_write_memory(struct target
*target
, target_addr_t address
,
1626 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
1628 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1630 if (armv7m
->arm
.is_armv6m
) {
1631 /* armv6m does not handle unaligned memory access */
1632 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
1633 return ERROR_TARGET_UNALIGNED_ACCESS
;
1636 return mem_ap_write_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
1639 static int cortex_m_init_target(struct command_context
*cmd_ctx
,
1640 struct target
*target
)
1642 armv7m_build_reg_cache(target
);
1643 arm_semihosting_init(target
);
1647 void cortex_m_deinit_target(struct target
*target
)
1649 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1651 armv7m_trace_tpiu_exit(target
);
1653 free(cortex_m
->fp_comparator_list
);
1655 cortex_m_dwt_free(target
);
1656 armv7m_free_reg_cache(target
);
1658 free(target
->private_config
);
1662 int cortex_m_profiling(struct target
*target
, uint32_t *samples
,
1663 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
)
1665 struct timeval timeout
, now
;
1666 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1670 retval
= target_read_u32(target
, DWT_PCSR
, ®_value
);
1671 if (retval
!= ERROR_OK
) {
1672 LOG_ERROR("Error while reading PCSR");
1675 if (reg_value
== 0) {
1676 LOG_INFO("PCSR sampling not supported on this processor.");
1677 return target_profiling_default(target
, samples
, max_num_samples
, num_samples
, seconds
);
1680 gettimeofday(&timeout
, NULL
);
1681 timeval_add_time(&timeout
, seconds
, 0);
1683 LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
1685 /* Make sure the target is running */
1686 target_poll(target
);
1687 if (target
->state
== TARGET_HALTED
)
1688 retval
= target_resume(target
, 1, 0, 0, 0);
1690 if (retval
!= ERROR_OK
) {
1691 LOG_ERROR("Error while resuming target");
1695 uint32_t sample_count
= 0;
1698 if (armv7m
&& armv7m
->debug_ap
) {
1699 uint32_t read_count
= max_num_samples
- sample_count
;
1700 if (read_count
> 1024)
1703 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
,
1704 (void *)&samples
[sample_count
],
1705 4, read_count
, DWT_PCSR
);
1706 sample_count
+= read_count
;
1708 target_read_u32(target
, DWT_PCSR
, &samples
[sample_count
++]);
1711 if (retval
!= ERROR_OK
) {
1712 LOG_ERROR("Error while reading PCSR");
1717 gettimeofday(&now
, NULL
);
1718 if (sample_count
>= max_num_samples
|| timeval_compare(&now
, &timeout
) > 0) {
1719 LOG_INFO("Profiling completed. %" PRIu32
" samples.", sample_count
);
1724 *num_samples
= sample_count
;
1729 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
1730 * on r/w if the core is not running, and clear on resume or reset ... or
1731 * at least, in a post_restore_context() method.
1734 struct dwt_reg_state
{
1735 struct target
*target
;
1737 uint8_t value
[4]; /* scratch/cache */
1740 static int cortex_m_dwt_get_reg(struct reg
*reg
)
1742 struct dwt_reg_state
*state
= reg
->arch_info
;
1745 int retval
= target_read_u32(state
->target
, state
->addr
, &tmp
);
1746 if (retval
!= ERROR_OK
)
1749 buf_set_u32(state
->value
, 0, 32, tmp
);
1753 static int cortex_m_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
1755 struct dwt_reg_state
*state
= reg
->arch_info
;
1757 return target_write_u32(state
->target
, state
->addr
,
1758 buf_get_u32(buf
, 0, reg
->size
));
1767 static const struct dwt_reg dwt_base_regs
[] = {
1768 { DWT_CTRL
, "dwt_ctrl", 32, },
1769 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
1770 * increments while the core is asleep.
1772 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
1773 /* plus some 8 bit counters, useful for profiling with TPIU */
1776 static const struct dwt_reg dwt_comp
[] = {
1777 #define DWT_COMPARATOR(i) \
1778 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
1779 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
1780 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
1797 #undef DWT_COMPARATOR
1800 static const struct reg_arch_type dwt_reg_type
= {
1801 .get
= cortex_m_dwt_get_reg
,
1802 .set
= cortex_m_dwt_set_reg
,
1805 static void cortex_m_dwt_addreg(struct target
*t
, struct reg
*r
, const struct dwt_reg
*d
)
1807 struct dwt_reg_state
*state
;
1809 state
= calloc(1, sizeof(*state
));
1812 state
->addr
= d
->addr
;
1817 r
->value
= state
->value
;
1818 r
->arch_info
= state
;
1819 r
->type
= &dwt_reg_type
;
1822 static void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
)
1825 struct reg_cache
*cache
;
1826 struct cortex_m_dwt_comparator
*comparator
;
1829 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
1830 LOG_DEBUG("DWT_CTRL: 0x%" PRIx32
, dwtcr
);
1832 LOG_DEBUG("no DWT");
1836 target_read_u32(target
, DWT_DEVARCH
, &cm
->dwt_devarch
);
1837 LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32
, cm
->dwt_devarch
);
1839 cm
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
1840 cm
->dwt_comp_available
= cm
->dwt_num_comp
;
1841 cm
->dwt_comparator_list
= calloc(cm
->dwt_num_comp
,
1842 sizeof(struct cortex_m_dwt_comparator
));
1843 if (!cm
->dwt_comparator_list
) {
1845 cm
->dwt_num_comp
= 0;
1846 LOG_ERROR("out of mem");
1850 cache
= calloc(1, sizeof(*cache
));
1853 free(cm
->dwt_comparator_list
);
1856 cache
->name
= "Cortex-M DWT registers";
1857 cache
->num_regs
= 2 + cm
->dwt_num_comp
* 3;
1858 cache
->reg_list
= calloc(cache
->num_regs
, sizeof(*cache
->reg_list
));
1859 if (!cache
->reg_list
) {
1864 for (reg
= 0; reg
< 2; reg
++)
1865 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
1866 dwt_base_regs
+ reg
);
1868 comparator
= cm
->dwt_comparator_list
;
1869 for (i
= 0; i
< cm
->dwt_num_comp
; i
++, comparator
++) {
1872 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
1873 for (j
= 0; j
< 3; j
++, reg
++)
1874 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
1875 dwt_comp
+ 3 * i
+ j
);
1877 /* make sure we clear any watchpoints enabled on the target */
1878 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
1881 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
1882 cm
->dwt_cache
= cache
;
1884 LOG_DEBUG("DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
1885 dwtcr
, cm
->dwt_num_comp
,
1886 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
1888 /* REVISIT: if num_comp > 1, check whether comparator #1 can
1889 * implement single-address data value watchpoints ... so we
1890 * won't need to check it later, when asked to set one up.
1894 static void cortex_m_dwt_free(struct target
*target
)
1896 struct cortex_m_common
*cm
= target_to_cm(target
);
1897 struct reg_cache
*cache
= cm
->dwt_cache
;
1899 free(cm
->dwt_comparator_list
);
1900 cm
->dwt_comparator_list
= NULL
;
1901 cm
->dwt_num_comp
= 0;
1904 register_unlink_cache(&target
->reg_cache
, cache
);
1906 if (cache
->reg_list
) {
1907 for (size_t i
= 0; i
< cache
->num_regs
; i
++)
1908 free(cache
->reg_list
[i
].arch_info
);
1909 free(cache
->reg_list
);
1913 cm
->dwt_cache
= NULL
;
1916 #define MVFR0 0xe000ef40
1917 #define MVFR1 0xe000ef44
1919 #define MVFR0_DEFAULT_M4 0x10110021
1920 #define MVFR1_DEFAULT_M4 0x11000011
1922 #define MVFR0_DEFAULT_M7_SP 0x10110021
1923 #define MVFR0_DEFAULT_M7_DP 0x10110221
1924 #define MVFR1_DEFAULT_M7_SP 0x11000011
1925 #define MVFR1_DEFAULT_M7_DP 0x12000011
1927 static int cortex_m_find_mem_ap(struct adiv5_dap
*swjdp
,
1928 struct adiv5_ap
**debug_ap
)
1930 if (dap_find_ap(swjdp
, AP_TYPE_AHB3_AP
, debug_ap
) == ERROR_OK
)
1933 return dap_find_ap(swjdp
, AP_TYPE_AHB5_AP
, debug_ap
);
1936 int cortex_m_examine(struct target
*target
)
1939 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
1941 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1942 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
1943 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1945 /* stlink shares the examine handler but does not support
1947 if (!armv7m
->stlink
) {
1948 if (cortex_m
->apsel
== DP_APSEL_INVALID
) {
1949 /* Search for the MEM-AP */
1950 retval
= cortex_m_find_mem_ap(swjdp
, &armv7m
->debug_ap
);
1951 if (retval
!= ERROR_OK
) {
1952 LOG_ERROR("Could not find MEM-AP to control the core");
1956 armv7m
->debug_ap
= dap_ap(swjdp
, cortex_m
->apsel
);
1959 /* Leave (only) generic DAP stuff for debugport_init(); */
1960 armv7m
->debug_ap
->memaccess_tck
= 8;
1962 retval
= mem_ap_init(armv7m
->debug_ap
);
1963 if (retval
!= ERROR_OK
)
1967 if (!target_was_examined(target
)) {
1968 target_set_examined(target
);
1970 /* Read from Device Identification Registers */
1971 retval
= target_read_u32(target
, CPUID
, &cpuid
);
1972 if (retval
!= ERROR_OK
)
1976 i
= (cpuid
>> 4) & 0xf;
1978 /* Check if it is an ARMv8-M core */
1979 armv7m
->arm
.is_armv8m
= true;
1981 switch (cpuid
& ARM_CPUID_PARTNO_MASK
) {
1982 case CORTEX_M23_PARTNO
:
1985 case CORTEX_M33_PARTNO
:
1988 case CORTEX_M35P_PARTNO
:
1991 case CORTEX_M55_PARTNO
:
1995 armv7m
->arm
.is_armv8m
= false;
2000 LOG_DEBUG("Cortex-M%d r%" PRId8
"p%" PRId8
" processor detected",
2001 i
, (uint8_t)((cpuid
>> 20) & 0xf), (uint8_t)((cpuid
>> 0) & 0xf));
2002 cortex_m
->maskints_erratum
= false;
2005 rev
= (cpuid
>> 20) & 0xf;
2006 patch
= (cpuid
>> 0) & 0xf;
2007 if ((rev
== 0) && (patch
< 2)) {
2008 LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
2009 cortex_m
->maskints_erratum
= true;
2012 LOG_DEBUG("cpuid: 0x%8.8" PRIx32
"", cpuid
);
2014 /* VECTRESET is supported only on ARMv7-M cores */
2015 cortex_m
->vectreset_supported
= !armv7m
->arm
.is_armv8m
&& !armv7m
->arm
.is_armv6m
;
2018 target_read_u32(target
, MVFR0
, &mvfr0
);
2019 target_read_u32(target
, MVFR1
, &mvfr1
);
2021 /* test for floating point feature on Cortex-M4 */
2022 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
2023 LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i
);
2024 armv7m
->fp_feature
= FPv4_SP
;
2026 } else if (i
== 7 || i
== 33 || i
== 35 || i
== 55) {
2027 target_read_u32(target
, MVFR0
, &mvfr0
);
2028 target_read_u32(target
, MVFR1
, &mvfr1
);
2030 /* test for floating point features on Cortex-M7 */
2031 if ((mvfr0
== MVFR0_DEFAULT_M7_SP
) && (mvfr1
== MVFR1_DEFAULT_M7_SP
)) {
2032 LOG_DEBUG("Cortex-M%d floating point feature FPv5_SP found", i
);
2033 armv7m
->fp_feature
= FPv5_SP
;
2034 } else if ((mvfr0
== MVFR0_DEFAULT_M7_DP
) && (mvfr1
== MVFR1_DEFAULT_M7_DP
)) {
2035 LOG_DEBUG("Cortex-M%d floating point feature FPv5_DP found", i
);
2036 armv7m
->fp_feature
= FPv5_DP
;
2038 } else if (i
== 0) {
2039 /* Cortex-M0 does not support unaligned memory access */
2040 armv7m
->arm
.is_armv6m
= true;
2043 if (armv7m
->fp_feature
== FP_NONE
&&
2044 armv7m
->arm
.core_cache
->num_regs
> ARMV7M_NUM_CORE_REGS_NOFP
) {
2045 /* free unavailable FPU registers */
2048 for (idx
= ARMV7M_NUM_CORE_REGS_NOFP
;
2049 idx
< armv7m
->arm
.core_cache
->num_regs
;
2051 free(armv7m
->arm
.core_cache
->reg_list
[idx
].feature
);
2052 free(armv7m
->arm
.core_cache
->reg_list
[idx
].reg_data_type
);
2054 armv7m
->arm
.core_cache
->num_regs
= ARMV7M_NUM_CORE_REGS_NOFP
;
2057 if (!armv7m
->stlink
) {
2058 if (i
== 3 || i
== 4)
2059 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2060 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2061 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 12);
2063 /* Cortex-M7 has only 1024 bytes autoincrement range */
2064 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 10);
2067 /* Enable debug requests */
2068 retval
= target_read_u32(target
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
2069 if (retval
!= ERROR_OK
)
2071 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
2072 uint32_t dhcsr
= (cortex_m
->dcb_dhcsr
| C_DEBUGEN
) & ~(C_HALT
| C_STEP
| C_MASKINTS
);
2074 retval
= target_write_u32(target
, DCB_DHCSR
, DBGKEY
| (dhcsr
& 0x0000FFFFUL
));
2075 if (retval
!= ERROR_OK
)
2077 cortex_m
->dcb_dhcsr
= dhcsr
;
2080 /* Configure trace modules */
2081 retval
= target_write_u32(target
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
2082 if (retval
!= ERROR_OK
)
2085 if (armv7m
->trace_config
.config_type
!= TRACE_CONFIG_TYPE_DISABLED
) {
2086 armv7m_trace_tpiu_config(target
);
2087 armv7m_trace_itm_config(target
);
2090 /* NOTE: FPB and DWT are both optional. */
2093 target_read_u32(target
, FP_CTRL
, &fpcr
);
2094 /* bits [14:12] and [7:4] */
2095 cortex_m
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF);
2096 cortex_m
->fp_num_lit
= (fpcr
>> 8) & 0xF;
2097 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2098 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2099 cortex_m
->fp_rev
= (fpcr
>> 28) & 0xf;
2100 free(cortex_m
->fp_comparator_list
);
2101 cortex_m
->fp_comparator_list
= calloc(
2102 cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
,
2103 sizeof(struct cortex_m_fp_comparator
));
2104 cortex_m
->fpb_enabled
= fpcr
& 1;
2105 for (i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
2106 cortex_m
->fp_comparator_list
[i
].type
=
2107 (i
< cortex_m
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
2108 cortex_m
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
2110 /* make sure we clear any breakpoints enabled on the target */
2111 target_write_u32(target
, cortex_m
->fp_comparator_list
[i
].fpcr_address
, 0);
2113 LOG_DEBUG("FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
2115 cortex_m
->fp_num_code
,
2116 cortex_m
->fp_num_lit
);
2119 cortex_m_dwt_free(target
);
2120 cortex_m_dwt_setup(cortex_m
, target
);
2122 /* These hardware breakpoints only work for code in flash! */
2123 LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
2124 target_name(target
),
2125 cortex_m
->fp_num_code
,
2126 cortex_m
->dwt_num_comp
);
2132 static int cortex_m_dcc_read(struct target
*target
, uint8_t *value
, uint8_t *ctrl
)
2134 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2139 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2140 if (retval
!= ERROR_OK
)
2143 dcrdr
= target_buffer_get_u16(target
, buf
);
2144 *ctrl
= (uint8_t)dcrdr
;
2145 *value
= (uint8_t)(dcrdr
>> 8);
2147 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
2149 /* write ack back to software dcc register
2150 * signify we have read data */
2151 if (dcrdr
& (1 << 0)) {
2152 target_buffer_set_u16(target
, buf
, 0);
2153 retval
= mem_ap_write_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2154 if (retval
!= ERROR_OK
)
2161 static int cortex_m_target_request_data(struct target
*target
,
2162 uint32_t size
, uint8_t *buffer
)
2168 for (i
= 0; i
< (size
* 4); i
++) {
2169 int retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2170 if (retval
!= ERROR_OK
)
2178 static int cortex_m_handle_target_request(void *priv
)
2180 struct target
*target
= priv
;
2181 if (!target_was_examined(target
))
2184 if (!target
->dbg_msg_enabled
)
2187 if (target
->state
== TARGET_RUNNING
) {
2192 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2193 if (retval
!= ERROR_OK
)
2196 /* check if we have data */
2197 if (ctrl
& (1 << 0)) {
2200 /* we assume target is quick enough */
2202 for (int i
= 1; i
<= 3; i
++) {
2203 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2204 if (retval
!= ERROR_OK
)
2206 request
|= ((uint32_t)data
<< (i
* 8));
2208 target_request(target
, request
);
2215 static int cortex_m_init_arch_info(struct target
*target
,
2216 struct cortex_m_common
*cortex_m
, struct adiv5_dap
*dap
)
2218 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2220 armv7m_init_arch_info(target
, armv7m
);
2222 /* default reset mode is to use srst if fitted
2223 * if not it will use CORTEX_M3_RESET_VECTRESET */
2224 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2226 armv7m
->arm
.dap
= dap
;
2228 /* register arch-specific functions */
2229 armv7m
->examine_debug_reason
= cortex_m_examine_debug_reason
;
2231 armv7m
->post_debug_entry
= NULL
;
2233 armv7m
->pre_restore_context
= NULL
;
2235 armv7m
->load_core_reg_u32
= cortex_m_load_core_reg_u32
;
2236 armv7m
->store_core_reg_u32
= cortex_m_store_core_reg_u32
;
2238 target_register_timer_callback(cortex_m_handle_target_request
, 1,
2239 TARGET_TIMER_TYPE_PERIODIC
, target
);
2244 static int cortex_m_target_create(struct target
*target
, Jim_Interp
*interp
)
2246 struct adiv5_private_config
*pc
;
2248 pc
= (struct adiv5_private_config
*)target
->private_config
;
2249 if (adiv5_verify_config(pc
) != ERROR_OK
)
2252 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
2253 if (cortex_m
== NULL
) {
2254 LOG_ERROR("No memory creating target");
2258 cortex_m
->common_magic
= CORTEX_M_COMMON_MAGIC
;
2259 cortex_m
->apsel
= pc
->ap_num
;
2261 cortex_m_init_arch_info(target
, cortex_m
, pc
->dap
);
2266 /*--------------------------------------------------------------------------*/
2268 static int cortex_m_verify_pointer(struct command_invocation
*cmd
,
2269 struct cortex_m_common
*cm
)
2271 if (cm
->common_magic
!= CORTEX_M_COMMON_MAGIC
) {
2272 command_print(cmd
, "target is not a Cortex-M");
2273 return ERROR_TARGET_INVALID
;
2279 * Only stuff below this line should need to verify that its target
2280 * is a Cortex-M3. Everything else should have indirected through the
2281 * cortexm3_target structure, which is only used with CM3 targets.
2284 COMMAND_HANDLER(handle_cortex_m_vector_catch_command
)
2286 struct target
*target
= get_current_target(CMD_CTX
);
2287 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2288 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2292 static const struct {
2296 { "hard_err", VC_HARDERR
, },
2297 { "int_err", VC_INTERR
, },
2298 { "bus_err", VC_BUSERR
, },
2299 { "state_err", VC_STATERR
, },
2300 { "chk_err", VC_CHKERR
, },
2301 { "nocp_err", VC_NOCPERR
, },
2302 { "mm_err", VC_MMERR
, },
2303 { "reset", VC_CORERESET
, },
2306 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2307 if (retval
!= ERROR_OK
)
2310 if (!target_was_examined(target
)) {
2311 LOG_ERROR("Target not examined yet");
2315 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2316 if (retval
!= ERROR_OK
)
2322 if (CMD_ARGC
== 1) {
2323 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2324 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2325 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2326 | VC_MMERR
| VC_CORERESET
;
2328 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2331 while (CMD_ARGC
-- > 0) {
2333 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2334 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2336 catch |= vec_ids
[i
].mask
;
2339 if (i
== ARRAY_SIZE(vec_ids
)) {
2340 LOG_ERROR("No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2341 return ERROR_COMMAND_SYNTAX_ERROR
;
2345 /* For now, armv7m->demcr only stores vector catch flags. */
2346 armv7m
->demcr
= catch;
2351 /* write, but don't assume it stuck (why not??) */
2352 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, demcr
);
2353 if (retval
!= ERROR_OK
)
2355 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2356 if (retval
!= ERROR_OK
)
2359 /* FIXME be sure to clear DEMCR on clean server shutdown.
2360 * Otherwise the vector catch hardware could fire when there's
2361 * no debugger hooked up, causing much confusion...
2365 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2366 command_print(CMD
, "%9s: %s", vec_ids
[i
].name
,
2367 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2373 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command
)
2375 struct target
*target
= get_current_target(CMD_CTX
);
2376 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2379 static const Jim_Nvp nvp_maskisr_modes
[] = {
2380 { .name
= "auto", .value
= CORTEX_M_ISRMASK_AUTO
},
2381 { .name
= "off", .value
= CORTEX_M_ISRMASK_OFF
},
2382 { .name
= "on", .value
= CORTEX_M_ISRMASK_ON
},
2383 { .name
= "steponly", .value
= CORTEX_M_ISRMASK_STEPONLY
},
2384 { .name
= NULL
, .value
= -1 },
2389 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2390 if (retval
!= ERROR_OK
)
2393 if (target
->state
!= TARGET_HALTED
) {
2394 command_print(CMD
, "target must be stopped for \"%s\" command", CMD_NAME
);
2399 n
= Jim_Nvp_name2value_simple(nvp_maskisr_modes
, CMD_ARGV
[0]);
2400 if (n
->name
== NULL
)
2401 return ERROR_COMMAND_SYNTAX_ERROR
;
2402 cortex_m
->isrmasking_mode
= n
->value
;
2403 cortex_m_set_maskints_for_halt(target
);
2406 n
= Jim_Nvp_value2name_simple(nvp_maskisr_modes
, cortex_m
->isrmasking_mode
);
2407 command_print(CMD
, "cortex_m interrupt mask %s", n
->name
);
2412 COMMAND_HANDLER(handle_cortex_m_reset_config_command
)
2414 struct target
*target
= get_current_target(CMD_CTX
);
2415 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2419 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2420 if (retval
!= ERROR_OK
)
2424 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2425 cortex_m
->soft_reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
2427 else if (strcmp(*CMD_ARGV
, "vectreset") == 0) {
2428 if (target_was_examined(target
)
2429 && !cortex_m
->vectreset_supported
)
2430 LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
2432 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2435 return ERROR_COMMAND_SYNTAX_ERROR
;
2438 switch (cortex_m
->soft_reset_config
) {
2439 case CORTEX_M_RESET_SYSRESETREQ
:
2440 reset_config
= "sysresetreq";
2443 case CORTEX_M_RESET_VECTRESET
:
2444 reset_config
= "vectreset";
2448 reset_config
= "unknown";
2452 command_print(CMD
, "cortex_m reset_config %s", reset_config
);
2457 static const struct command_registration cortex_m_exec_command_handlers
[] = {
2460 .handler
= handle_cortex_m_mask_interrupts_command
,
2461 .mode
= COMMAND_EXEC
,
2462 .help
= "mask cortex_m interrupts",
2463 .usage
= "['auto'|'on'|'off'|'steponly']",
2466 .name
= "vector_catch",
2467 .handler
= handle_cortex_m_vector_catch_command
,
2468 .mode
= COMMAND_EXEC
,
2469 .help
= "configure hardware vectors to trigger debug entry",
2470 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
2473 .name
= "reset_config",
2474 .handler
= handle_cortex_m_reset_config_command
,
2475 .mode
= COMMAND_ANY
,
2476 .help
= "configure software reset handling",
2477 .usage
= "['sysresetreq'|'vectreset']",
2479 COMMAND_REGISTRATION_DONE
2481 static const struct command_registration cortex_m_command_handlers
[] = {
2483 .chain
= armv7m_command_handlers
,
2486 .chain
= armv7m_trace_command_handlers
,
2490 .mode
= COMMAND_EXEC
,
2491 .help
= "Cortex-M command group",
2493 .chain
= cortex_m_exec_command_handlers
,
2496 .chain
= rtt_target_command_handlers
,
2498 COMMAND_REGISTRATION_DONE
2501 struct target_type cortexm_target
= {
2503 .deprecated_name
= "cortex_m3",
2505 .poll
= cortex_m_poll
,
2506 .arch_state
= armv7m_arch_state
,
2508 .target_request_data
= cortex_m_target_request_data
,
2510 .halt
= cortex_m_halt
,
2511 .resume
= cortex_m_resume
,
2512 .step
= cortex_m_step
,
2514 .assert_reset
= cortex_m_assert_reset
,
2515 .deassert_reset
= cortex_m_deassert_reset
,
2516 .soft_reset_halt
= cortex_m_soft_reset_halt
,
2518 .get_gdb_arch
= arm_get_gdb_arch
,
2519 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
2521 .read_memory
= cortex_m_read_memory
,
2522 .write_memory
= cortex_m_write_memory
,
2523 .checksum_memory
= armv7m_checksum_memory
,
2524 .blank_check_memory
= armv7m_blank_check_memory
,
2526 .run_algorithm
= armv7m_run_algorithm
,
2527 .start_algorithm
= armv7m_start_algorithm
,
2528 .wait_algorithm
= armv7m_wait_algorithm
,
2530 .add_breakpoint
= cortex_m_add_breakpoint
,
2531 .remove_breakpoint
= cortex_m_remove_breakpoint
,
2532 .add_watchpoint
= cortex_m_add_watchpoint
,
2533 .remove_watchpoint
= cortex_m_remove_watchpoint
,
2535 .commands
= cortex_m_command_handlers
,
2536 .target_create
= cortex_m_target_create
,
2537 .target_jim_configure
= adiv5_jim_configure
,
2538 .init_target
= cortex_m_init_target
,
2539 .examine
= cortex_m_examine
,
2540 .deinit_target
= cortex_m_deinit_target
,
2542 .profiling
= cortex_m_profiling
,
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256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)