1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
7 * Copyright (C) 2006 by Magnus Lundin *
10 * Copyright (C) 2008 by Spencer Oliver *
11 * spen@spen-soft.co.uk *
14 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
16 ***************************************************************************/
21 #include "jtag/interface.h"
22 #include "breakpoints.h"
24 #include "target_request.h"
25 #include "target_type.h"
26 #include "arm_adi_v5.h"
27 #include "arm_disassembler.h"
29 #include "arm_opcodes.h"
30 #include "arm_semihosting.h"
32 #include <helper/nvp.h>
33 #include <helper/time_support.h>
36 /* NOTE: most of this should work fine for the Cortex-M1 and
37 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
38 * Some differences: M0/M1 doesn't have FPB remapping or the
39 * DWT tracing/profiling support. (So the cycle counter will
40 * not be usable; the other stuff isn't currently used here.)
42 * Although there are some workarounds for errata seen only in r0p0
43 * silicon, such old parts are hard to find and thus not much tested
47 /* Timeout for register r/w */
48 #define DHCSR_S_REGRDY_TIMEOUT (500)
50 /* Supported Cortex-M Cores */
51 static const struct cortex_m_part_info cortex_m_parts
[] = {
53 .partno
= CORTEX_M0_PARTNO
,
58 .partno
= CORTEX_M0P_PARTNO
,
63 .partno
= CORTEX_M1_PARTNO
,
68 .partno
= CORTEX_M3_PARTNO
,
71 .flags
= CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K
,
74 .partno
= CORTEX_M4_PARTNO
,
77 .flags
= CORTEX_M_F_HAS_FPV4
| CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K
,
80 .partno
= CORTEX_M7_PARTNO
,
83 .flags
= CORTEX_M_F_HAS_FPV5
,
86 .partno
= CORTEX_M23_PARTNO
,
91 .partno
= CORTEX_M33_PARTNO
,
94 .flags
= CORTEX_M_F_HAS_FPV5
,
97 .partno
= CORTEX_M35P_PARTNO
,
98 .name
= "Cortex-M35P",
100 .flags
= CORTEX_M_F_HAS_FPV5
,
103 .partno
= CORTEX_M55_PARTNO
,
104 .name
= "Cortex-M55",
105 .arch
= ARM_ARCH_V8M
,
106 .flags
= CORTEX_M_F_HAS_FPV5
,
109 .partno
= STAR_MC1_PARTNO
,
111 .arch
= ARM_ARCH_V8M
,
112 .flags
= CORTEX_M_F_HAS_FPV5
,
116 /* forward declarations */
117 static int cortex_m_store_core_reg_u32(struct target
*target
,
118 uint32_t num
, uint32_t value
);
119 static void cortex_m_dwt_free(struct target
*target
);
121 /** DCB DHCSR register contains S_RETIRE_ST and S_RESET_ST bits cleared
122 * on a read. Call this helper function each time DHCSR is read
123 * to preserve S_RESET_ST state in case of a reset event was detected.
125 static inline void cortex_m_cumulate_dhcsr_sticky(struct cortex_m_common
*cortex_m
,
128 cortex_m
->dcb_dhcsr_cumulated_sticky
|= dhcsr
;
131 /** Read DCB DHCSR register to cortex_m->dcb_dhcsr and cumulate
132 * sticky bits in cortex_m->dcb_dhcsr_cumulated_sticky
134 static int cortex_m_read_dhcsr_atomic_sticky(struct target
*target
)
136 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
137 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
139 int retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
140 &cortex_m
->dcb_dhcsr
);
141 if (retval
!= ERROR_OK
)
144 cortex_m_cumulate_dhcsr_sticky(cortex_m
, cortex_m
->dcb_dhcsr
);
148 static int cortex_m_load_core_reg_u32(struct target
*target
,
149 uint32_t regsel
, uint32_t *value
)
151 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
152 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
154 uint32_t dcrdr
, tmp_value
;
157 /* because the DCB_DCRDR is used for the emulated dcc channel
158 * we have to save/restore the DCB_DCRDR when used */
159 if (target
->dbg_msg_enabled
) {
160 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
161 if (retval
!= ERROR_OK
)
165 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regsel
);
166 if (retval
!= ERROR_OK
)
169 /* check if value from register is ready and pre-read it */
172 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DHCSR
,
173 &cortex_m
->dcb_dhcsr
);
174 if (retval
!= ERROR_OK
)
176 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
,
178 if (retval
!= ERROR_OK
)
180 cortex_m_cumulate_dhcsr_sticky(cortex_m
, cortex_m
->dcb_dhcsr
);
181 if (cortex_m
->dcb_dhcsr
& S_REGRDY
)
183 cortex_m
->slow_register_read
= true; /* Polling (still) needed. */
184 if (timeval_ms() > then
+ DHCSR_S_REGRDY_TIMEOUT
) {
185 LOG_TARGET_ERROR(target
, "Timeout waiting for DCRDR transfer ready");
186 return ERROR_TIMEOUT_REACHED
;
193 if (target
->dbg_msg_enabled
) {
194 /* restore DCB_DCRDR - this needs to be in a separate
195 * transaction otherwise the emulated DCC channel breaks */
196 if (retval
== ERROR_OK
)
197 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
203 static int cortex_m_slow_read_all_regs(struct target
*target
)
205 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
206 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
207 const unsigned int num_regs
= armv7m
->arm
.core_cache
->num_regs
;
209 /* Opportunistically restore fast read, it'll revert to slow
210 * if any register needed polling in cortex_m_load_core_reg_u32(). */
211 cortex_m
->slow_register_read
= false;
213 for (unsigned int reg_id
= 0; reg_id
< num_regs
; reg_id
++) {
214 struct reg
*r
= &armv7m
->arm
.core_cache
->reg_list
[reg_id
];
216 int retval
= armv7m
->arm
.read_core_reg(target
, r
, reg_id
, ARM_MODE_ANY
);
217 if (retval
!= ERROR_OK
)
222 if (!cortex_m
->slow_register_read
)
223 LOG_TARGET_DEBUG(target
, "Switching back to fast register reads");
228 static int cortex_m_queue_reg_read(struct target
*target
, uint32_t regsel
,
229 uint32_t *reg_value
, uint32_t *dhcsr
)
231 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
234 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regsel
);
235 if (retval
!= ERROR_OK
)
238 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DHCSR
, dhcsr
);
239 if (retval
!= ERROR_OK
)
242 return mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, reg_value
);
245 static int cortex_m_fast_read_all_regs(struct target
*target
)
247 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
248 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
252 /* because the DCB_DCRDR is used for the emulated dcc channel
253 * we have to save/restore the DCB_DCRDR when used */
254 if (target
->dbg_msg_enabled
) {
255 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
256 if (retval
!= ERROR_OK
)
260 const unsigned int num_regs
= armv7m
->arm
.core_cache
->num_regs
;
261 const unsigned int n_r32
= ARMV7M_LAST_REG
- ARMV7M_CORE_FIRST_REG
+ 1
262 + ARMV7M_FPU_LAST_REG
- ARMV7M_FPU_FIRST_REG
+ 1;
263 /* we need one 32-bit word for each register except FP D0..D15, which
265 uint32_t r_vals
[n_r32
];
266 uint32_t dhcsr
[n_r32
];
268 unsigned int wi
= 0; /* write index to r_vals and dhcsr arrays */
269 unsigned int reg_id
; /* register index in the reg_list, ARMV7M_R0... */
270 for (reg_id
= 0; reg_id
< num_regs
; reg_id
++) {
271 struct reg
*r
= &armv7m
->arm
.core_cache
->reg_list
[reg_id
];
273 continue; /* skip non existent registers */
276 /* Any 8-bit or shorter register is unpacked from a 32-bit
277 * container register. Skip it now. */
281 uint32_t regsel
= armv7m_map_id_to_regsel(reg_id
);
282 retval
= cortex_m_queue_reg_read(target
, regsel
, &r_vals
[wi
],
284 if (retval
!= ERROR_OK
)
288 assert(r
->size
== 32 || r
->size
== 64);
290 continue; /* done with 32-bit register */
292 assert(reg_id
>= ARMV7M_FPU_FIRST_REG
&& reg_id
<= ARMV7M_FPU_LAST_REG
);
293 /* the odd part of FP register (S1, S3...) */
294 retval
= cortex_m_queue_reg_read(target
, regsel
+ 1, &r_vals
[wi
],
296 if (retval
!= ERROR_OK
)
303 retval
= dap_run(armv7m
->debug_ap
->dap
);
304 if (retval
!= ERROR_OK
)
307 if (target
->dbg_msg_enabled
) {
308 /* restore DCB_DCRDR - this needs to be in a separate
309 * transaction otherwise the emulated DCC channel breaks */
310 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
311 if (retval
!= ERROR_OK
)
315 bool not_ready
= false;
316 for (unsigned int i
= 0; i
< wi
; i
++) {
317 if ((dhcsr
[i
] & S_REGRDY
) == 0) {
319 LOG_TARGET_DEBUG(target
, "Register %u was not ready during fast read", i
);
321 cortex_m_cumulate_dhcsr_sticky(cortex_m
, dhcsr
[i
]);
325 /* Any register was not ready,
326 * fall back to slow read with S_REGRDY polling */
327 return ERROR_TIMEOUT_REACHED
;
330 LOG_TARGET_DEBUG(target
, "read %u 32-bit registers", wi
);
332 unsigned int ri
= 0; /* read index from r_vals array */
333 for (reg_id
= 0; reg_id
< num_regs
; reg_id
++) {
334 struct reg
*r
= &armv7m
->arm
.core_cache
->reg_list
[reg_id
];
336 continue; /* skip non existent registers */
340 unsigned int reg32_id
;
342 if (armv7m_map_reg_packing(reg_id
, ®32_id
, &offset
)) {
343 /* Unpack a partial register from 32-bit container register */
344 struct reg
*r32
= &armv7m
->arm
.core_cache
->reg_list
[reg32_id
];
346 /* The container register ought to precede all regs unpacked
347 * from it in the reg_list. So the value should be ready
350 buf_cpy(r32
->value
+ offset
, r
->value
, r
->size
);
353 assert(r
->size
== 32 || r
->size
== 64);
354 buf_set_u32(r
->value
, 0, 32, r_vals
[ri
++]);
357 assert(reg_id
>= ARMV7M_FPU_FIRST_REG
&& reg_id
<= ARMV7M_FPU_LAST_REG
);
358 /* the odd part of FP register (S1, S3...) */
359 buf_set_u32(r
->value
+ 4, 0, 32, r_vals
[ri
++]);
369 static int cortex_m_store_core_reg_u32(struct target
*target
,
370 uint32_t regsel
, uint32_t value
)
372 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
373 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
378 /* because the DCB_DCRDR is used for the emulated dcc channel
379 * we have to save/restore the DCB_DCRDR when used */
380 if (target
->dbg_msg_enabled
) {
381 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
382 if (retval
!= ERROR_OK
)
386 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
387 if (retval
!= ERROR_OK
)
390 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regsel
| DCRSR_WNR
);
391 if (retval
!= ERROR_OK
)
394 /* check if value is written into register */
397 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
398 if (retval
!= ERROR_OK
)
400 if (cortex_m
->dcb_dhcsr
& S_REGRDY
)
402 if (timeval_ms() > then
+ DHCSR_S_REGRDY_TIMEOUT
) {
403 LOG_TARGET_ERROR(target
, "Timeout waiting for DCRDR transfer ready");
404 return ERROR_TIMEOUT_REACHED
;
409 if (target
->dbg_msg_enabled
) {
410 /* restore DCB_DCRDR - this needs to be in a separate
411 * transaction otherwise the emulated DCC channel breaks */
412 if (retval
== ERROR_OK
)
413 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
419 static int cortex_m_write_debug_halt_mask(struct target
*target
,
420 uint32_t mask_on
, uint32_t mask_off
)
422 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
423 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
425 /* mask off status bits */
426 cortex_m
->dcb_dhcsr
&= ~((0xFFFFul
<< 16) | mask_off
);
427 /* create new register mask */
428 cortex_m
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
430 return mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, cortex_m
->dcb_dhcsr
);
433 static int cortex_m_set_maskints(struct target
*target
, bool mask
)
435 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
436 if (!!(cortex_m
->dcb_dhcsr
& C_MASKINTS
) != mask
)
437 return cortex_m_write_debug_halt_mask(target
, mask
? C_MASKINTS
: 0, mask
? 0 : C_MASKINTS
);
442 static int cortex_m_set_maskints_for_halt(struct target
*target
)
444 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
445 switch (cortex_m
->isrmasking_mode
) {
446 case CORTEX_M_ISRMASK_AUTO
:
447 /* interrupts taken at resume, whether for step or run -> no mask */
448 return cortex_m_set_maskints(target
, false);
450 case CORTEX_M_ISRMASK_OFF
:
451 /* interrupts never masked */
452 return cortex_m_set_maskints(target
, false);
454 case CORTEX_M_ISRMASK_ON
:
455 /* interrupts always masked */
456 return cortex_m_set_maskints(target
, true);
458 case CORTEX_M_ISRMASK_STEPONLY
:
459 /* interrupts masked for single step only -> mask now if MASKINTS
460 * erratum, otherwise only mask before stepping */
461 return cortex_m_set_maskints(target
, cortex_m
->maskints_erratum
);
466 static int cortex_m_set_maskints_for_run(struct target
*target
)
468 switch (target_to_cm(target
)->isrmasking_mode
) {
469 case CORTEX_M_ISRMASK_AUTO
:
470 /* interrupts taken at resume, whether for step or run -> no mask */
471 return cortex_m_set_maskints(target
, false);
473 case CORTEX_M_ISRMASK_OFF
:
474 /* interrupts never masked */
475 return cortex_m_set_maskints(target
, false);
477 case CORTEX_M_ISRMASK_ON
:
478 /* interrupts always masked */
479 return cortex_m_set_maskints(target
, true);
481 case CORTEX_M_ISRMASK_STEPONLY
:
482 /* interrupts masked for single step only -> no mask */
483 return cortex_m_set_maskints(target
, false);
488 static int cortex_m_set_maskints_for_step(struct target
*target
)
490 switch (target_to_cm(target
)->isrmasking_mode
) {
491 case CORTEX_M_ISRMASK_AUTO
:
492 /* the auto-interrupt should already be done -> mask */
493 return cortex_m_set_maskints(target
, true);
495 case CORTEX_M_ISRMASK_OFF
:
496 /* interrupts never masked */
497 return cortex_m_set_maskints(target
, false);
499 case CORTEX_M_ISRMASK_ON
:
500 /* interrupts always masked */
501 return cortex_m_set_maskints(target
, true);
503 case CORTEX_M_ISRMASK_STEPONLY
:
504 /* interrupts masked for single step only -> mask */
505 return cortex_m_set_maskints(target
, true);
510 static int cortex_m_clear_halt(struct target
*target
)
512 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
513 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
516 /* clear step if any */
517 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
519 /* Read Debug Fault Status Register */
520 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, &cortex_m
->nvic_dfsr
);
521 if (retval
!= ERROR_OK
)
524 /* Clear Debug Fault Status */
525 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, cortex_m
->nvic_dfsr
);
526 if (retval
!= ERROR_OK
)
528 LOG_TARGET_DEBUG(target
, "NVIC_DFSR 0x%" PRIx32
"", cortex_m
->nvic_dfsr
);
533 static int cortex_m_single_step_core(struct target
*target
)
535 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
538 /* Mask interrupts before clearing halt, if not done already. This avoids
539 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
540 * HALT can put the core into an unknown state.
542 if (!(cortex_m
->dcb_dhcsr
& C_MASKINTS
)) {
543 retval
= cortex_m_write_debug_halt_mask(target
, C_MASKINTS
, 0);
544 if (retval
!= ERROR_OK
)
547 retval
= cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
548 if (retval
!= ERROR_OK
)
550 LOG_TARGET_DEBUG(target
, "single step");
552 /* restore dhcsr reg */
553 cortex_m_clear_halt(target
);
558 static int cortex_m_enable_fpb(struct target
*target
)
560 int retval
= target_write_u32(target
, FP_CTRL
, 3);
561 if (retval
!= ERROR_OK
)
564 /* check the fpb is actually enabled */
566 retval
= target_read_u32(target
, FP_CTRL
, &fpctrl
);
567 if (retval
!= ERROR_OK
)
576 static int cortex_m_endreset_event(struct target
*target
)
580 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
581 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
582 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
583 struct cortex_m_fp_comparator
*fp_list
= cortex_m
->fp_comparator_list
;
584 struct cortex_m_dwt_comparator
*dwt_list
= cortex_m
->dwt_comparator_list
;
586 /* REVISIT The four debug monitor bits are currently ignored... */
587 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &dcb_demcr
);
588 if (retval
!= ERROR_OK
)
590 LOG_TARGET_DEBUG(target
, "DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
592 /* this register is used for emulated dcc channel */
593 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
594 if (retval
!= ERROR_OK
)
597 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
598 if (retval
!= ERROR_OK
)
601 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
602 /* Enable debug requests */
603 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
604 if (retval
!= ERROR_OK
)
608 /* Restore proper interrupt masking setting for running CPU. */
609 cortex_m_set_maskints_for_run(target
);
611 /* Enable features controlled by ITM and DWT blocks, and catch only
612 * the vectors we were told to pay attention to.
614 * Target firmware is responsible for all fault handling policy
615 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
616 * or manual updates to the NVIC SHCSR and CCR registers.
618 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
619 if (retval
!= ERROR_OK
)
622 /* Paranoia: evidently some (early?) chips don't preserve all the
623 * debug state (including FPB, DWT, etc) across reset...
627 retval
= cortex_m_enable_fpb(target
);
628 if (retval
!= ERROR_OK
) {
629 LOG_TARGET_ERROR(target
, "Failed to enable the FPB");
633 cortex_m
->fpb_enabled
= true;
635 /* Restore FPB registers */
636 for (unsigned int i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
637 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
638 if (retval
!= ERROR_OK
)
642 /* Restore DWT registers */
643 for (unsigned int i
= 0; i
< cortex_m
->dwt_num_comp
; i
++) {
644 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
646 if (retval
!= ERROR_OK
)
648 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
650 if (retval
!= ERROR_OK
)
652 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
653 dwt_list
[i
].function
);
654 if (retval
!= ERROR_OK
)
657 retval
= dap_run(swjdp
);
658 if (retval
!= ERROR_OK
)
661 register_cache_invalidate(armv7m
->arm
.core_cache
);
663 /* TODO: invalidate also working areas (needed in the case of detected reset).
664 * Doing so will require flash drivers to test if working area
665 * is still valid in all target algo calling loops.
668 /* make sure we have latest dhcsr flags */
669 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
670 if (retval
!= ERROR_OK
)
676 static int cortex_m_examine_debug_reason(struct target
*target
)
678 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
680 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
681 * only check the debug reason if we don't know it already */
683 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
684 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
685 if (cortex_m
->nvic_dfsr
& DFSR_BKPT
) {
686 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
687 if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
688 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
689 } else if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
690 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
691 else if (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)
692 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
693 else if (cortex_m
->nvic_dfsr
& DFSR_EXTERNAL
)
694 target
->debug_reason
= DBG_REASON_DBGRQ
;
696 target
->debug_reason
= DBG_REASON_UNDEFINED
;
702 static int cortex_m_examine_exception_reason(struct target
*target
)
704 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
705 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
706 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
709 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SHCSR
, &shcsr
);
710 if (retval
!= ERROR_OK
)
712 switch (armv7m
->exception_number
) {
715 case 3: /* Hard Fault */
716 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_HFSR
, &except_sr
);
717 if (retval
!= ERROR_OK
)
719 if (except_sr
& 0x40000000) {
720 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &cfsr
);
721 if (retval
!= ERROR_OK
)
725 case 4: /* Memory Management */
726 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
727 if (retval
!= ERROR_OK
)
729 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_MMFAR
, &except_ar
);
730 if (retval
!= ERROR_OK
)
733 case 5: /* Bus Fault */
734 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
735 if (retval
!= ERROR_OK
)
737 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_BFAR
, &except_ar
);
738 if (retval
!= ERROR_OK
)
741 case 6: /* Usage Fault */
742 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
743 if (retval
!= ERROR_OK
)
746 case 7: /* Secure Fault */
747 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SFSR
, &except_sr
);
748 if (retval
!= ERROR_OK
)
750 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SFAR
, &except_ar
);
751 if (retval
!= ERROR_OK
)
754 case 11: /* SVCall */
756 case 12: /* Debug Monitor */
757 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_DFSR
, &except_sr
);
758 if (retval
!= ERROR_OK
)
761 case 14: /* PendSV */
763 case 15: /* SysTick */
769 retval
= dap_run(swjdp
);
770 if (retval
== ERROR_OK
)
771 LOG_TARGET_DEBUG(target
, "%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
772 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
773 armv7m_exception_string(armv7m
->exception_number
),
774 shcsr
, except_sr
, cfsr
, except_ar
);
778 static int cortex_m_debug_entry(struct target
*target
)
782 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
783 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
784 struct arm
*arm
= &armv7m
->arm
;
787 LOG_TARGET_DEBUG(target
, " ");
789 /* Do this really early to minimize the window where the MASKINTS erratum
790 * can pile up pending interrupts. */
791 cortex_m_set_maskints_for_halt(target
);
793 cortex_m_clear_halt(target
);
795 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
796 if (retval
!= ERROR_OK
)
799 retval
= armv7m
->examine_debug_reason(target
);
800 if (retval
!= ERROR_OK
)
803 /* examine PE security state */
805 if (armv7m
->arm
.arch
== ARM_ARCH_V8M
) {
806 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DSCSR
, &dscsr
);
807 if (retval
!= ERROR_OK
)
811 /* Load all registers to arm.core_cache */
812 if (!cortex_m
->slow_register_read
) {
813 retval
= cortex_m_fast_read_all_regs(target
);
814 if (retval
== ERROR_TIMEOUT_REACHED
) {
815 cortex_m
->slow_register_read
= true;
816 LOG_TARGET_DEBUG(target
, "Switched to slow register read");
820 if (cortex_m
->slow_register_read
)
821 retval
= cortex_m_slow_read_all_regs(target
);
823 if (retval
!= ERROR_OK
)
827 xpsr
= buf_get_u32(r
->value
, 0, 32);
829 /* Are we in an exception handler */
831 armv7m
->exception_number
= (xpsr
& 0x1FF);
833 arm
->core_mode
= ARM_MODE_HANDLER
;
834 arm
->map
= armv7m_msp_reg_map
;
836 unsigned control
= buf_get_u32(arm
->core_cache
837 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 3);
839 /* is this thread privileged? */
840 arm
->core_mode
= control
& 1
841 ? ARM_MODE_USER_THREAD
844 /* which stack is it using? */
846 arm
->map
= armv7m_psp_reg_map
;
848 arm
->map
= armv7m_msp_reg_map
;
850 armv7m
->exception_number
= 0;
853 if (armv7m
->exception_number
)
854 cortex_m_examine_exception_reason(target
);
856 bool secure_state
= (dscsr
& DSCSR_CDS
) == DSCSR_CDS
;
857 LOG_TARGET_DEBUG(target
, "entered debug state in core mode: %s at PC 0x%" PRIx32
858 ", cpu in %s state, target->state: %s",
859 arm_mode_name(arm
->core_mode
),
860 buf_get_u32(arm
->pc
->value
, 0, 32),
861 secure_state
? "Secure" : "Non-Secure",
862 target_state_name(target
));
864 if (armv7m
->post_debug_entry
) {
865 retval
= armv7m
->post_debug_entry(target
);
866 if (retval
!= ERROR_OK
)
873 static int cortex_m_poll_one(struct target
*target
)
875 int detected_failure
= ERROR_OK
;
876 int retval
= ERROR_OK
;
877 enum target_state prev_target_state
= target
->state
;
878 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
879 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
881 /* Read from Debug Halting Control and Status Register */
882 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
883 if (retval
!= ERROR_OK
) {
884 target
->state
= TARGET_UNKNOWN
;
888 /* Recover from lockup. See ARMv7-M architecture spec,
889 * section B1.5.15 "Unrecoverable exception cases".
891 if (cortex_m
->dcb_dhcsr
& S_LOCKUP
) {
892 LOG_TARGET_ERROR(target
, "clearing lockup after double fault");
893 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
894 target
->debug_reason
= DBG_REASON_DBGRQ
;
896 /* We have to execute the rest (the "finally" equivalent, but
897 * still throw this exception again).
899 detected_failure
= ERROR_FAIL
;
901 /* refresh status bits */
902 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
903 if (retval
!= ERROR_OK
)
907 if (cortex_m
->dcb_dhcsr_cumulated_sticky
& S_RESET_ST
) {
908 cortex_m
->dcb_dhcsr_cumulated_sticky
&= ~S_RESET_ST
;
909 if (target
->state
!= TARGET_RESET
) {
910 target
->state
= TARGET_RESET
;
911 LOG_TARGET_INFO(target
, "external reset detected");
916 if (target
->state
== TARGET_RESET
) {
917 /* Cannot switch context while running so endreset is
918 * called with target->state == TARGET_RESET
920 LOG_TARGET_DEBUG(target
, "Exit from reset with dcb_dhcsr 0x%" PRIx32
,
921 cortex_m
->dcb_dhcsr
);
922 retval
= cortex_m_endreset_event(target
);
923 if (retval
!= ERROR_OK
) {
924 target
->state
= TARGET_UNKNOWN
;
927 target
->state
= TARGET_RUNNING
;
928 prev_target_state
= TARGET_RUNNING
;
931 if (cortex_m
->dcb_dhcsr
& S_HALT
) {
932 target
->state
= TARGET_HALTED
;
934 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
935 retval
= cortex_m_debug_entry(target
);
937 /* arm_semihosting needs to know registers, don't run if debug entry returned error */
938 if (retval
== ERROR_OK
&& arm_semihosting(target
, &retval
) != 0)
942 LOG_TARGET_DEBUG(target
, "postpone target event 'halted'");
943 target
->smp_halt_event_postponed
= true;
945 /* regardless of errors returned in previous code update state */
946 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
949 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
950 retval
= cortex_m_debug_entry(target
);
952 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
954 if (retval
!= ERROR_OK
)
958 if (target
->state
== TARGET_UNKNOWN
) {
959 /* Check if processor is retiring instructions or sleeping.
960 * Unlike S_RESET_ST here we test if the target *is* running now,
961 * not if it has been running (possibly in the past). Instructions are
962 * typically processed much faster than OpenOCD polls DHCSR so S_RETIRE_ST
963 * is read always 1. That's the reason not to use dcb_dhcsr_cumulated_sticky.
965 if (cortex_m
->dcb_dhcsr
& S_RETIRE_ST
|| cortex_m
->dcb_dhcsr
& S_SLEEP
) {
966 target
->state
= TARGET_RUNNING
;
971 /* Check that target is truly halted, since the target could be resumed externally */
972 if ((prev_target_state
== TARGET_HALTED
) && !(cortex_m
->dcb_dhcsr
& S_HALT
)) {
973 /* registers are now invalid */
974 register_cache_invalidate(armv7m
->arm
.core_cache
);
976 target
->state
= TARGET_RUNNING
;
977 LOG_TARGET_WARNING(target
, "external resume detected");
978 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
982 /* Did we detect a failure condition that we cleared? */
983 if (detected_failure
!= ERROR_OK
)
984 retval
= detected_failure
;
988 static int cortex_m_halt_one(struct target
*target
);
990 static int cortex_m_smp_halt_all(struct list_head
*smp_targets
)
992 int retval
= ERROR_OK
;
993 struct target_list
*head
;
995 foreach_smp_target(head
, smp_targets
) {
996 struct target
*curr
= head
->target
;
997 if (!target_was_examined(curr
))
999 if (curr
->state
== TARGET_HALTED
)
1002 int ret2
= cortex_m_halt_one(curr
);
1003 if (retval
== ERROR_OK
)
1004 retval
= ret2
; /* store the first error code ignore others */
1009 static int cortex_m_smp_post_halt_poll(struct list_head
*smp_targets
)
1011 int retval
= ERROR_OK
;
1012 struct target_list
*head
;
1014 foreach_smp_target(head
, smp_targets
) {
1015 struct target
*curr
= head
->target
;
1016 if (!target_was_examined(curr
))
1018 /* skip targets that were already halted */
1019 if (curr
->state
== TARGET_HALTED
)
1022 int ret2
= cortex_m_poll_one(curr
);
1023 if (retval
== ERROR_OK
)
1024 retval
= ret2
; /* store the first error code ignore others */
1029 static int cortex_m_poll_smp(struct list_head
*smp_targets
)
1031 int retval
= ERROR_OK
;
1032 struct target_list
*head
;
1033 bool halted
= false;
1035 foreach_smp_target(head
, smp_targets
) {
1036 struct target
*curr
= head
->target
;
1037 if (curr
->smp_halt_event_postponed
) {
1044 retval
= cortex_m_smp_halt_all(smp_targets
);
1046 int ret2
= cortex_m_smp_post_halt_poll(smp_targets
);
1047 if (retval
== ERROR_OK
)
1048 retval
= ret2
; /* store the first error code ignore others */
1050 foreach_smp_target(head
, smp_targets
) {
1051 struct target
*curr
= head
->target
;
1052 if (!curr
->smp_halt_event_postponed
)
1055 curr
->smp_halt_event_postponed
= false;
1056 if (curr
->state
== TARGET_HALTED
) {
1057 LOG_TARGET_DEBUG(curr
, "sending postponed target event 'halted'");
1058 target_call_event_callbacks(curr
, TARGET_EVENT_HALTED
);
1061 /* There is no need to set gdb_service->target
1062 * as hwthread_update_threads() selects an interesting thread
1069 static int cortex_m_poll(struct target
*target
)
1071 int retval
= cortex_m_poll_one(target
);
1074 struct target_list
*last
;
1075 last
= list_last_entry(target
->smp_targets
, struct target_list
, lh
);
1076 if (target
== last
->target
)
1077 /* After the last target in SMP group has been polled
1078 * check for postponed halted events and eventually halt and re-poll
1080 cortex_m_poll_smp(target
->smp_targets
);
1085 static int cortex_m_halt_one(struct target
*target
)
1087 LOG_TARGET_DEBUG(target
, "target->state: %s", target_state_name(target
));
1089 if (target
->state
== TARGET_HALTED
) {
1090 LOG_TARGET_DEBUG(target
, "target was already halted");
1094 if (target
->state
== TARGET_UNKNOWN
)
1095 LOG_TARGET_WARNING(target
, "target was in unknown state when halt was requested");
1097 if (target
->state
== TARGET_RESET
) {
1098 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
1099 LOG_TARGET_ERROR(target
, "can't request a halt while in reset if nSRST pulls nTRST");
1100 return ERROR_TARGET_FAILURE
;
1102 /* we came here in a reset_halt or reset_init sequence
1103 * debug entry was already prepared in cortex_m3_assert_reset()
1105 target
->debug_reason
= DBG_REASON_DBGRQ
;
1111 /* Write to Debug Halting Control and Status Register */
1112 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1114 /* Do this really early to minimize the window where the MASKINTS erratum
1115 * can pile up pending interrupts. */
1116 cortex_m_set_maskints_for_halt(target
);
1118 target
->debug_reason
= DBG_REASON_DBGRQ
;
1123 static int cortex_m_halt(struct target
*target
)
1126 return cortex_m_smp_halt_all(target
->smp_targets
);
1128 return cortex_m_halt_one(target
);
1131 static int cortex_m_soft_reset_halt(struct target
*target
)
1133 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1134 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1135 int retval
, timeout
= 0;
1137 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
1138 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
1139 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
1140 * core, not the peripherals */
1141 LOG_TARGET_DEBUG(target
, "soft_reset_halt is discouraged, please use 'reset halt' instead.");
1143 if (!cortex_m
->vectreset_supported
) {
1144 LOG_TARGET_ERROR(target
, "VECTRESET is not supported on this Cortex-M core");
1149 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_STEP
| C_MASKINTS
);
1150 if (retval
!= ERROR_OK
)
1153 /* Enter debug state on reset; restore DEMCR in endreset_event() */
1154 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
,
1155 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1156 if (retval
!= ERROR_OK
)
1159 /* Request a core-only reset */
1160 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
1161 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
1162 if (retval
!= ERROR_OK
)
1164 target
->state
= TARGET_RESET
;
1166 /* registers are now invalid */
1167 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1169 while (timeout
< 100) {
1170 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
1171 if (retval
== ERROR_OK
) {
1172 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
,
1173 &cortex_m
->nvic_dfsr
);
1174 if (retval
!= ERROR_OK
)
1176 if ((cortex_m
->dcb_dhcsr
& S_HALT
)
1177 && (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)) {
1178 LOG_TARGET_DEBUG(target
, "system reset-halted, DHCSR 0x%08" PRIx32
", DFSR 0x%08" PRIx32
,
1179 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_dfsr
);
1180 cortex_m_poll(target
);
1181 /* FIXME restore user's vector catch config */
1184 LOG_TARGET_DEBUG(target
, "waiting for system reset-halt, "
1185 "DHCSR 0x%08" PRIx32
", %d ms",
1186 cortex_m
->dcb_dhcsr
, timeout
);
1196 void cortex_m_enable_breakpoints(struct target
*target
)
1198 struct breakpoint
*breakpoint
= target
->breakpoints
;
1200 /* set any pending breakpoints */
1201 while (breakpoint
) {
1202 if (!breakpoint
->is_set
)
1203 cortex_m_set_breakpoint(target
, breakpoint
);
1204 breakpoint
= breakpoint
->next
;
1208 static int cortex_m_restore_one(struct target
*target
, bool current
,
1209 target_addr_t
*address
, bool handle_breakpoints
, bool debug_execution
)
1211 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1212 struct breakpoint
*breakpoint
= NULL
;
1216 if (target
->state
!= TARGET_HALTED
) {
1217 LOG_TARGET_ERROR(target
, "not halted");
1218 return ERROR_TARGET_NOT_HALTED
;
1221 if (!debug_execution
) {
1222 target_free_all_working_areas(target
);
1223 cortex_m_enable_breakpoints(target
);
1224 cortex_m_enable_watchpoints(target
);
1227 if (debug_execution
) {
1228 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
1230 /* Disable interrupts */
1231 /* We disable interrupts in the PRIMASK register instead of
1232 * masking with C_MASKINTS. This is probably the same issue
1233 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
1234 * in parallel with disabled interrupts can cause local faults
1237 * This breaks non-debug (application) execution if not
1238 * called from armv7m_start_algorithm() which saves registers.
1240 buf_set_u32(r
->value
, 0, 1, 1);
1244 /* Make sure we are in Thumb mode, set xPSR.T bit */
1245 /* armv7m_start_algorithm() initializes entire xPSR register.
1246 * This duplicity handles the case when cortex_m_resume()
1247 * is used with the debug_execution flag directly,
1248 * not called through armv7m_start_algorithm().
1250 r
= armv7m
->arm
.cpsr
;
1251 buf_set_u32(r
->value
, 24, 1, 1);
1256 /* current = 1: continue on current pc, otherwise continue at <address> */
1259 buf_set_u32(r
->value
, 0, 32, *address
);
1264 /* if we halted last time due to a bkpt instruction
1265 * then we have to manually step over it, otherwise
1266 * the core will break again */
1268 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
1269 && !debug_execution
)
1270 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
1272 resume_pc
= buf_get_u32(r
->value
, 0, 32);
1274 *address
= resume_pc
;
1276 int retval
= armv7m_restore_context(target
);
1277 if (retval
!= ERROR_OK
)
1280 /* the front-end may request us not to handle breakpoints */
1281 if (handle_breakpoints
) {
1282 /* Single step past breakpoint at current address */
1283 breakpoint
= breakpoint_find(target
, resume_pc
);
1285 LOG_TARGET_DEBUG(target
, "unset breakpoint at " TARGET_ADDR_FMT
" (ID: %" PRIu32
")",
1286 breakpoint
->address
,
1287 breakpoint
->unique_id
);
1288 retval
= cortex_m_unset_breakpoint(target
, breakpoint
);
1289 if (retval
== ERROR_OK
)
1290 retval
= cortex_m_single_step_core(target
);
1291 int ret2
= cortex_m_set_breakpoint(target
, breakpoint
);
1292 if (retval
!= ERROR_OK
)
1294 if (ret2
!= ERROR_OK
)
1302 static int cortex_m_restart_one(struct target
*target
, bool debug_execution
)
1304 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1307 cortex_m_set_maskints_for_run(target
);
1308 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1310 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1311 /* registers are now invalid */
1312 register_cache_invalidate(armv7m
->arm
.core_cache
);
1314 if (!debug_execution
) {
1315 target
->state
= TARGET_RUNNING
;
1316 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1318 target
->state
= TARGET_DEBUG_RUNNING
;
1319 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1325 static int cortex_m_restore_smp(struct target
*target
, bool handle_breakpoints
)
1327 struct target_list
*head
;
1328 target_addr_t address
;
1329 foreach_smp_target(head
, target
->smp_targets
) {
1330 struct target
*curr
= head
->target
;
1331 /* skip calling target */
1334 if (!target_was_examined(curr
))
1336 /* skip running targets */
1337 if (curr
->state
== TARGET_RUNNING
)
1340 int retval
= cortex_m_restore_one(curr
, true, &address
,
1341 handle_breakpoints
, false);
1342 if (retval
!= ERROR_OK
)
1345 retval
= cortex_m_restart_one(curr
, false);
1346 if (retval
!= ERROR_OK
)
1349 LOG_TARGET_DEBUG(curr
, "SMP resumed at " TARGET_ADDR_FMT
, address
);
1354 static int cortex_m_resume(struct target
*target
, int current
,
1355 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
1357 int retval
= cortex_m_restore_one(target
, !!current
, &address
, !!handle_breakpoints
, !!debug_execution
);
1358 if (retval
!= ERROR_OK
) {
1359 LOG_TARGET_ERROR(target
, "context restore failed, aborting resume");
1363 if (target
->smp
&& !debug_execution
) {
1364 retval
= cortex_m_restore_smp(target
, !!handle_breakpoints
);
1365 if (retval
!= ERROR_OK
)
1366 LOG_WARNING("resume of a SMP target failed, trying to resume current one");
1369 cortex_m_restart_one(target
, !!debug_execution
);
1370 if (retval
!= ERROR_OK
) {
1371 LOG_TARGET_ERROR(target
, "resume failed");
1375 LOG_TARGET_DEBUG(target
, "%sresumed at " TARGET_ADDR_FMT
,
1376 debug_execution
? "debug " : "", address
);
1381 /* int irqstepcount = 0; */
1382 static int cortex_m_step(struct target
*target
, int current
,
1383 target_addr_t address
, int handle_breakpoints
)
1385 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1386 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1387 struct breakpoint
*breakpoint
= NULL
;
1388 struct reg
*pc
= armv7m
->arm
.pc
;
1389 bool bkpt_inst_found
= false;
1391 bool isr_timed_out
= false;
1393 if (target
->state
!= TARGET_HALTED
) {
1394 LOG_TARGET_ERROR(target
, "not halted");
1395 return ERROR_TARGET_NOT_HALTED
;
1398 /* Just one of SMP cores will step. Set the gdb control
1399 * target to current one or gdb miss gdb-end event */
1400 if (target
->smp
&& target
->gdb_service
)
1401 target
->gdb_service
->target
= target
;
1403 /* current = 1: continue on current pc, otherwise continue at <address> */
1405 buf_set_u32(pc
->value
, 0, 32, address
);
1410 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
1412 /* the front-end may request us not to handle breakpoints */
1413 if (handle_breakpoints
) {
1414 breakpoint
= breakpoint_find(target
, pc_value
);
1416 cortex_m_unset_breakpoint(target
, breakpoint
);
1419 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
1421 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1423 armv7m_restore_context(target
);
1425 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1427 /* if no bkpt instruction is found at pc then we can perform
1428 * a normal step, otherwise we have to manually step over the bkpt
1429 * instruction - as such simulate a step */
1430 if (bkpt_inst_found
== false) {
1431 if (cortex_m
->isrmasking_mode
!= CORTEX_M_ISRMASK_AUTO
) {
1432 /* Automatic ISR masking mode off: Just step over the next
1433 * instruction, with interrupts on or off as appropriate. */
1434 cortex_m_set_maskints_for_step(target
);
1435 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1437 /* Process interrupts during stepping in a way they don't interfere
1442 * Set a temporary break point at the current pc and let the core run
1443 * with interrupts enabled. Pending interrupts get served and we run
1444 * into the breakpoint again afterwards. Then we step over the next
1445 * instruction with interrupts disabled.
1447 * If the pending interrupts don't complete within time, we leave the
1448 * core running. This may happen if the interrupts trigger faster
1449 * than the core can process them or the handler doesn't return.
1451 * If no more breakpoints are available we simply do a step with
1452 * interrupts enabled.
1458 * If a break point is already set on the lower half word then a break point on
1459 * the upper half word will not break again when the core is restarted. So we
1460 * just step over the instruction with interrupts disabled.
1462 * The documentation has no information about this, it was found by observation
1463 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
1464 * suffer from this problem.
1466 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
1467 * address has it always cleared. The former is done to indicate thumb mode
1471 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
1472 LOG_TARGET_DEBUG(target
, "Stepping over next instruction with interrupts disabled");
1473 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
1474 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1475 /* Re-enable interrupts if appropriate */
1476 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1477 cortex_m_set_maskints_for_halt(target
);
1480 /* Set a temporary break point */
1482 retval
= cortex_m_set_breakpoint(target
, breakpoint
);
1484 enum breakpoint_type type
= BKPT_HARD
;
1485 if (cortex_m
->fp_rev
== 0 && pc_value
> 0x1FFFFFFF) {
1486 /* FPB rev.1 cannot handle such addr, try BKPT instr */
1489 retval
= breakpoint_add(target
, pc_value
, 2, type
);
1492 bool tmp_bp_set
= (retval
== ERROR_OK
);
1494 /* No more breakpoints left, just do a step */
1496 cortex_m_set_maskints_for_step(target
);
1497 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1498 /* Re-enable interrupts if appropriate */
1499 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1500 cortex_m_set_maskints_for_halt(target
);
1502 /* Start the core */
1503 LOG_TARGET_DEBUG(target
, "Starting core to serve pending interrupts");
1504 int64_t t_start
= timeval_ms();
1505 cortex_m_set_maskints_for_run(target
);
1506 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
1508 /* Wait for pending handlers to complete or timeout */
1510 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
1511 if (retval
!= ERROR_OK
) {
1512 target
->state
= TARGET_UNKNOWN
;
1515 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
1516 } while (!((cortex_m
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
1518 /* only remove breakpoint if we created it */
1520 cortex_m_unset_breakpoint(target
, breakpoint
);
1522 /* Remove the temporary breakpoint */
1523 breakpoint_remove(target
, pc_value
);
1526 if (isr_timed_out
) {
1527 LOG_TARGET_DEBUG(target
, "Interrupt handlers didn't complete within time, "
1528 "leaving target running");
1530 /* Step over next instruction with interrupts disabled */
1531 cortex_m_set_maskints_for_step(target
);
1532 cortex_m_write_debug_halt_mask(target
,
1533 C_HALT
| C_MASKINTS
,
1535 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1536 /* Re-enable interrupts if appropriate */
1537 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1538 cortex_m_set_maskints_for_halt(target
);
1545 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
1546 if (retval
!= ERROR_OK
)
1549 /* registers are now invalid */
1550 register_cache_invalidate(armv7m
->arm
.core_cache
);
1553 cortex_m_set_breakpoint(target
, breakpoint
);
1555 if (isr_timed_out
) {
1556 /* Leave the core running. The user has to stop execution manually. */
1557 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1558 target
->state
= TARGET_RUNNING
;
1562 LOG_TARGET_DEBUG(target
, "target stepped dcb_dhcsr = 0x%" PRIx32
1563 " nvic_icsr = 0x%" PRIx32
,
1564 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1566 retval
= cortex_m_debug_entry(target
);
1567 if (retval
!= ERROR_OK
)
1569 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1571 LOG_TARGET_DEBUG(target
, "target stepped dcb_dhcsr = 0x%" PRIx32
1572 " nvic_icsr = 0x%" PRIx32
,
1573 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1578 static int cortex_m_assert_reset(struct target
*target
)
1580 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1581 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1582 enum cortex_m_soft_reset_config reset_config
= cortex_m
->soft_reset_config
;
1584 LOG_TARGET_DEBUG(target
, "target->state: %s,%s examined",
1585 target_state_name(target
),
1586 target_was_examined(target
) ? "" : " not");
1588 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1590 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
1591 /* allow scripts to override the reset event */
1593 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1594 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1595 target
->state
= TARGET_RESET
;
1600 /* some cores support connecting while srst is asserted
1601 * use that mode is it has been configured */
1603 bool srst_asserted
= false;
1605 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1606 ((jtag_reset_config
& RESET_SRST_NO_GATING
) || !armv7m
->debug_ap
)) {
1607 /* If we have no debug_ap, asserting SRST is the only thing
1609 adapter_assert_reset();
1610 srst_asserted
= true;
1613 /* TODO: replace the hack calling target_examine_one()
1614 * as soon as a better reset framework is available */
1615 if (!target_was_examined(target
) && !target
->defer_examine
1616 && srst_asserted
&& (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1617 LOG_TARGET_DEBUG(target
, "Trying to re-examine under reset");
1618 target_examine_one(target
);
1621 /* We need at least debug_ap to go further.
1622 * Inform user and bail out if we don't have one. */
1623 if (!armv7m
->debug_ap
) {
1624 if (srst_asserted
) {
1625 if (target
->reset_halt
)
1626 LOG_TARGET_ERROR(target
, "Debug AP not available, will not halt after reset!");
1628 /* Do not propagate error: reset was asserted, proceed to deassert! */
1629 target
->state
= TARGET_RESET
;
1630 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1634 LOG_TARGET_ERROR(target
, "Debug AP not available, reset NOT asserted!");
1639 /* Enable debug requests */
1640 int retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
1642 /* Store important errors instead of failing and proceed to reset assert */
1644 if (retval
!= ERROR_OK
|| !(cortex_m
->dcb_dhcsr
& C_DEBUGEN
))
1645 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
1647 /* If the processor is sleeping in a WFI or WFE instruction, the
1648 * C_HALT bit must be asserted to regain control */
1649 if (retval
== ERROR_OK
&& (cortex_m
->dcb_dhcsr
& S_SLEEP
))
1650 retval
= cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1652 mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
1653 /* Ignore less important errors */
1655 if (!target
->reset_halt
) {
1656 /* Set/Clear C_MASKINTS in a separate operation */
1657 cortex_m_set_maskints_for_run(target
);
1659 /* clear any debug flags before resuming */
1660 cortex_m_clear_halt(target
);
1662 /* clear C_HALT in dhcsr reg */
1663 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1665 /* Halt in debug on reset; endreset_event() restores DEMCR.
1667 * REVISIT catching BUSERR presumably helps to defend against
1668 * bad vector table entries. Should this include MMERR or
1672 retval2
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
,
1673 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1674 if (retval
!= ERROR_OK
|| retval2
!= ERROR_OK
)
1675 LOG_TARGET_INFO(target
, "AP write error, reset will not halt");
1678 if (jtag_reset_config
& RESET_HAS_SRST
) {
1679 /* default to asserting srst */
1681 adapter_assert_reset();
1683 /* srst is asserted, ignore AP access errors */
1686 /* Use a standard Cortex-M3 software reset mechanism.
1687 * We default to using VECTRESET as it is supported on all current cores
1688 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1689 * This has the disadvantage of not resetting the peripherals, so a
1690 * reset-init event handler is needed to perform any peripheral resets.
1692 if (!cortex_m
->vectreset_supported
1693 && reset_config
== CORTEX_M_RESET_VECTRESET
) {
1694 reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
1695 LOG_TARGET_WARNING(target
, "VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1696 LOG_TARGET_WARNING(target
, "Set 'cortex_m reset_config sysresetreq'.");
1699 LOG_TARGET_DEBUG(target
, "Using Cortex-M %s", (reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1700 ? "SYSRESETREQ" : "VECTRESET");
1702 if (reset_config
== CORTEX_M_RESET_VECTRESET
) {
1703 LOG_TARGET_WARNING(target
, "Only resetting the Cortex-M core, use a reset-init event "
1704 "handler to reset any peripherals or configure hardware srst support.");
1708 retval3
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
1709 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1710 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1711 if (retval3
!= ERROR_OK
)
1712 LOG_TARGET_DEBUG(target
, "Ignoring AP write error right after reset");
1714 retval3
= dap_dp_init_or_reconnect(armv7m
->debug_ap
->dap
);
1715 if (retval3
!= ERROR_OK
) {
1716 LOG_TARGET_ERROR(target
, "DP initialisation failed");
1717 /* The error return value must not be propagated in this case.
1718 * SYSRESETREQ or VECTRESET have been possibly triggered
1719 * so reset processing should continue */
1721 /* I do not know why this is necessary, but it
1722 * fixes strange effects (step/resume cause NMI
1723 * after reset) on LM3S6918 -- Michael Schwingen
1726 mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
, &tmp
);
1730 target
->state
= TARGET_RESET
;
1733 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1735 /* now return stored error code if any */
1736 if (retval
!= ERROR_OK
)
1739 if (target
->reset_halt
&& target_was_examined(target
)) {
1740 retval
= target_halt(target
);
1741 if (retval
!= ERROR_OK
)
1748 static int cortex_m_deassert_reset(struct target
*target
)
1750 struct armv7m_common
*armv7m
= &target_to_cm(target
)->armv7m
;
1752 LOG_TARGET_DEBUG(target
, "target->state: %s,%s examined",
1753 target_state_name(target
),
1754 target_was_examined(target
) ? "" : " not");
1756 /* deassert reset lines */
1757 adapter_deassert_reset();
1759 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1761 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1762 !(jtag_reset_config
& RESET_SRST_NO_GATING
) &&
1765 int retval
= dap_dp_init_or_reconnect(armv7m
->debug_ap
->dap
);
1766 if (retval
!= ERROR_OK
) {
1767 LOG_TARGET_ERROR(target
, "DP initialisation failed");
1775 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1778 unsigned int fp_num
= 0;
1779 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1780 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1782 if (breakpoint
->is_set
) {
1783 LOG_TARGET_WARNING(target
, "breakpoint (BPID: %" PRIu32
") already set", breakpoint
->unique_id
);
1787 if (breakpoint
->type
== BKPT_HARD
) {
1788 uint32_t fpcr_value
;
1789 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m
->fp_num_code
))
1791 if (fp_num
>= cortex_m
->fp_num_code
) {
1792 LOG_TARGET_ERROR(target
, "Can not find free FPB Comparator!");
1793 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1795 breakpoint_hw_set(breakpoint
, fp_num
);
1796 fpcr_value
= breakpoint
->address
| 1;
1797 if (cortex_m
->fp_rev
== 0) {
1798 if (breakpoint
->address
> 0x1FFFFFFF) {
1799 LOG_TARGET_ERROR(target
, "Cortex-M Flash Patch Breakpoint rev.1 "
1800 "cannot handle HW breakpoint above address 0x1FFFFFFE");
1804 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1805 fpcr_value
= (fpcr_value
& 0x1FFFFFFC) | hilo
| 1;
1806 } else if (cortex_m
->fp_rev
> 1) {
1807 LOG_TARGET_ERROR(target
, "Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1810 comparator_list
[fp_num
].used
= true;
1811 comparator_list
[fp_num
].fpcr_value
= fpcr_value
;
1812 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1813 comparator_list
[fp_num
].fpcr_value
);
1814 LOG_TARGET_DEBUG(target
, "fpc_num %i fpcr_value 0x%" PRIx32
"",
1816 comparator_list
[fp_num
].fpcr_value
);
1817 if (!cortex_m
->fpb_enabled
) {
1818 LOG_TARGET_DEBUG(target
, "FPB wasn't enabled, do it now");
1819 retval
= cortex_m_enable_fpb(target
);
1820 if (retval
!= ERROR_OK
) {
1821 LOG_TARGET_ERROR(target
, "Failed to enable the FPB");
1825 cortex_m
->fpb_enabled
= true;
1827 } else if (breakpoint
->type
== BKPT_SOFT
) {
1830 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1831 * semihosting; don't use that. Otherwise the BKPT
1832 * parameter is arbitrary.
1834 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1835 retval
= target_read_memory(target
,
1836 breakpoint
->address
& 0xFFFFFFFE,
1837 breakpoint
->length
, 1,
1838 breakpoint
->orig_instr
);
1839 if (retval
!= ERROR_OK
)
1841 retval
= target_write_memory(target
,
1842 breakpoint
->address
& 0xFFFFFFFE,
1843 breakpoint
->length
, 1,
1845 if (retval
!= ERROR_OK
)
1847 breakpoint
->is_set
= true;
1850 LOG_TARGET_DEBUG(target
, "BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (n=%u)",
1851 breakpoint
->unique_id
,
1852 (int)(breakpoint
->type
),
1853 breakpoint
->address
,
1855 (breakpoint
->type
== BKPT_SOFT
) ? 0 : breakpoint
->number
);
1860 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1863 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1864 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1866 if (!breakpoint
->is_set
) {
1867 LOG_TARGET_WARNING(target
, "breakpoint not set");
1871 LOG_TARGET_DEBUG(target
, "BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (n=%u)",
1872 breakpoint
->unique_id
,
1873 (int)(breakpoint
->type
),
1874 breakpoint
->address
,
1876 (breakpoint
->type
== BKPT_SOFT
) ? 0 : breakpoint
->number
);
1878 if (breakpoint
->type
== BKPT_HARD
) {
1879 unsigned int fp_num
= breakpoint
->number
;
1880 if (fp_num
>= cortex_m
->fp_num_code
) {
1881 LOG_TARGET_DEBUG(target
, "Invalid FP Comparator number in breakpoint");
1884 comparator_list
[fp_num
].used
= false;
1885 comparator_list
[fp_num
].fpcr_value
= 0;
1886 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1887 comparator_list
[fp_num
].fpcr_value
);
1889 /* restore original instruction (kept in target endianness) */
1890 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE,
1891 breakpoint
->length
, 1,
1892 breakpoint
->orig_instr
);
1893 if (retval
!= ERROR_OK
)
1896 breakpoint
->is_set
= false;
1901 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1903 if (breakpoint
->length
== 3) {
1904 LOG_TARGET_DEBUG(target
, "Using a two byte breakpoint for 32bit Thumb-2 request");
1905 breakpoint
->length
= 2;
1908 if ((breakpoint
->length
!= 2)) {
1909 LOG_TARGET_INFO(target
, "only breakpoints of two bytes length supported");
1910 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1913 return cortex_m_set_breakpoint(target
, breakpoint
);
1916 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1918 if (!breakpoint
->is_set
)
1921 return cortex_m_unset_breakpoint(target
, breakpoint
);
1924 static int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1926 unsigned int dwt_num
= 0;
1927 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1929 /* REVISIT Don't fully trust these "not used" records ... users
1930 * may set up breakpoints by hand, e.g. dual-address data value
1931 * watchpoint using comparator #1; comparator #0 matching cycle
1932 * count; send data trace info through ITM and TPIU; etc
1934 struct cortex_m_dwt_comparator
*comparator
;
1936 for (comparator
= cortex_m
->dwt_comparator_list
;
1937 comparator
->used
&& dwt_num
< cortex_m
->dwt_num_comp
;
1938 comparator
++, dwt_num
++)
1940 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
1941 LOG_TARGET_ERROR(target
, "Can not find free DWT Comparator");
1944 comparator
->used
= true;
1945 watchpoint_set(watchpoint
, dwt_num
);
1947 comparator
->comp
= watchpoint
->address
;
1948 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1951 if ((cortex_m
->dwt_devarch
& 0x1FFFFF) != DWT_DEVARCH_ARMV8M
) {
1952 uint32_t mask
= 0, temp
;
1954 /* watchpoint params were validated earlier */
1955 temp
= watchpoint
->length
;
1962 comparator
->mask
= mask
;
1963 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1966 switch (watchpoint
->rw
) {
1968 comparator
->function
= 5;
1971 comparator
->function
= 6;
1974 comparator
->function
= 7;
1978 uint32_t data_size
= watchpoint
->length
>> 1;
1979 comparator
->mask
= (watchpoint
->length
>> 1) | 1;
1981 switch (watchpoint
->rw
) {
1983 comparator
->function
= 4;
1986 comparator
->function
= 5;
1989 comparator
->function
= 6;
1992 comparator
->function
= comparator
->function
| (1 << 4) |
1996 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
1997 comparator
->function
);
1999 LOG_TARGET_DEBUG(target
, "Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
2000 watchpoint
->unique_id
, dwt_num
,
2001 (unsigned) comparator
->comp
,
2002 (unsigned) comparator
->mask
,
2003 (unsigned) comparator
->function
);
2007 static int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
2009 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2010 struct cortex_m_dwt_comparator
*comparator
;
2012 if (!watchpoint
->is_set
) {
2013 LOG_TARGET_WARNING(target
, "watchpoint (wpid: %d) not set",
2014 watchpoint
->unique_id
);
2018 unsigned int dwt_num
= watchpoint
->number
;
2020 LOG_TARGET_DEBUG(target
, "Watchpoint (ID %d) DWT%u address: 0x%08x clear",
2021 watchpoint
->unique_id
, dwt_num
,
2022 (unsigned) watchpoint
->address
);
2024 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
2025 LOG_TARGET_DEBUG(target
, "Invalid DWT Comparator number in watchpoint");
2029 comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
2030 comparator
->used
= false;
2031 comparator
->function
= 0;
2032 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
2033 comparator
->function
);
2035 watchpoint
->is_set
= false;
2040 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
2042 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2044 if (cortex_m
->dwt_comp_available
< 1) {
2045 LOG_TARGET_DEBUG(target
, "no comparators?");
2046 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2049 /* hardware doesn't support data value masking */
2050 if (watchpoint
->mask
!= ~(uint32_t)0) {
2051 LOG_TARGET_DEBUG(target
, "watchpoint value masks not supported");
2052 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2055 /* hardware allows address masks of up to 32K */
2058 for (mask
= 0; mask
< 16; mask
++) {
2059 if ((1u << mask
) == watchpoint
->length
)
2063 LOG_TARGET_DEBUG(target
, "unsupported watchpoint length");
2064 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2066 if (watchpoint
->address
& ((1 << mask
) - 1)) {
2067 LOG_TARGET_DEBUG(target
, "watchpoint address is unaligned");
2068 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2071 /* Caller doesn't seem to be able to describe watching for data
2072 * values of zero; that flags "no value".
2074 * REVISIT This DWT may well be able to watch for specific data
2075 * values. Requires comparator #1 to set DATAVMATCH and match
2076 * the data, and another comparator (DATAVADDR0) matching addr.
2078 if (watchpoint
->value
) {
2079 LOG_TARGET_DEBUG(target
, "data value watchpoint not YET supported");
2080 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2083 cortex_m
->dwt_comp_available
--;
2084 LOG_TARGET_DEBUG(target
, "dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
2089 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
2091 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2093 /* REVISIT why check? DWT can be updated with core running ... */
2094 if (target
->state
!= TARGET_HALTED
) {
2095 LOG_TARGET_ERROR(target
, "not halted");
2096 return ERROR_TARGET_NOT_HALTED
;
2099 if (watchpoint
->is_set
)
2100 cortex_m_unset_watchpoint(target
, watchpoint
);
2102 cortex_m
->dwt_comp_available
++;
2103 LOG_TARGET_DEBUG(target
, "dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
2108 static int cortex_m_hit_watchpoint(struct target
*target
, struct watchpoint
**hit_watchpoint
)
2110 if (target
->debug_reason
!= DBG_REASON_WATCHPOINT
)
2113 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2115 for (struct watchpoint
*wp
= target
->watchpoints
; wp
; wp
= wp
->next
) {
2119 unsigned int dwt_num
= wp
->number
;
2120 struct cortex_m_dwt_comparator
*comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
2122 uint32_t dwt_function
;
2123 int retval
= target_read_u32(target
, comparator
->dwt_comparator_address
+ 8, &dwt_function
);
2124 if (retval
!= ERROR_OK
)
2127 /* check the MATCHED bit */
2128 if (dwt_function
& BIT(24)) {
2129 *hit_watchpoint
= wp
;
2137 void cortex_m_enable_watchpoints(struct target
*target
)
2139 struct watchpoint
*watchpoint
= target
->watchpoints
;
2141 /* set any pending watchpoints */
2142 while (watchpoint
) {
2143 if (!watchpoint
->is_set
)
2144 cortex_m_set_watchpoint(target
, watchpoint
);
2145 watchpoint
= watchpoint
->next
;
2149 static int cortex_m_read_memory(struct target
*target
, target_addr_t address
,
2150 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2152 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2154 if (armv7m
->arm
.arch
== ARM_ARCH_V6M
) {
2155 /* armv6m does not handle unaligned memory access */
2156 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2157 return ERROR_TARGET_UNALIGNED_ACCESS
;
2160 return mem_ap_read_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
2163 static int cortex_m_write_memory(struct target
*target
, target_addr_t address
,
2164 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2166 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2168 if (armv7m
->arm
.arch
== ARM_ARCH_V6M
) {
2169 /* armv6m does not handle unaligned memory access */
2170 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2171 return ERROR_TARGET_UNALIGNED_ACCESS
;
2174 return mem_ap_write_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
2177 static int cortex_m_init_target(struct command_context
*cmd_ctx
,
2178 struct target
*target
)
2180 armv7m_build_reg_cache(target
);
2181 arm_semihosting_init(target
);
2185 void cortex_m_deinit_target(struct target
*target
)
2187 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2188 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2190 if (!armv7m
->is_hla_target
&& armv7m
->debug_ap
)
2191 dap_put_ap(armv7m
->debug_ap
);
2193 free(cortex_m
->fp_comparator_list
);
2195 cortex_m_dwt_free(target
);
2196 armv7m_free_reg_cache(target
);
2198 free(target
->private_config
);
2202 int cortex_m_profiling(struct target
*target
, uint32_t *samples
,
2203 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
)
2205 struct timeval timeout
, now
;
2206 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2210 retval
= target_read_u32(target
, DWT_PCSR
, ®_value
);
2211 if (retval
!= ERROR_OK
) {
2212 LOG_TARGET_ERROR(target
, "Error while reading PCSR");
2215 if (reg_value
== 0) {
2216 LOG_TARGET_INFO(target
, "PCSR sampling not supported on this processor.");
2217 return target_profiling_default(target
, samples
, max_num_samples
, num_samples
, seconds
);
2220 gettimeofday(&timeout
, NULL
);
2221 timeval_add_time(&timeout
, seconds
, 0);
2223 LOG_TARGET_INFO(target
, "Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
2225 /* Make sure the target is running */
2226 target_poll(target
);
2227 if (target
->state
== TARGET_HALTED
)
2228 retval
= target_resume(target
, 1, 0, 0, 0);
2230 if (retval
!= ERROR_OK
) {
2231 LOG_TARGET_ERROR(target
, "Error while resuming target");
2235 uint32_t sample_count
= 0;
2238 if (armv7m
&& armv7m
->debug_ap
) {
2239 uint32_t read_count
= max_num_samples
- sample_count
;
2240 if (read_count
> 1024)
2243 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
,
2244 (void *)&samples
[sample_count
],
2245 4, read_count
, DWT_PCSR
);
2246 sample_count
+= read_count
;
2248 target_read_u32(target
, DWT_PCSR
, &samples
[sample_count
++]);
2251 if (retval
!= ERROR_OK
) {
2252 LOG_TARGET_ERROR(target
, "Error while reading PCSR");
2257 gettimeofday(&now
, NULL
);
2258 if (sample_count
>= max_num_samples
|| timeval_compare(&now
, &timeout
) > 0) {
2259 LOG_TARGET_INFO(target
, "Profiling completed. %" PRIu32
" samples.", sample_count
);
2264 *num_samples
= sample_count
;
2269 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
2270 * on r/w if the core is not running, and clear on resume or reset ... or
2271 * at least, in a post_restore_context() method.
2274 struct dwt_reg_state
{
2275 struct target
*target
;
2277 uint8_t value
[4]; /* scratch/cache */
2280 static int cortex_m_dwt_get_reg(struct reg
*reg
)
2282 struct dwt_reg_state
*state
= reg
->arch_info
;
2285 int retval
= target_read_u32(state
->target
, state
->addr
, &tmp
);
2286 if (retval
!= ERROR_OK
)
2289 buf_set_u32(state
->value
, 0, 32, tmp
);
2293 static int cortex_m_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
2295 struct dwt_reg_state
*state
= reg
->arch_info
;
2297 return target_write_u32(state
->target
, state
->addr
,
2298 buf_get_u32(buf
, 0, reg
->size
));
2307 static const struct dwt_reg dwt_base_regs
[] = {
2308 { DWT_CTRL
, "dwt_ctrl", 32, },
2309 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
2310 * increments while the core is asleep.
2312 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
2313 /* plus some 8 bit counters, useful for profiling with TPIU */
2316 static const struct dwt_reg dwt_comp
[] = {
2317 #define DWT_COMPARATOR(i) \
2318 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
2319 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
2320 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
2337 #undef DWT_COMPARATOR
2340 static const struct reg_arch_type dwt_reg_type
= {
2341 .get
= cortex_m_dwt_get_reg
,
2342 .set
= cortex_m_dwt_set_reg
,
2345 static void cortex_m_dwt_addreg(struct target
*t
, struct reg
*r
, const struct dwt_reg
*d
)
2347 struct dwt_reg_state
*state
;
2349 state
= calloc(1, sizeof(*state
));
2352 state
->addr
= d
->addr
;
2357 r
->value
= state
->value
;
2358 r
->arch_info
= state
;
2359 r
->type
= &dwt_reg_type
;
2362 static void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
)
2365 struct reg_cache
*cache
;
2366 struct cortex_m_dwt_comparator
*comparator
;
2369 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
2370 LOG_TARGET_DEBUG(target
, "DWT_CTRL: 0x%" PRIx32
, dwtcr
);
2372 LOG_TARGET_DEBUG(target
, "no DWT");
2376 target_read_u32(target
, DWT_DEVARCH
, &cm
->dwt_devarch
);
2377 LOG_TARGET_DEBUG(target
, "DWT_DEVARCH: 0x%" PRIx32
, cm
->dwt_devarch
);
2379 cm
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
2380 cm
->dwt_comp_available
= cm
->dwt_num_comp
;
2381 cm
->dwt_comparator_list
= calloc(cm
->dwt_num_comp
,
2382 sizeof(struct cortex_m_dwt_comparator
));
2383 if (!cm
->dwt_comparator_list
) {
2385 cm
->dwt_num_comp
= 0;
2386 LOG_TARGET_ERROR(target
, "out of mem");
2390 cache
= calloc(1, sizeof(*cache
));
2393 free(cm
->dwt_comparator_list
);
2396 cache
->name
= "Cortex-M DWT registers";
2397 cache
->num_regs
= 2 + cm
->dwt_num_comp
* 3;
2398 cache
->reg_list
= calloc(cache
->num_regs
, sizeof(*cache
->reg_list
));
2399 if (!cache
->reg_list
) {
2404 for (reg
= 0; reg
< 2; reg
++)
2405 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2406 dwt_base_regs
+ reg
);
2408 comparator
= cm
->dwt_comparator_list
;
2409 for (unsigned int i
= 0; i
< cm
->dwt_num_comp
; i
++, comparator
++) {
2412 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
2413 for (j
= 0; j
< 3; j
++, reg
++)
2414 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2415 dwt_comp
+ 3 * i
+ j
);
2417 /* make sure we clear any watchpoints enabled on the target */
2418 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
2421 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
2422 cm
->dwt_cache
= cache
;
2424 LOG_TARGET_DEBUG(target
, "DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
2425 dwtcr
, cm
->dwt_num_comp
,
2426 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
2428 /* REVISIT: if num_comp > 1, check whether comparator #1 can
2429 * implement single-address data value watchpoints ... so we
2430 * won't need to check it later, when asked to set one up.
2434 static void cortex_m_dwt_free(struct target
*target
)
2436 struct cortex_m_common
*cm
= target_to_cm(target
);
2437 struct reg_cache
*cache
= cm
->dwt_cache
;
2439 free(cm
->dwt_comparator_list
);
2440 cm
->dwt_comparator_list
= NULL
;
2441 cm
->dwt_num_comp
= 0;
2444 register_unlink_cache(&target
->reg_cache
, cache
);
2446 if (cache
->reg_list
) {
2447 for (size_t i
= 0; i
< cache
->num_regs
; i
++)
2448 free(cache
->reg_list
[i
].arch_info
);
2449 free(cache
->reg_list
);
2453 cm
->dwt_cache
= NULL
;
2456 static bool cortex_m_has_tz(struct target
*target
)
2458 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2459 uint32_t dauthstatus
;
2461 if (armv7m
->arm
.arch
!= ARM_ARCH_V8M
)
2464 int retval
= target_read_u32(target
, DAUTHSTATUS
, &dauthstatus
);
2465 if (retval
!= ERROR_OK
) {
2466 LOG_WARNING("Error reading DAUTHSTATUS register");
2469 return (dauthstatus
& DAUTHSTATUS_SID_MASK
) != 0;
2472 #define MVFR0 0xe000ef40
2473 #define MVFR1 0xe000ef44
2475 #define MVFR0_DEFAULT_M4 0x10110021
2476 #define MVFR1_DEFAULT_M4 0x11000011
2478 #define MVFR0_DEFAULT_M7_SP 0x10110021
2479 #define MVFR0_DEFAULT_M7_DP 0x10110221
2480 #define MVFR1_DEFAULT_M7_SP 0x11000011
2481 #define MVFR1_DEFAULT_M7_DP 0x12000011
2483 static int cortex_m_find_mem_ap(struct adiv5_dap
*swjdp
,
2484 struct adiv5_ap
**debug_ap
)
2486 if (dap_find_get_ap(swjdp
, AP_TYPE_AHB3_AP
, debug_ap
) == ERROR_OK
)
2489 return dap_find_get_ap(swjdp
, AP_TYPE_AHB5_AP
, debug_ap
);
2492 int cortex_m_examine(struct target
*target
)
2495 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
2496 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2497 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
2498 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2500 /* hla_target shares the examine handler but does not support
2502 if (!armv7m
->is_hla_target
) {
2503 if (!armv7m
->debug_ap
) {
2504 if (cortex_m
->apsel
== DP_APSEL_INVALID
) {
2505 /* Search for the MEM-AP */
2506 retval
= cortex_m_find_mem_ap(swjdp
, &armv7m
->debug_ap
);
2507 if (retval
!= ERROR_OK
) {
2508 LOG_TARGET_ERROR(target
, "Could not find MEM-AP to control the core");
2512 armv7m
->debug_ap
= dap_get_ap(swjdp
, cortex_m
->apsel
);
2513 if (!armv7m
->debug_ap
) {
2514 LOG_ERROR("Cannot get AP");
2520 armv7m
->debug_ap
->memaccess_tck
= 8;
2522 retval
= mem_ap_init(armv7m
->debug_ap
);
2523 if (retval
!= ERROR_OK
)
2527 if (!target_was_examined(target
)) {
2528 target_set_examined(target
);
2530 /* Read from Device Identification Registers */
2531 retval
= target_read_u32(target
, CPUID
, &cpuid
);
2532 if (retval
!= ERROR_OK
)
2535 /* Get ARCH and CPU types */
2536 const enum cortex_m_partno core_partno
= (cpuid
& ARM_CPUID_PARTNO_MASK
) >> ARM_CPUID_PARTNO_POS
;
2538 for (unsigned int n
= 0; n
< ARRAY_SIZE(cortex_m_parts
); n
++) {
2539 if (core_partno
== cortex_m_parts
[n
].partno
) {
2540 cortex_m
->core_info
= &cortex_m_parts
[n
];
2545 if (!cortex_m
->core_info
) {
2546 LOG_TARGET_ERROR(target
, "Cortex-M PARTNO 0x%x is unrecognized", core_partno
);
2550 armv7m
->arm
.arch
= cortex_m
->core_info
->arch
;
2552 LOG_TARGET_INFO(target
, "%s r%" PRId8
"p%" PRId8
" processor detected",
2553 cortex_m
->core_info
->name
,
2554 (uint8_t)((cpuid
>> 20) & 0xf),
2555 (uint8_t)((cpuid
>> 0) & 0xf));
2557 cortex_m
->maskints_erratum
= false;
2558 if (core_partno
== CORTEX_M7_PARTNO
) {
2560 rev
= (cpuid
>> 20) & 0xf;
2561 patch
= (cpuid
>> 0) & 0xf;
2562 if ((rev
== 0) && (patch
< 2)) {
2563 LOG_TARGET_WARNING(target
, "Silicon bug: single stepping may enter pending exception handler!");
2564 cortex_m
->maskints_erratum
= true;
2567 LOG_TARGET_DEBUG(target
, "cpuid: 0x%8.8" PRIx32
"", cpuid
);
2569 if (cortex_m
->core_info
->flags
& CORTEX_M_F_HAS_FPV4
) {
2570 target_read_u32(target
, MVFR0
, &mvfr0
);
2571 target_read_u32(target
, MVFR1
, &mvfr1
);
2573 /* test for floating point feature on Cortex-M4 */
2574 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
2575 LOG_TARGET_DEBUG(target
, "%s floating point feature FPv4_SP found", cortex_m
->core_info
->name
);
2576 armv7m
->fp_feature
= FPV4_SP
;
2578 } else if (cortex_m
->core_info
->flags
& CORTEX_M_F_HAS_FPV5
) {
2579 target_read_u32(target
, MVFR0
, &mvfr0
);
2580 target_read_u32(target
, MVFR1
, &mvfr1
);
2582 /* test for floating point features on Cortex-M7 */
2583 if ((mvfr0
== MVFR0_DEFAULT_M7_SP
) && (mvfr1
== MVFR1_DEFAULT_M7_SP
)) {
2584 LOG_TARGET_DEBUG(target
, "%s floating point feature FPv5_SP found", cortex_m
->core_info
->name
);
2585 armv7m
->fp_feature
= FPV5_SP
;
2586 } else if ((mvfr0
== MVFR0_DEFAULT_M7_DP
) && (mvfr1
== MVFR1_DEFAULT_M7_DP
)) {
2587 LOG_TARGET_DEBUG(target
, "%s floating point feature FPv5_DP found", cortex_m
->core_info
->name
);
2588 armv7m
->fp_feature
= FPV5_DP
;
2592 /* VECTRESET is supported only on ARMv7-M cores */
2593 cortex_m
->vectreset_supported
= armv7m
->arm
.arch
== ARM_ARCH_V7M
;
2595 /* Check for FPU, otherwise mark FPU register as non-existent */
2596 if (armv7m
->fp_feature
== FP_NONE
)
2597 for (size_t idx
= ARMV7M_FPU_FIRST_REG
; idx
<= ARMV7M_FPU_LAST_REG
; idx
++)
2598 armv7m
->arm
.core_cache
->reg_list
[idx
].exist
= false;
2600 if (!cortex_m_has_tz(target
))
2601 for (size_t idx
= ARMV8M_FIRST_REG
; idx
<= ARMV8M_LAST_REG
; idx
++)
2602 armv7m
->arm
.core_cache
->reg_list
[idx
].exist
= false;
2604 if (!armv7m
->is_hla_target
) {
2605 if (cortex_m
->core_info
->flags
& CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K
)
2606 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2607 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2608 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 12);
2611 retval
= target_read_u32(target
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
2612 if (retval
!= ERROR_OK
)
2615 /* Don't cumulate sticky S_RESET_ST at the very first read of DHCSR
2616 * as S_RESET_ST may indicate a reset that happened long time ago
2617 * (most probably the power-on reset before OpenOCD was started).
2618 * As we are just initializing the debug system we do not need
2619 * to call cortex_m_endreset_event() in the following poll.
2621 if (!cortex_m
->dcb_dhcsr_sticky_is_recent
) {
2622 cortex_m
->dcb_dhcsr_sticky_is_recent
= true;
2623 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
2624 LOG_TARGET_DEBUG(target
, "reset happened some time ago, ignore");
2625 cortex_m
->dcb_dhcsr
&= ~S_RESET_ST
;
2628 cortex_m_cumulate_dhcsr_sticky(cortex_m
, cortex_m
->dcb_dhcsr
);
2630 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
2631 /* Enable debug requests */
2632 uint32_t dhcsr
= (cortex_m
->dcb_dhcsr
| C_DEBUGEN
) & ~(C_HALT
| C_STEP
| C_MASKINTS
);
2634 retval
= target_write_u32(target
, DCB_DHCSR
, DBGKEY
| (dhcsr
& 0x0000FFFFUL
));
2635 if (retval
!= ERROR_OK
)
2637 cortex_m
->dcb_dhcsr
= dhcsr
;
2640 /* Configure trace modules */
2641 retval
= target_write_u32(target
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
2642 if (retval
!= ERROR_OK
)
2645 if (armv7m
->trace_config
.itm_deferred_config
)
2646 armv7m_trace_itm_config(target
);
2648 /* NOTE: FPB and DWT are both optional. */
2651 target_read_u32(target
, FP_CTRL
, &fpcr
);
2652 /* bits [14:12] and [7:4] */
2653 cortex_m
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF);
2654 cortex_m
->fp_num_lit
= (fpcr
>> 8) & 0xF;
2655 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2656 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2657 cortex_m
->fp_rev
= (fpcr
>> 28) & 0xf;
2658 free(cortex_m
->fp_comparator_list
);
2659 cortex_m
->fp_comparator_list
= calloc(
2660 cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
,
2661 sizeof(struct cortex_m_fp_comparator
));
2662 cortex_m
->fpb_enabled
= fpcr
& 1;
2663 for (unsigned int i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
2664 cortex_m
->fp_comparator_list
[i
].type
=
2665 (i
< cortex_m
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
2666 cortex_m
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
2668 /* make sure we clear any breakpoints enabled on the target */
2669 target_write_u32(target
, cortex_m
->fp_comparator_list
[i
].fpcr_address
, 0);
2671 LOG_TARGET_DEBUG(target
, "FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
2673 cortex_m
->fp_num_code
,
2674 cortex_m
->fp_num_lit
);
2677 cortex_m_dwt_free(target
);
2678 cortex_m_dwt_setup(cortex_m
, target
);
2680 /* These hardware breakpoints only work for code in flash! */
2681 LOG_TARGET_INFO(target
, "target has %d breakpoints, %d watchpoints",
2682 cortex_m
->fp_num_code
,
2683 cortex_m
->dwt_num_comp
);
2689 static int cortex_m_dcc_read(struct target
*target
, uint8_t *value
, uint8_t *ctrl
)
2691 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2696 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2697 if (retval
!= ERROR_OK
)
2700 dcrdr
= target_buffer_get_u16(target
, buf
);
2701 *ctrl
= (uint8_t)dcrdr
;
2702 *value
= (uint8_t)(dcrdr
>> 8);
2704 LOG_TARGET_DEBUG(target
, "data 0x%x ctrl 0x%x", *value
, *ctrl
);
2706 /* write ack back to software dcc register
2707 * signify we have read data */
2708 if (dcrdr
& (1 << 0)) {
2709 target_buffer_set_u16(target
, buf
, 0);
2710 retval
= mem_ap_write_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2711 if (retval
!= ERROR_OK
)
2718 static int cortex_m_target_request_data(struct target
*target
,
2719 uint32_t size
, uint8_t *buffer
)
2725 for (i
= 0; i
< (size
* 4); i
++) {
2726 int retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2727 if (retval
!= ERROR_OK
)
2735 static int cortex_m_handle_target_request(void *priv
)
2737 struct target
*target
= priv
;
2738 if (!target_was_examined(target
))
2741 if (!target
->dbg_msg_enabled
)
2744 if (target
->state
== TARGET_RUNNING
) {
2749 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2750 if (retval
!= ERROR_OK
)
2753 /* check if we have data */
2754 if (ctrl
& (1 << 0)) {
2757 /* we assume target is quick enough */
2759 for (int i
= 1; i
<= 3; i
++) {
2760 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2761 if (retval
!= ERROR_OK
)
2763 request
|= ((uint32_t)data
<< (i
* 8));
2765 target_request(target
, request
);
2772 static int cortex_m_init_arch_info(struct target
*target
,
2773 struct cortex_m_common
*cortex_m
, struct adiv5_dap
*dap
)
2775 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2777 armv7m_init_arch_info(target
, armv7m
);
2779 /* default reset mode is to use srst if fitted
2780 * if not it will use CORTEX_M3_RESET_VECTRESET */
2781 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2783 armv7m
->arm
.dap
= dap
;
2785 /* register arch-specific functions */
2786 armv7m
->examine_debug_reason
= cortex_m_examine_debug_reason
;
2788 armv7m
->post_debug_entry
= NULL
;
2790 armv7m
->pre_restore_context
= NULL
;
2792 armv7m
->load_core_reg_u32
= cortex_m_load_core_reg_u32
;
2793 armv7m
->store_core_reg_u32
= cortex_m_store_core_reg_u32
;
2795 target_register_timer_callback(cortex_m_handle_target_request
, 1,
2796 TARGET_TIMER_TYPE_PERIODIC
, target
);
2801 static int cortex_m_target_create(struct target
*target
, Jim_Interp
*interp
)
2803 struct adiv5_private_config
*pc
;
2805 pc
= (struct adiv5_private_config
*)target
->private_config
;
2806 if (adiv5_verify_config(pc
) != ERROR_OK
)
2809 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
2811 LOG_TARGET_ERROR(target
, "No memory creating target");
2815 cortex_m
->common_magic
= CORTEX_M_COMMON_MAGIC
;
2816 cortex_m
->apsel
= pc
->ap_num
;
2818 cortex_m_init_arch_info(target
, cortex_m
, pc
->dap
);
2823 /*--------------------------------------------------------------------------*/
2825 static int cortex_m_verify_pointer(struct command_invocation
*cmd
,
2826 struct cortex_m_common
*cm
)
2828 if (!is_cortex_m_with_dap_access(cm
)) {
2829 command_print(cmd
, "target is not a Cortex-M");
2830 return ERROR_TARGET_INVALID
;
2836 * Only stuff below this line should need to verify that its target
2837 * is a Cortex-M3. Everything else should have indirected through the
2838 * cortexm3_target structure, which is only used with CM3 targets.
2841 COMMAND_HANDLER(handle_cortex_m_vector_catch_command
)
2843 struct target
*target
= get_current_target(CMD_CTX
);
2844 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2845 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2849 static const struct {
2853 { "hard_err", VC_HARDERR
, },
2854 { "int_err", VC_INTERR
, },
2855 { "bus_err", VC_BUSERR
, },
2856 { "state_err", VC_STATERR
, },
2857 { "chk_err", VC_CHKERR
, },
2858 { "nocp_err", VC_NOCPERR
, },
2859 { "mm_err", VC_MMERR
, },
2860 { "reset", VC_CORERESET
, },
2863 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2864 if (retval
!= ERROR_OK
)
2867 if (!target_was_examined(target
)) {
2868 LOG_TARGET_ERROR(target
, "Target not examined yet");
2872 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2873 if (retval
!= ERROR_OK
)
2879 if (CMD_ARGC
== 1) {
2880 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2881 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2882 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2883 | VC_MMERR
| VC_CORERESET
;
2885 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2888 while (CMD_ARGC
-- > 0) {
2890 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2891 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2893 catch |= vec_ids
[i
].mask
;
2896 if (i
== ARRAY_SIZE(vec_ids
)) {
2897 LOG_TARGET_ERROR(target
, "No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2898 return ERROR_COMMAND_SYNTAX_ERROR
;
2902 /* For now, armv7m->demcr only stores vector catch flags. */
2903 armv7m
->demcr
= catch;
2908 /* write, but don't assume it stuck (why not??) */
2909 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, demcr
);
2910 if (retval
!= ERROR_OK
)
2912 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2913 if (retval
!= ERROR_OK
)
2916 /* FIXME be sure to clear DEMCR on clean server shutdown.
2917 * Otherwise the vector catch hardware could fire when there's
2918 * no debugger hooked up, causing much confusion...
2922 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2923 command_print(CMD
, "%9s: %s", vec_ids
[i
].name
,
2924 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2930 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command
)
2932 struct target
*target
= get_current_target(CMD_CTX
);
2933 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2936 static const struct nvp nvp_maskisr_modes
[] = {
2937 { .name
= "auto", .value
= CORTEX_M_ISRMASK_AUTO
},
2938 { .name
= "off", .value
= CORTEX_M_ISRMASK_OFF
},
2939 { .name
= "on", .value
= CORTEX_M_ISRMASK_ON
},
2940 { .name
= "steponly", .value
= CORTEX_M_ISRMASK_STEPONLY
},
2941 { .name
= NULL
, .value
= -1 },
2943 const struct nvp
*n
;
2946 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2947 if (retval
!= ERROR_OK
)
2950 if (target
->state
!= TARGET_HALTED
) {
2951 command_print(CMD
, "Error: target must be stopped for \"%s\" command", CMD_NAME
);
2952 return ERROR_TARGET_NOT_HALTED
;
2956 n
= nvp_name2value(nvp_maskisr_modes
, CMD_ARGV
[0]);
2958 return ERROR_COMMAND_SYNTAX_ERROR
;
2959 cortex_m
->isrmasking_mode
= n
->value
;
2960 cortex_m_set_maskints_for_halt(target
);
2963 n
= nvp_value2name(nvp_maskisr_modes
, cortex_m
->isrmasking_mode
);
2964 command_print(CMD
, "cortex_m interrupt mask %s", n
->name
);
2969 COMMAND_HANDLER(handle_cortex_m_reset_config_command
)
2971 struct target
*target
= get_current_target(CMD_CTX
);
2972 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2976 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2977 if (retval
!= ERROR_OK
)
2981 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2982 cortex_m
->soft_reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
2984 else if (strcmp(*CMD_ARGV
, "vectreset") == 0) {
2985 if (target_was_examined(target
)
2986 && !cortex_m
->vectreset_supported
)
2987 LOG_TARGET_WARNING(target
, "VECTRESET is not supported on your Cortex-M core!");
2989 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2992 return ERROR_COMMAND_SYNTAX_ERROR
;
2995 switch (cortex_m
->soft_reset_config
) {
2996 case CORTEX_M_RESET_SYSRESETREQ
:
2997 reset_config
= "sysresetreq";
3000 case CORTEX_M_RESET_VECTRESET
:
3001 reset_config
= "vectreset";
3005 reset_config
= "unknown";
3009 command_print(CMD
, "cortex_m reset_config %s", reset_config
);
3014 static const struct command_registration cortex_m_exec_command_handlers
[] = {
3017 .handler
= handle_cortex_m_mask_interrupts_command
,
3018 .mode
= COMMAND_EXEC
,
3019 .help
= "mask cortex_m interrupts",
3020 .usage
= "['auto'|'on'|'off'|'steponly']",
3023 .name
= "vector_catch",
3024 .handler
= handle_cortex_m_vector_catch_command
,
3025 .mode
= COMMAND_EXEC
,
3026 .help
= "configure hardware vectors to trigger debug entry",
3027 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
3030 .name
= "reset_config",
3031 .handler
= handle_cortex_m_reset_config_command
,
3032 .mode
= COMMAND_ANY
,
3033 .help
= "configure software reset handling",
3034 .usage
= "['sysresetreq'|'vectreset']",
3037 .chain
= smp_command_handlers
,
3039 COMMAND_REGISTRATION_DONE
3041 static const struct command_registration cortex_m_command_handlers
[] = {
3043 .chain
= armv7m_command_handlers
,
3046 .chain
= armv7m_trace_command_handlers
,
3048 /* START_DEPRECATED_TPIU */
3050 .chain
= arm_tpiu_deprecated_command_handlers
,
3052 /* END_DEPRECATED_TPIU */
3055 .mode
= COMMAND_EXEC
,
3056 .help
= "Cortex-M command group",
3058 .chain
= cortex_m_exec_command_handlers
,
3061 .chain
= rtt_target_command_handlers
,
3063 COMMAND_REGISTRATION_DONE
3066 struct target_type cortexm_target
= {
3069 .poll
= cortex_m_poll
,
3070 .arch_state
= armv7m_arch_state
,
3072 .target_request_data
= cortex_m_target_request_data
,
3074 .halt
= cortex_m_halt
,
3075 .resume
= cortex_m_resume
,
3076 .step
= cortex_m_step
,
3078 .assert_reset
= cortex_m_assert_reset
,
3079 .deassert_reset
= cortex_m_deassert_reset
,
3080 .soft_reset_halt
= cortex_m_soft_reset_halt
,
3082 .get_gdb_arch
= arm_get_gdb_arch
,
3083 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
3085 .read_memory
= cortex_m_read_memory
,
3086 .write_memory
= cortex_m_write_memory
,
3087 .checksum_memory
= armv7m_checksum_memory
,
3088 .blank_check_memory
= armv7m_blank_check_memory
,
3090 .run_algorithm
= armv7m_run_algorithm
,
3091 .start_algorithm
= armv7m_start_algorithm
,
3092 .wait_algorithm
= armv7m_wait_algorithm
,
3094 .add_breakpoint
= cortex_m_add_breakpoint
,
3095 .remove_breakpoint
= cortex_m_remove_breakpoint
,
3096 .add_watchpoint
= cortex_m_add_watchpoint
,
3097 .remove_watchpoint
= cortex_m_remove_watchpoint
,
3098 .hit_watchpoint
= cortex_m_hit_watchpoint
,
3100 .commands
= cortex_m_command_handlers
,
3101 .target_create
= cortex_m_target_create
,
3102 .target_jim_configure
= adiv5_jim_configure
,
3103 .init_target
= cortex_m_init_target
,
3104 .examine
= cortex_m_examine
,
3105 .deinit_target
= cortex_m_deinit_target
,
3107 .profiling
= cortex_m_profiling
,