1 // SPDX-License-Identifier: GPL-2.0-or-later
3 /***************************************************************************
4 * Copyright (C) 2005 by Dominic Rath *
5 * Dominic.Rath@gmx.de *
7 * Copyright (C) 2006 by Magnus Lundin *
10 * Copyright (C) 2008 by Spencer Oliver *
11 * spen@spen-soft.co.uk *
14 * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) *
16 ***************************************************************************/
21 #include "jtag/interface.h"
22 #include "breakpoints.h"
24 #include "target_request.h"
25 #include "target_type.h"
26 #include "arm_adi_v5.h"
27 #include "arm_disassembler.h"
29 #include "arm_opcodes.h"
30 #include "arm_semihosting.h"
32 #include <helper/nvp.h>
33 #include <helper/time_support.h>
36 /* NOTE: most of this should work fine for the Cortex-M1 and
37 * Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
38 * Some differences: M0/M1 doesn't have FPB remapping or the
39 * DWT tracing/profiling support. (So the cycle counter will
40 * not be usable; the other stuff isn't currently used here.)
42 * Although there are some workarounds for errata seen only in r0p0
43 * silicon, such old parts are hard to find and thus not much tested
47 /* Timeout for register r/w */
48 #define DHCSR_S_REGRDY_TIMEOUT (500)
50 /* Supported Cortex-M Cores */
51 static const struct cortex_m_part_info cortex_m_parts
[] = {
53 .impl_part
= CORTEX_M0_PARTNO
,
58 .impl_part
= CORTEX_M0P_PARTNO
,
63 .impl_part
= CORTEX_M1_PARTNO
,
68 .impl_part
= CORTEX_M3_PARTNO
,
71 .flags
= CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K
,
74 .impl_part
= CORTEX_M4_PARTNO
,
77 .flags
= CORTEX_M_F_HAS_FPV4
| CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K
,
80 .impl_part
= CORTEX_M7_PARTNO
,
83 .flags
= CORTEX_M_F_HAS_FPV5
,
86 .impl_part
= CORTEX_M23_PARTNO
,
91 .impl_part
= CORTEX_M33_PARTNO
,
94 .flags
= CORTEX_M_F_HAS_FPV5
,
97 .impl_part
= CORTEX_M35P_PARTNO
,
98 .name
= "Cortex-M35P",
100 .flags
= CORTEX_M_F_HAS_FPV5
,
103 .impl_part
= CORTEX_M55_PARTNO
,
104 .name
= "Cortex-M55",
105 .arch
= ARM_ARCH_V8M
,
106 .flags
= CORTEX_M_F_HAS_FPV5
,
109 .impl_part
= STAR_MC1_PARTNO
,
111 .arch
= ARM_ARCH_V8M
,
112 .flags
= CORTEX_M_F_HAS_FPV5
,
115 .impl_part
= REALTEK_M200_PARTNO
,
116 .name
= "Real-M200 (KM0)",
117 .arch
= ARM_ARCH_V8M
,
120 .impl_part
= REALTEK_M300_PARTNO
,
121 .name
= "Real-M300 (KM4)",
122 .arch
= ARM_ARCH_V8M
,
123 .flags
= CORTEX_M_F_HAS_FPV5
,
127 /* forward declarations */
128 static int cortex_m_store_core_reg_u32(struct target
*target
,
129 uint32_t num
, uint32_t value
);
130 static void cortex_m_dwt_free(struct target
*target
);
132 /** DCB DHCSR register contains S_RETIRE_ST and S_RESET_ST bits cleared
133 * on a read. Call this helper function each time DHCSR is read
134 * to preserve S_RESET_ST state in case of a reset event was detected.
136 static inline void cortex_m_cumulate_dhcsr_sticky(struct cortex_m_common
*cortex_m
,
139 cortex_m
->dcb_dhcsr_cumulated_sticky
|= dhcsr
;
142 /** Read DCB DHCSR register to cortex_m->dcb_dhcsr and cumulate
143 * sticky bits in cortex_m->dcb_dhcsr_cumulated_sticky
145 static int cortex_m_read_dhcsr_atomic_sticky(struct target
*target
)
147 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
148 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
150 int retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
,
151 &cortex_m
->dcb_dhcsr
);
152 if (retval
!= ERROR_OK
)
155 cortex_m_cumulate_dhcsr_sticky(cortex_m
, cortex_m
->dcb_dhcsr
);
159 static int cortex_m_load_core_reg_u32(struct target
*target
,
160 uint32_t regsel
, uint32_t *value
)
162 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
163 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
165 uint32_t dcrdr
, tmp_value
;
168 /* because the DCB_DCRDR is used for the emulated dcc channel
169 * we have to save/restore the DCB_DCRDR when used */
170 if (target
->dbg_msg_enabled
) {
171 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
172 if (retval
!= ERROR_OK
)
176 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regsel
);
177 if (retval
!= ERROR_OK
)
180 /* check if value from register is ready and pre-read it */
183 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DHCSR
,
184 &cortex_m
->dcb_dhcsr
);
185 if (retval
!= ERROR_OK
)
187 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
,
189 if (retval
!= ERROR_OK
)
191 cortex_m_cumulate_dhcsr_sticky(cortex_m
, cortex_m
->dcb_dhcsr
);
192 if (cortex_m
->dcb_dhcsr
& S_REGRDY
)
194 cortex_m
->slow_register_read
= true; /* Polling (still) needed. */
195 if (timeval_ms() > then
+ DHCSR_S_REGRDY_TIMEOUT
) {
196 LOG_TARGET_ERROR(target
, "Timeout waiting for DCRDR transfer ready");
197 return ERROR_TIMEOUT_REACHED
;
204 if (target
->dbg_msg_enabled
) {
205 /* restore DCB_DCRDR - this needs to be in a separate
206 * transaction otherwise the emulated DCC channel breaks */
207 if (retval
== ERROR_OK
)
208 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
214 static int cortex_m_slow_read_all_regs(struct target
*target
)
216 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
217 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
218 const unsigned int num_regs
= armv7m
->arm
.core_cache
->num_regs
;
220 /* Opportunistically restore fast read, it'll revert to slow
221 * if any register needed polling in cortex_m_load_core_reg_u32(). */
222 cortex_m
->slow_register_read
= false;
224 for (unsigned int reg_id
= 0; reg_id
< num_regs
; reg_id
++) {
225 struct reg
*r
= &armv7m
->arm
.core_cache
->reg_list
[reg_id
];
227 int retval
= armv7m
->arm
.read_core_reg(target
, r
, reg_id
, ARM_MODE_ANY
);
228 if (retval
!= ERROR_OK
)
233 if (!cortex_m
->slow_register_read
)
234 LOG_TARGET_DEBUG(target
, "Switching back to fast register reads");
239 static int cortex_m_queue_reg_read(struct target
*target
, uint32_t regsel
,
240 uint32_t *reg_value
, uint32_t *dhcsr
)
242 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
245 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regsel
);
246 if (retval
!= ERROR_OK
)
249 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DHCSR
, dhcsr
);
250 if (retval
!= ERROR_OK
)
253 return mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, reg_value
);
256 static int cortex_m_fast_read_all_regs(struct target
*target
)
258 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
259 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
263 /* because the DCB_DCRDR is used for the emulated dcc channel
264 * we have to save/restore the DCB_DCRDR when used */
265 if (target
->dbg_msg_enabled
) {
266 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
267 if (retval
!= ERROR_OK
)
271 const unsigned int num_regs
= armv7m
->arm
.core_cache
->num_regs
;
272 const unsigned int n_r32
= ARMV7M_LAST_REG
- ARMV7M_CORE_FIRST_REG
+ 1
273 + ARMV7M_FPU_LAST_REG
- ARMV7M_FPU_FIRST_REG
+ 1;
274 /* we need one 32-bit word for each register except FP D0..D15, which
276 uint32_t r_vals
[n_r32
];
277 uint32_t dhcsr
[n_r32
];
279 unsigned int wi
= 0; /* write index to r_vals and dhcsr arrays */
280 unsigned int reg_id
; /* register index in the reg_list, ARMV7M_R0... */
281 for (reg_id
= 0; reg_id
< num_regs
; reg_id
++) {
282 struct reg
*r
= &armv7m
->arm
.core_cache
->reg_list
[reg_id
];
284 continue; /* skip non existent registers */
287 /* Any 8-bit or shorter register is unpacked from a 32-bit
288 * container register. Skip it now. */
292 uint32_t regsel
= armv7m_map_id_to_regsel(reg_id
);
293 retval
= cortex_m_queue_reg_read(target
, regsel
, &r_vals
[wi
],
295 if (retval
!= ERROR_OK
)
299 assert(r
->size
== 32 || r
->size
== 64);
301 continue; /* done with 32-bit register */
303 assert(reg_id
>= ARMV7M_FPU_FIRST_REG
&& reg_id
<= ARMV7M_FPU_LAST_REG
);
304 /* the odd part of FP register (S1, S3...) */
305 retval
= cortex_m_queue_reg_read(target
, regsel
+ 1, &r_vals
[wi
],
307 if (retval
!= ERROR_OK
)
314 retval
= dap_run(armv7m
->debug_ap
->dap
);
315 if (retval
!= ERROR_OK
)
318 if (target
->dbg_msg_enabled
) {
319 /* restore DCB_DCRDR - this needs to be in a separate
320 * transaction otherwise the emulated DCC channel breaks */
321 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
322 if (retval
!= ERROR_OK
)
326 bool not_ready
= false;
327 for (unsigned int i
= 0; i
< wi
; i
++) {
328 if ((dhcsr
[i
] & S_REGRDY
) == 0) {
330 LOG_TARGET_DEBUG(target
, "Register %u was not ready during fast read", i
);
332 cortex_m_cumulate_dhcsr_sticky(cortex_m
, dhcsr
[i
]);
336 /* Any register was not ready,
337 * fall back to slow read with S_REGRDY polling */
338 return ERROR_TIMEOUT_REACHED
;
341 LOG_TARGET_DEBUG(target
, "read %u 32-bit registers", wi
);
343 unsigned int ri
= 0; /* read index from r_vals array */
344 for (reg_id
= 0; reg_id
< num_regs
; reg_id
++) {
345 struct reg
*r
= &armv7m
->arm
.core_cache
->reg_list
[reg_id
];
347 continue; /* skip non existent registers */
351 unsigned int reg32_id
;
353 if (armv7m_map_reg_packing(reg_id
, ®32_id
, &offset
)) {
354 /* Unpack a partial register from 32-bit container register */
355 struct reg
*r32
= &armv7m
->arm
.core_cache
->reg_list
[reg32_id
];
357 /* The container register ought to precede all regs unpacked
358 * from it in the reg_list. So the value should be ready
361 buf_cpy(r32
->value
+ offset
, r
->value
, r
->size
);
364 assert(r
->size
== 32 || r
->size
== 64);
365 buf_set_u32(r
->value
, 0, 32, r_vals
[ri
++]);
368 assert(reg_id
>= ARMV7M_FPU_FIRST_REG
&& reg_id
<= ARMV7M_FPU_LAST_REG
);
369 /* the odd part of FP register (S1, S3...) */
370 buf_set_u32(r
->value
+ 4, 0, 32, r_vals
[ri
++]);
380 static int cortex_m_store_core_reg_u32(struct target
*target
,
381 uint32_t regsel
, uint32_t value
)
383 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
384 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
389 /* because the DCB_DCRDR is used for the emulated dcc channel
390 * we have to save/restore the DCB_DCRDR when used */
391 if (target
->dbg_msg_enabled
) {
392 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DCRDR
, &dcrdr
);
393 if (retval
!= ERROR_OK
)
397 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, value
);
398 if (retval
!= ERROR_OK
)
401 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRSR
, regsel
| DCRSR_WNR
);
402 if (retval
!= ERROR_OK
)
405 /* check if value is written into register */
408 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
409 if (retval
!= ERROR_OK
)
411 if (cortex_m
->dcb_dhcsr
& S_REGRDY
)
413 if (timeval_ms() > then
+ DHCSR_S_REGRDY_TIMEOUT
) {
414 LOG_TARGET_ERROR(target
, "Timeout waiting for DCRDR transfer ready");
415 return ERROR_TIMEOUT_REACHED
;
420 if (target
->dbg_msg_enabled
) {
421 /* restore DCB_DCRDR - this needs to be in a separate
422 * transaction otherwise the emulated DCC channel breaks */
423 if (retval
== ERROR_OK
)
424 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DCRDR
, dcrdr
);
430 static int cortex_m_write_debug_halt_mask(struct target
*target
,
431 uint32_t mask_on
, uint32_t mask_off
)
433 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
434 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
436 /* mask off status bits */
437 cortex_m
->dcb_dhcsr
&= ~((0xFFFFul
<< 16) | mask_off
);
438 /* create new register mask */
439 cortex_m
->dcb_dhcsr
|= DBGKEY
| C_DEBUGEN
| mask_on
;
441 return mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DHCSR
, cortex_m
->dcb_dhcsr
);
444 static int cortex_m_set_maskints(struct target
*target
, bool mask
)
446 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
447 if (!!(cortex_m
->dcb_dhcsr
& C_MASKINTS
) != mask
)
448 return cortex_m_write_debug_halt_mask(target
, mask
? C_MASKINTS
: 0, mask
? 0 : C_MASKINTS
);
453 static int cortex_m_set_maskints_for_halt(struct target
*target
)
455 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
456 switch (cortex_m
->isrmasking_mode
) {
457 case CORTEX_M_ISRMASK_AUTO
:
458 /* interrupts taken at resume, whether for step or run -> no mask */
459 return cortex_m_set_maskints(target
, false);
461 case CORTEX_M_ISRMASK_OFF
:
462 /* interrupts never masked */
463 return cortex_m_set_maskints(target
, false);
465 case CORTEX_M_ISRMASK_ON
:
466 /* interrupts always masked */
467 return cortex_m_set_maskints(target
, true);
469 case CORTEX_M_ISRMASK_STEPONLY
:
470 /* interrupts masked for single step only -> mask now if MASKINTS
471 * erratum, otherwise only mask before stepping */
472 return cortex_m_set_maskints(target
, cortex_m
->maskints_erratum
);
477 static int cortex_m_set_maskints_for_run(struct target
*target
)
479 switch (target_to_cm(target
)->isrmasking_mode
) {
480 case CORTEX_M_ISRMASK_AUTO
:
481 /* interrupts taken at resume, whether for step or run -> no mask */
482 return cortex_m_set_maskints(target
, false);
484 case CORTEX_M_ISRMASK_OFF
:
485 /* interrupts never masked */
486 return cortex_m_set_maskints(target
, false);
488 case CORTEX_M_ISRMASK_ON
:
489 /* interrupts always masked */
490 return cortex_m_set_maskints(target
, true);
492 case CORTEX_M_ISRMASK_STEPONLY
:
493 /* interrupts masked for single step only -> no mask */
494 return cortex_m_set_maskints(target
, false);
499 static int cortex_m_set_maskints_for_step(struct target
*target
)
501 switch (target_to_cm(target
)->isrmasking_mode
) {
502 case CORTEX_M_ISRMASK_AUTO
:
503 /* the auto-interrupt should already be done -> mask */
504 return cortex_m_set_maskints(target
, true);
506 case CORTEX_M_ISRMASK_OFF
:
507 /* interrupts never masked */
508 return cortex_m_set_maskints(target
, false);
510 case CORTEX_M_ISRMASK_ON
:
511 /* interrupts always masked */
512 return cortex_m_set_maskints(target
, true);
514 case CORTEX_M_ISRMASK_STEPONLY
:
515 /* interrupts masked for single step only -> mask */
516 return cortex_m_set_maskints(target
, true);
521 static int cortex_m_clear_halt(struct target
*target
)
523 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
524 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
527 /* clear step if any */
528 cortex_m_write_debug_halt_mask(target
, C_HALT
, C_STEP
);
530 /* Read Debug Fault Status Register */
531 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, &cortex_m
->nvic_dfsr
);
532 if (retval
!= ERROR_OK
)
535 /* Clear Debug Fault Status */
536 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
, cortex_m
->nvic_dfsr
);
537 if (retval
!= ERROR_OK
)
539 LOG_TARGET_DEBUG(target
, "NVIC_DFSR 0x%" PRIx32
"", cortex_m
->nvic_dfsr
);
544 static int cortex_m_single_step_core(struct target
*target
)
546 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
549 /* Mask interrupts before clearing halt, if not done already. This avoids
550 * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
551 * HALT can put the core into an unknown state.
553 if (!(cortex_m
->dcb_dhcsr
& C_MASKINTS
)) {
554 retval
= cortex_m_write_debug_halt_mask(target
, C_MASKINTS
, 0);
555 if (retval
!= ERROR_OK
)
558 retval
= cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
559 if (retval
!= ERROR_OK
)
561 LOG_TARGET_DEBUG(target
, "single step");
563 /* restore dhcsr reg */
564 cortex_m_clear_halt(target
);
569 static int cortex_m_enable_fpb(struct target
*target
)
571 int retval
= target_write_u32(target
, FP_CTRL
, 3);
572 if (retval
!= ERROR_OK
)
575 /* check the fpb is actually enabled */
577 retval
= target_read_u32(target
, FP_CTRL
, &fpctrl
);
578 if (retval
!= ERROR_OK
)
587 static int cortex_m_endreset_event(struct target
*target
)
591 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
592 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
593 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
594 struct cortex_m_fp_comparator
*fp_list
= cortex_m
->fp_comparator_list
;
595 struct cortex_m_dwt_comparator
*dwt_list
= cortex_m
->dwt_comparator_list
;
597 /* REVISIT The four debug monitor bits are currently ignored... */
598 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &dcb_demcr
);
599 if (retval
!= ERROR_OK
)
601 LOG_TARGET_DEBUG(target
, "DCB_DEMCR = 0x%8.8" PRIx32
"", dcb_demcr
);
603 /* this register is used for emulated dcc channel */
604 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
605 if (retval
!= ERROR_OK
)
608 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
609 if (retval
!= ERROR_OK
)
612 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
613 /* Enable debug requests */
614 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
615 if (retval
!= ERROR_OK
)
619 /* Restore proper interrupt masking setting for running CPU. */
620 cortex_m_set_maskints_for_run(target
);
622 /* Enable features controlled by ITM and DWT blocks, and catch only
623 * the vectors we were told to pay attention to.
625 * Target firmware is responsible for all fault handling policy
626 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
627 * or manual updates to the NVIC SHCSR and CCR registers.
629 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
630 if (retval
!= ERROR_OK
)
633 /* Paranoia: evidently some (early?) chips don't preserve all the
634 * debug state (including FPB, DWT, etc) across reset...
638 retval
= cortex_m_enable_fpb(target
);
639 if (retval
!= ERROR_OK
) {
640 LOG_TARGET_ERROR(target
, "Failed to enable the FPB");
644 cortex_m
->fpb_enabled
= true;
646 /* Restore FPB registers */
647 for (unsigned int i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
648 retval
= target_write_u32(target
, fp_list
[i
].fpcr_address
, fp_list
[i
].fpcr_value
);
649 if (retval
!= ERROR_OK
)
653 /* Restore DWT registers */
654 for (unsigned int i
= 0; i
< cortex_m
->dwt_num_comp
; i
++) {
655 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 0,
657 if (retval
!= ERROR_OK
)
659 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 4,
661 if (retval
!= ERROR_OK
)
663 retval
= target_write_u32(target
, dwt_list
[i
].dwt_comparator_address
+ 8,
664 dwt_list
[i
].function
);
665 if (retval
!= ERROR_OK
)
668 retval
= dap_run(swjdp
);
669 if (retval
!= ERROR_OK
)
672 register_cache_invalidate(armv7m
->arm
.core_cache
);
674 /* TODO: invalidate also working areas (needed in the case of detected reset).
675 * Doing so will require flash drivers to test if working area
676 * is still valid in all target algo calling loops.
679 /* make sure we have latest dhcsr flags */
680 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
681 if (retval
!= ERROR_OK
)
687 static int cortex_m_examine_debug_reason(struct target
*target
)
689 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
691 /* THIS IS NOT GOOD, TODO - better logic for detection of debug state reason
692 * only check the debug reason if we don't know it already */
694 if ((target
->debug_reason
!= DBG_REASON_DBGRQ
)
695 && (target
->debug_reason
!= DBG_REASON_SINGLESTEP
)) {
696 if (cortex_m
->nvic_dfsr
& DFSR_BKPT
) {
697 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
698 if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
699 target
->debug_reason
= DBG_REASON_WPTANDBKPT
;
700 } else if (cortex_m
->nvic_dfsr
& DFSR_DWTTRAP
)
701 target
->debug_reason
= DBG_REASON_WATCHPOINT
;
702 else if (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)
703 target
->debug_reason
= DBG_REASON_BREAKPOINT
;
704 else if (cortex_m
->nvic_dfsr
& DFSR_EXTERNAL
)
705 target
->debug_reason
= DBG_REASON_DBGRQ
;
707 target
->debug_reason
= DBG_REASON_UNDEFINED
;
713 static int cortex_m_examine_exception_reason(struct target
*target
)
715 uint32_t shcsr
= 0, except_sr
= 0, cfsr
= -1, except_ar
= -1;
716 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
717 struct adiv5_dap
*swjdp
= armv7m
->arm
.dap
;
720 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SHCSR
, &shcsr
);
721 if (retval
!= ERROR_OK
)
723 switch (armv7m
->exception_number
) {
726 case 3: /* Hard Fault */
727 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_HFSR
, &except_sr
);
728 if (retval
!= ERROR_OK
)
730 if (except_sr
& 0x40000000) {
731 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &cfsr
);
732 if (retval
!= ERROR_OK
)
736 case 4: /* Memory Management */
737 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
738 if (retval
!= ERROR_OK
)
740 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_MMFAR
, &except_ar
);
741 if (retval
!= ERROR_OK
)
744 case 5: /* Bus Fault */
745 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
746 if (retval
!= ERROR_OK
)
748 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_BFAR
, &except_ar
);
749 if (retval
!= ERROR_OK
)
752 case 6: /* Usage Fault */
753 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_CFSR
, &except_sr
);
754 if (retval
!= ERROR_OK
)
757 case 7: /* Secure Fault */
758 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SFSR
, &except_sr
);
759 if (retval
!= ERROR_OK
)
761 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_SFAR
, &except_ar
);
762 if (retval
!= ERROR_OK
)
765 case 11: /* SVCall */
767 case 12: /* Debug Monitor */
768 retval
= mem_ap_read_u32(armv7m
->debug_ap
, NVIC_DFSR
, &except_sr
);
769 if (retval
!= ERROR_OK
)
772 case 14: /* PendSV */
774 case 15: /* SysTick */
780 retval
= dap_run(swjdp
);
781 if (retval
== ERROR_OK
)
782 LOG_TARGET_DEBUG(target
, "%s SHCSR 0x%" PRIx32
", SR 0x%" PRIx32
783 ", CFSR 0x%" PRIx32
", AR 0x%" PRIx32
,
784 armv7m_exception_string(armv7m
->exception_number
),
785 shcsr
, except_sr
, cfsr
, except_ar
);
789 static int cortex_m_debug_entry(struct target
*target
)
793 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
794 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
795 struct arm
*arm
= &armv7m
->arm
;
798 LOG_TARGET_DEBUG(target
, " ");
800 /* Do this really early to minimize the window where the MASKINTS erratum
801 * can pile up pending interrupts. */
802 cortex_m_set_maskints_for_halt(target
);
804 cortex_m_clear_halt(target
);
806 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
807 if (retval
!= ERROR_OK
)
810 retval
= armv7m
->examine_debug_reason(target
);
811 if (retval
!= ERROR_OK
)
814 /* examine PE security state */
816 if (armv7m
->arm
.arch
== ARM_ARCH_V8M
) {
817 retval
= mem_ap_read_u32(armv7m
->debug_ap
, DCB_DSCSR
, &dscsr
);
818 if (retval
!= ERROR_OK
)
822 /* Load all registers to arm.core_cache */
823 if (!cortex_m
->slow_register_read
) {
824 retval
= cortex_m_fast_read_all_regs(target
);
825 if (retval
== ERROR_TIMEOUT_REACHED
) {
826 cortex_m
->slow_register_read
= true;
827 LOG_TARGET_DEBUG(target
, "Switched to slow register read");
831 if (cortex_m
->slow_register_read
)
832 retval
= cortex_m_slow_read_all_regs(target
);
834 if (retval
!= ERROR_OK
)
838 xpsr
= buf_get_u32(r
->value
, 0, 32);
840 /* Are we in an exception handler */
842 armv7m
->exception_number
= (xpsr
& 0x1FF);
844 arm
->core_mode
= ARM_MODE_HANDLER
;
845 arm
->map
= armv7m_msp_reg_map
;
847 unsigned control
= buf_get_u32(arm
->core_cache
848 ->reg_list
[ARMV7M_CONTROL
].value
, 0, 3);
850 /* is this thread privileged? */
851 arm
->core_mode
= control
& 1
852 ? ARM_MODE_USER_THREAD
855 /* which stack is it using? */
857 arm
->map
= armv7m_psp_reg_map
;
859 arm
->map
= armv7m_msp_reg_map
;
861 armv7m
->exception_number
= 0;
864 if (armv7m
->exception_number
)
865 cortex_m_examine_exception_reason(target
);
867 bool secure_state
= (dscsr
& DSCSR_CDS
) == DSCSR_CDS
;
868 LOG_TARGET_DEBUG(target
, "entered debug state in core mode: %s at PC 0x%" PRIx32
869 ", cpu in %s state, target->state: %s",
870 arm_mode_name(arm
->core_mode
),
871 buf_get_u32(arm
->pc
->value
, 0, 32),
872 secure_state
? "Secure" : "Non-Secure",
873 target_state_name(target
));
875 if (armv7m
->post_debug_entry
) {
876 retval
= armv7m
->post_debug_entry(target
);
877 if (retval
!= ERROR_OK
)
884 static int cortex_m_poll_one(struct target
*target
)
886 int detected_failure
= ERROR_OK
;
887 int retval
= ERROR_OK
;
888 enum target_state prev_target_state
= target
->state
;
889 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
890 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
892 /* Read from Debug Halting Control and Status Register */
893 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
894 if (retval
!= ERROR_OK
) {
895 target
->state
= TARGET_UNKNOWN
;
899 /* Recover from lockup. See ARMv7-M architecture spec,
900 * section B1.5.15 "Unrecoverable exception cases".
902 if (cortex_m
->dcb_dhcsr
& S_LOCKUP
) {
903 LOG_TARGET_ERROR(target
, "clearing lockup after double fault");
904 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
905 target
->debug_reason
= DBG_REASON_DBGRQ
;
907 /* We have to execute the rest (the "finally" equivalent, but
908 * still throw this exception again).
910 detected_failure
= ERROR_FAIL
;
912 /* refresh status bits */
913 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
914 if (retval
!= ERROR_OK
)
918 if (cortex_m
->dcb_dhcsr_cumulated_sticky
& S_RESET_ST
) {
919 cortex_m
->dcb_dhcsr_cumulated_sticky
&= ~S_RESET_ST
;
920 if (target
->state
!= TARGET_RESET
) {
921 target
->state
= TARGET_RESET
;
922 LOG_TARGET_INFO(target
, "external reset detected");
927 if (target
->state
== TARGET_RESET
) {
928 /* Cannot switch context while running so endreset is
929 * called with target->state == TARGET_RESET
931 LOG_TARGET_DEBUG(target
, "Exit from reset with dcb_dhcsr 0x%" PRIx32
,
932 cortex_m
->dcb_dhcsr
);
933 retval
= cortex_m_endreset_event(target
);
934 if (retval
!= ERROR_OK
) {
935 target
->state
= TARGET_UNKNOWN
;
938 target
->state
= TARGET_RUNNING
;
939 prev_target_state
= TARGET_RUNNING
;
942 if (cortex_m
->dcb_dhcsr
& S_HALT
) {
943 target
->state
= TARGET_HALTED
;
945 if ((prev_target_state
== TARGET_RUNNING
) || (prev_target_state
== TARGET_RESET
)) {
946 retval
= cortex_m_debug_entry(target
);
948 /* arm_semihosting needs to know registers, don't run if debug entry returned error */
949 if (retval
== ERROR_OK
&& arm_semihosting(target
, &retval
) != 0)
953 LOG_TARGET_DEBUG(target
, "postpone target event 'halted'");
954 target
->smp_halt_event_postponed
= true;
956 /* regardless of errors returned in previous code update state */
957 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
960 if (prev_target_state
== TARGET_DEBUG_RUNNING
) {
961 retval
= cortex_m_debug_entry(target
);
963 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_HALTED
);
965 if (retval
!= ERROR_OK
)
969 if (target
->state
== TARGET_UNKNOWN
) {
970 /* Check if processor is retiring instructions or sleeping.
971 * Unlike S_RESET_ST here we test if the target *is* running now,
972 * not if it has been running (possibly in the past). Instructions are
973 * typically processed much faster than OpenOCD polls DHCSR so S_RETIRE_ST
974 * is read always 1. That's the reason not to use dcb_dhcsr_cumulated_sticky.
976 if (cortex_m
->dcb_dhcsr
& S_RETIRE_ST
|| cortex_m
->dcb_dhcsr
& S_SLEEP
) {
977 target
->state
= TARGET_RUNNING
;
982 /* Check that target is truly halted, since the target could be resumed externally */
983 if ((prev_target_state
== TARGET_HALTED
) && !(cortex_m
->dcb_dhcsr
& S_HALT
)) {
984 /* registers are now invalid */
985 register_cache_invalidate(armv7m
->arm
.core_cache
);
987 target
->state
= TARGET_RUNNING
;
988 LOG_TARGET_WARNING(target
, "external resume detected");
989 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
993 /* Did we detect a failure condition that we cleared? */
994 if (detected_failure
!= ERROR_OK
)
995 retval
= detected_failure
;
999 static int cortex_m_halt_one(struct target
*target
);
1001 static int cortex_m_smp_halt_all(struct list_head
*smp_targets
)
1003 int retval
= ERROR_OK
;
1004 struct target_list
*head
;
1006 foreach_smp_target(head
, smp_targets
) {
1007 struct target
*curr
= head
->target
;
1008 if (!target_was_examined(curr
))
1010 if (curr
->state
== TARGET_HALTED
)
1013 int ret2
= cortex_m_halt_one(curr
);
1014 if (retval
== ERROR_OK
)
1015 retval
= ret2
; /* store the first error code ignore others */
1020 static int cortex_m_smp_post_halt_poll(struct list_head
*smp_targets
)
1022 int retval
= ERROR_OK
;
1023 struct target_list
*head
;
1025 foreach_smp_target(head
, smp_targets
) {
1026 struct target
*curr
= head
->target
;
1027 if (!target_was_examined(curr
))
1029 /* skip targets that were already halted */
1030 if (curr
->state
== TARGET_HALTED
)
1033 int ret2
= cortex_m_poll_one(curr
);
1034 if (retval
== ERROR_OK
)
1035 retval
= ret2
; /* store the first error code ignore others */
1040 static int cortex_m_poll_smp(struct list_head
*smp_targets
)
1042 int retval
= ERROR_OK
;
1043 struct target_list
*head
;
1044 bool halted
= false;
1046 foreach_smp_target(head
, smp_targets
) {
1047 struct target
*curr
= head
->target
;
1048 if (curr
->smp_halt_event_postponed
) {
1055 retval
= cortex_m_smp_halt_all(smp_targets
);
1057 int ret2
= cortex_m_smp_post_halt_poll(smp_targets
);
1058 if (retval
== ERROR_OK
)
1059 retval
= ret2
; /* store the first error code ignore others */
1061 foreach_smp_target(head
, smp_targets
) {
1062 struct target
*curr
= head
->target
;
1063 if (!curr
->smp_halt_event_postponed
)
1066 curr
->smp_halt_event_postponed
= false;
1067 if (curr
->state
== TARGET_HALTED
) {
1068 LOG_TARGET_DEBUG(curr
, "sending postponed target event 'halted'");
1069 target_call_event_callbacks(curr
, TARGET_EVENT_HALTED
);
1072 /* There is no need to set gdb_service->target
1073 * as hwthread_update_threads() selects an interesting thread
1080 static int cortex_m_poll(struct target
*target
)
1082 int retval
= cortex_m_poll_one(target
);
1085 struct target_list
*last
;
1086 last
= list_last_entry(target
->smp_targets
, struct target_list
, lh
);
1087 if (target
== last
->target
)
1088 /* After the last target in SMP group has been polled
1089 * check for postponed halted events and eventually halt and re-poll
1091 cortex_m_poll_smp(target
->smp_targets
);
1096 static int cortex_m_halt_one(struct target
*target
)
1098 LOG_TARGET_DEBUG(target
, "target->state: %s", target_state_name(target
));
1100 if (target
->state
== TARGET_HALTED
) {
1101 LOG_TARGET_DEBUG(target
, "target was already halted");
1105 if (target
->state
== TARGET_UNKNOWN
)
1106 LOG_TARGET_WARNING(target
, "target was in unknown state when halt was requested");
1108 if (target
->state
== TARGET_RESET
) {
1109 if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST
) && jtag_get_srst()) {
1110 LOG_TARGET_ERROR(target
, "can't request a halt while in reset if nSRST pulls nTRST");
1111 return ERROR_TARGET_FAILURE
;
1113 /* we came here in a reset_halt or reset_init sequence
1114 * debug entry was already prepared in cortex_m3_assert_reset()
1116 target
->debug_reason
= DBG_REASON_DBGRQ
;
1122 /* Write to Debug Halting Control and Status Register */
1123 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1125 /* Do this really early to minimize the window where the MASKINTS erratum
1126 * can pile up pending interrupts. */
1127 cortex_m_set_maskints_for_halt(target
);
1129 target
->debug_reason
= DBG_REASON_DBGRQ
;
1134 static int cortex_m_halt(struct target
*target
)
1137 return cortex_m_smp_halt_all(target
->smp_targets
);
1139 return cortex_m_halt_one(target
);
1142 static int cortex_m_soft_reset_halt(struct target
*target
)
1144 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1145 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1146 int retval
, timeout
= 0;
1148 /* on single cortex_m MCU soft_reset_halt should be avoided as same functionality
1149 * can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
1150 * As this reset only uses VC_CORERESET it would only ever reset the cortex_m
1151 * core, not the peripherals */
1152 LOG_TARGET_DEBUG(target
, "soft_reset_halt is discouraged, please use 'reset halt' instead.");
1154 if (!cortex_m
->vectreset_supported
) {
1155 LOG_TARGET_ERROR(target
, "VECTRESET is not supported on this Cortex-M core");
1160 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_STEP
| C_MASKINTS
);
1161 if (retval
!= ERROR_OK
)
1164 /* Enter debug state on reset; restore DEMCR in endreset_event() */
1165 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
,
1166 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1167 if (retval
!= ERROR_OK
)
1170 /* Request a core-only reset */
1171 retval
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
1172 AIRCR_VECTKEY
| AIRCR_VECTRESET
);
1173 if (retval
!= ERROR_OK
)
1175 target
->state
= TARGET_RESET
;
1177 /* registers are now invalid */
1178 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1180 while (timeout
< 100) {
1181 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
1182 if (retval
== ERROR_OK
) {
1183 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_DFSR
,
1184 &cortex_m
->nvic_dfsr
);
1185 if (retval
!= ERROR_OK
)
1187 if ((cortex_m
->dcb_dhcsr
& S_HALT
)
1188 && (cortex_m
->nvic_dfsr
& DFSR_VCATCH
)) {
1189 LOG_TARGET_DEBUG(target
, "system reset-halted, DHCSR 0x%08" PRIx32
", DFSR 0x%08" PRIx32
,
1190 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_dfsr
);
1191 cortex_m_poll(target
);
1192 /* FIXME restore user's vector catch config */
1195 LOG_TARGET_DEBUG(target
, "waiting for system reset-halt, "
1196 "DHCSR 0x%08" PRIx32
", %d ms",
1197 cortex_m
->dcb_dhcsr
, timeout
);
1207 void cortex_m_enable_breakpoints(struct target
*target
)
1209 struct breakpoint
*breakpoint
= target
->breakpoints
;
1211 /* set any pending breakpoints */
1212 while (breakpoint
) {
1213 if (!breakpoint
->is_set
)
1214 cortex_m_set_breakpoint(target
, breakpoint
);
1215 breakpoint
= breakpoint
->next
;
1219 static int cortex_m_restore_one(struct target
*target
, bool current
,
1220 target_addr_t
*address
, bool handle_breakpoints
, bool debug_execution
)
1222 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1223 struct breakpoint
*breakpoint
= NULL
;
1227 if (target
->state
!= TARGET_HALTED
) {
1228 LOG_TARGET_ERROR(target
, "not halted");
1229 return ERROR_TARGET_NOT_HALTED
;
1232 if (!debug_execution
) {
1233 target_free_all_working_areas(target
);
1234 cortex_m_enable_breakpoints(target
);
1235 cortex_m_enable_watchpoints(target
);
1238 if (debug_execution
) {
1239 r
= armv7m
->arm
.core_cache
->reg_list
+ ARMV7M_PRIMASK
;
1241 /* Disable interrupts */
1242 /* We disable interrupts in the PRIMASK register instead of
1243 * masking with C_MASKINTS. This is probably the same issue
1244 * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
1245 * in parallel with disabled interrupts can cause local faults
1248 * This breaks non-debug (application) execution if not
1249 * called from armv7m_start_algorithm() which saves registers.
1251 buf_set_u32(r
->value
, 0, 1, 1);
1255 /* Make sure we are in Thumb mode, set xPSR.T bit */
1256 /* armv7m_start_algorithm() initializes entire xPSR register.
1257 * This duplicity handles the case when cortex_m_resume()
1258 * is used with the debug_execution flag directly,
1259 * not called through armv7m_start_algorithm().
1261 r
= armv7m
->arm
.cpsr
;
1262 buf_set_u32(r
->value
, 24, 1, 1);
1267 /* current = 1: continue on current pc, otherwise continue at <address> */
1270 buf_set_u32(r
->value
, 0, 32, *address
);
1275 /* if we halted last time due to a bkpt instruction
1276 * then we have to manually step over it, otherwise
1277 * the core will break again */
1279 if (!breakpoint_find(target
, buf_get_u32(r
->value
, 0, 32))
1280 && !debug_execution
)
1281 armv7m_maybe_skip_bkpt_inst(target
, NULL
);
1283 resume_pc
= buf_get_u32(r
->value
, 0, 32);
1285 *address
= resume_pc
;
1287 int retval
= armv7m_restore_context(target
);
1288 if (retval
!= ERROR_OK
)
1291 /* the front-end may request us not to handle breakpoints */
1292 if (handle_breakpoints
) {
1293 /* Single step past breakpoint at current address */
1294 breakpoint
= breakpoint_find(target
, resume_pc
);
1296 LOG_TARGET_DEBUG(target
, "unset breakpoint at " TARGET_ADDR_FMT
" (ID: %" PRIu32
")",
1297 breakpoint
->address
,
1298 breakpoint
->unique_id
);
1299 retval
= cortex_m_unset_breakpoint(target
, breakpoint
);
1300 if (retval
== ERROR_OK
)
1301 retval
= cortex_m_single_step_core(target
);
1302 int ret2
= cortex_m_set_breakpoint(target
, breakpoint
);
1303 if (retval
!= ERROR_OK
)
1305 if (ret2
!= ERROR_OK
)
1313 static int cortex_m_restart_one(struct target
*target
, bool debug_execution
)
1315 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
1318 cortex_m_set_maskints_for_run(target
);
1319 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1321 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1322 /* registers are now invalid */
1323 register_cache_invalidate(armv7m
->arm
.core_cache
);
1325 if (!debug_execution
) {
1326 target
->state
= TARGET_RUNNING
;
1327 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1329 target
->state
= TARGET_DEBUG_RUNNING
;
1330 target_call_event_callbacks(target
, TARGET_EVENT_DEBUG_RESUMED
);
1336 static int cortex_m_restore_smp(struct target
*target
, bool handle_breakpoints
)
1338 struct target_list
*head
;
1339 target_addr_t address
;
1340 foreach_smp_target(head
, target
->smp_targets
) {
1341 struct target
*curr
= head
->target
;
1342 /* skip calling target */
1345 if (!target_was_examined(curr
))
1347 /* skip running targets */
1348 if (curr
->state
== TARGET_RUNNING
)
1351 int retval
= cortex_m_restore_one(curr
, true, &address
,
1352 handle_breakpoints
, false);
1353 if (retval
!= ERROR_OK
)
1356 retval
= cortex_m_restart_one(curr
, false);
1357 if (retval
!= ERROR_OK
)
1360 LOG_TARGET_DEBUG(curr
, "SMP resumed at " TARGET_ADDR_FMT
, address
);
1365 static int cortex_m_resume(struct target
*target
, int current
,
1366 target_addr_t address
, int handle_breakpoints
, int debug_execution
)
1368 int retval
= cortex_m_restore_one(target
, !!current
, &address
, !!handle_breakpoints
, !!debug_execution
);
1369 if (retval
!= ERROR_OK
) {
1370 LOG_TARGET_ERROR(target
, "context restore failed, aborting resume");
1374 if (target
->smp
&& !debug_execution
) {
1375 retval
= cortex_m_restore_smp(target
, !!handle_breakpoints
);
1376 if (retval
!= ERROR_OK
)
1377 LOG_WARNING("resume of a SMP target failed, trying to resume current one");
1380 cortex_m_restart_one(target
, !!debug_execution
);
1381 if (retval
!= ERROR_OK
) {
1382 LOG_TARGET_ERROR(target
, "resume failed");
1386 LOG_TARGET_DEBUG(target
, "%sresumed at " TARGET_ADDR_FMT
,
1387 debug_execution
? "debug " : "", address
);
1392 /* int irqstepcount = 0; */
1393 static int cortex_m_step(struct target
*target
, int current
,
1394 target_addr_t address
, int handle_breakpoints
)
1396 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1397 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1398 struct breakpoint
*breakpoint
= NULL
;
1399 struct reg
*pc
= armv7m
->arm
.pc
;
1400 bool bkpt_inst_found
= false;
1402 bool isr_timed_out
= false;
1404 if (target
->state
!= TARGET_HALTED
) {
1405 LOG_TARGET_ERROR(target
, "not halted");
1406 return ERROR_TARGET_NOT_HALTED
;
1409 /* Just one of SMP cores will step. Set the gdb control
1410 * target to current one or gdb miss gdb-end event */
1411 if (target
->smp
&& target
->gdb_service
)
1412 target
->gdb_service
->target
= target
;
1414 /* current = 1: continue on current pc, otherwise continue at <address> */
1416 buf_set_u32(pc
->value
, 0, 32, address
);
1421 uint32_t pc_value
= buf_get_u32(pc
->value
, 0, 32);
1423 /* the front-end may request us not to handle breakpoints */
1424 if (handle_breakpoints
) {
1425 breakpoint
= breakpoint_find(target
, pc_value
);
1427 cortex_m_unset_breakpoint(target
, breakpoint
);
1430 armv7m_maybe_skip_bkpt_inst(target
, &bkpt_inst_found
);
1432 target
->debug_reason
= DBG_REASON_SINGLESTEP
;
1434 armv7m_restore_context(target
);
1436 target_call_event_callbacks(target
, TARGET_EVENT_RESUMED
);
1438 /* if no bkpt instruction is found at pc then we can perform
1439 * a normal step, otherwise we have to manually step over the bkpt
1440 * instruction - as such simulate a step */
1441 if (bkpt_inst_found
== false) {
1442 if (cortex_m
->isrmasking_mode
!= CORTEX_M_ISRMASK_AUTO
) {
1443 /* Automatic ISR masking mode off: Just step over the next
1444 * instruction, with interrupts on or off as appropriate. */
1445 cortex_m_set_maskints_for_step(target
);
1446 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1448 /* Process interrupts during stepping in a way they don't interfere
1453 * Set a temporary break point at the current pc and let the core run
1454 * with interrupts enabled. Pending interrupts get served and we run
1455 * into the breakpoint again afterwards. Then we step over the next
1456 * instruction with interrupts disabled.
1458 * If the pending interrupts don't complete within time, we leave the
1459 * core running. This may happen if the interrupts trigger faster
1460 * than the core can process them or the handler doesn't return.
1462 * If no more breakpoints are available we simply do a step with
1463 * interrupts enabled.
1469 * If a break point is already set on the lower half word then a break point on
1470 * the upper half word will not break again when the core is restarted. So we
1471 * just step over the instruction with interrupts disabled.
1473 * The documentation has no information about this, it was found by observation
1474 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
1475 * suffer from this problem.
1477 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
1478 * address has it always cleared. The former is done to indicate thumb mode
1482 if ((pc_value
& 0x02) && breakpoint_find(target
, pc_value
& ~0x03)) {
1483 LOG_TARGET_DEBUG(target
, "Stepping over next instruction with interrupts disabled");
1484 cortex_m_write_debug_halt_mask(target
, C_HALT
| C_MASKINTS
, 0);
1485 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1486 /* Re-enable interrupts if appropriate */
1487 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1488 cortex_m_set_maskints_for_halt(target
);
1491 /* Set a temporary break point */
1493 retval
= cortex_m_set_breakpoint(target
, breakpoint
);
1495 enum breakpoint_type type
= BKPT_HARD
;
1496 if (cortex_m
->fp_rev
== 0 && pc_value
> 0x1FFFFFFF) {
1497 /* FPB rev.1 cannot handle such addr, try BKPT instr */
1500 retval
= breakpoint_add(target
, pc_value
, 2, type
);
1503 bool tmp_bp_set
= (retval
== ERROR_OK
);
1505 /* No more breakpoints left, just do a step */
1507 cortex_m_set_maskints_for_step(target
);
1508 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1509 /* Re-enable interrupts if appropriate */
1510 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1511 cortex_m_set_maskints_for_halt(target
);
1513 /* Start the core */
1514 LOG_TARGET_DEBUG(target
, "Starting core to serve pending interrupts");
1515 int64_t t_start
= timeval_ms();
1516 cortex_m_set_maskints_for_run(target
);
1517 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
);
1519 /* Wait for pending handlers to complete or timeout */
1521 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
1522 if (retval
!= ERROR_OK
) {
1523 target
->state
= TARGET_UNKNOWN
;
1526 isr_timed_out
= ((timeval_ms() - t_start
) > 500);
1527 } while (!((cortex_m
->dcb_dhcsr
& S_HALT
) || isr_timed_out
));
1529 /* only remove breakpoint if we created it */
1531 cortex_m_unset_breakpoint(target
, breakpoint
);
1533 /* Remove the temporary breakpoint */
1534 breakpoint_remove(target
, pc_value
);
1537 if (isr_timed_out
) {
1538 LOG_TARGET_DEBUG(target
, "Interrupt handlers didn't complete within time, "
1539 "leaving target running");
1541 /* Step over next instruction with interrupts disabled */
1542 cortex_m_set_maskints_for_step(target
);
1543 cortex_m_write_debug_halt_mask(target
,
1544 C_HALT
| C_MASKINTS
,
1546 cortex_m_write_debug_halt_mask(target
, C_STEP
, C_HALT
);
1547 /* Re-enable interrupts if appropriate */
1548 cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1549 cortex_m_set_maskints_for_halt(target
);
1556 retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
1557 if (retval
!= ERROR_OK
)
1560 /* registers are now invalid */
1561 register_cache_invalidate(armv7m
->arm
.core_cache
);
1564 cortex_m_set_breakpoint(target
, breakpoint
);
1566 if (isr_timed_out
) {
1567 /* Leave the core running. The user has to stop execution manually. */
1568 target
->debug_reason
= DBG_REASON_NOTHALTED
;
1569 target
->state
= TARGET_RUNNING
;
1573 LOG_TARGET_DEBUG(target
, "target stepped dcb_dhcsr = 0x%" PRIx32
1574 " nvic_icsr = 0x%" PRIx32
,
1575 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1577 retval
= cortex_m_debug_entry(target
);
1578 if (retval
!= ERROR_OK
)
1580 target_call_event_callbacks(target
, TARGET_EVENT_HALTED
);
1582 LOG_TARGET_DEBUG(target
, "target stepped dcb_dhcsr = 0x%" PRIx32
1583 " nvic_icsr = 0x%" PRIx32
,
1584 cortex_m
->dcb_dhcsr
, cortex_m
->nvic_icsr
);
1589 static int cortex_m_assert_reset(struct target
*target
)
1591 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1592 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
1593 enum cortex_m_soft_reset_config reset_config
= cortex_m
->soft_reset_config
;
1595 LOG_TARGET_DEBUG(target
, "target->state: %s,%s examined",
1596 target_state_name(target
),
1597 target_was_examined(target
) ? "" : " not");
1599 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1601 if (target_has_event_action(target
, TARGET_EVENT_RESET_ASSERT
)) {
1602 /* allow scripts to override the reset event */
1604 target_handle_event(target
, TARGET_EVENT_RESET_ASSERT
);
1605 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1606 target
->state
= TARGET_RESET
;
1611 /* some cores support connecting while srst is asserted
1612 * use that mode is it has been configured */
1614 bool srst_asserted
= false;
1616 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1617 ((jtag_reset_config
& RESET_SRST_NO_GATING
) || !armv7m
->debug_ap
)) {
1618 /* If we have no debug_ap, asserting SRST is the only thing
1620 adapter_assert_reset();
1621 srst_asserted
= true;
1624 /* TODO: replace the hack calling target_examine_one()
1625 * as soon as a better reset framework is available */
1626 if (!target_was_examined(target
) && !target
->defer_examine
1627 && srst_asserted
&& (jtag_reset_config
& RESET_SRST_NO_GATING
)) {
1628 LOG_TARGET_DEBUG(target
, "Trying to re-examine under reset");
1629 target_examine_one(target
);
1632 /* We need at least debug_ap to go further.
1633 * Inform user and bail out if we don't have one. */
1634 if (!armv7m
->debug_ap
) {
1635 if (srst_asserted
) {
1636 if (target
->reset_halt
)
1637 LOG_TARGET_ERROR(target
, "Debug AP not available, will not halt after reset!");
1639 /* Do not propagate error: reset was asserted, proceed to deassert! */
1640 target
->state
= TARGET_RESET
;
1641 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1645 LOG_TARGET_ERROR(target
, "Debug AP not available, reset NOT asserted!");
1650 /* Enable debug requests */
1651 int retval
= cortex_m_read_dhcsr_atomic_sticky(target
);
1653 /* Store important errors instead of failing and proceed to reset assert */
1655 if (retval
!= ERROR_OK
|| !(cortex_m
->dcb_dhcsr
& C_DEBUGEN
))
1656 retval
= cortex_m_write_debug_halt_mask(target
, 0, C_HALT
| C_STEP
| C_MASKINTS
);
1658 /* If the processor is sleeping in a WFI or WFE instruction, the
1659 * C_HALT bit must be asserted to regain control */
1660 if (retval
== ERROR_OK
&& (cortex_m
->dcb_dhcsr
& S_SLEEP
))
1661 retval
= cortex_m_write_debug_halt_mask(target
, C_HALT
, 0);
1663 mem_ap_write_u32(armv7m
->debug_ap
, DCB_DCRDR
, 0);
1664 /* Ignore less important errors */
1666 if (!target
->reset_halt
) {
1667 /* Set/Clear C_MASKINTS in a separate operation */
1668 cortex_m_set_maskints_for_run(target
);
1670 /* clear any debug flags before resuming */
1671 cortex_m_clear_halt(target
);
1673 /* clear C_HALT in dhcsr reg */
1674 cortex_m_write_debug_halt_mask(target
, 0, C_HALT
);
1676 /* Halt in debug on reset; endreset_event() restores DEMCR.
1678 * REVISIT catching BUSERR presumably helps to defend against
1679 * bad vector table entries. Should this include MMERR or
1683 retval2
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
,
1684 TRCENA
| VC_HARDERR
| VC_BUSERR
| VC_CORERESET
);
1685 if (retval
!= ERROR_OK
|| retval2
!= ERROR_OK
)
1686 LOG_TARGET_INFO(target
, "AP write error, reset will not halt");
1689 if (jtag_reset_config
& RESET_HAS_SRST
) {
1690 /* default to asserting srst */
1692 adapter_assert_reset();
1694 /* srst is asserted, ignore AP access errors */
1697 /* Use a standard Cortex-M3 software reset mechanism.
1698 * We default to using VECTRESET as it is supported on all current cores
1699 * (except Cortex-M0, M0+ and M1 which support SYSRESETREQ only!)
1700 * This has the disadvantage of not resetting the peripherals, so a
1701 * reset-init event handler is needed to perform any peripheral resets.
1703 if (!cortex_m
->vectreset_supported
1704 && reset_config
== CORTEX_M_RESET_VECTRESET
) {
1705 reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
1706 LOG_TARGET_WARNING(target
, "VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
1707 LOG_TARGET_WARNING(target
, "Set 'cortex_m reset_config sysresetreq'.");
1710 LOG_TARGET_DEBUG(target
, "Using Cortex-M %s", (reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1711 ? "SYSRESETREQ" : "VECTRESET");
1713 if (reset_config
== CORTEX_M_RESET_VECTRESET
) {
1714 LOG_TARGET_WARNING(target
, "Only resetting the Cortex-M core, use a reset-init event "
1715 "handler to reset any peripherals or configure hardware srst support.");
1719 retval3
= mem_ap_write_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
,
1720 AIRCR_VECTKEY
| ((reset_config
== CORTEX_M_RESET_SYSRESETREQ
)
1721 ? AIRCR_SYSRESETREQ
: AIRCR_VECTRESET
));
1722 if (retval3
!= ERROR_OK
)
1723 LOG_TARGET_DEBUG(target
, "Ignoring AP write error right after reset");
1725 retval3
= dap_dp_init_or_reconnect(armv7m
->debug_ap
->dap
);
1726 if (retval3
!= ERROR_OK
) {
1727 LOG_TARGET_ERROR(target
, "DP initialisation failed");
1728 /* The error return value must not be propagated in this case.
1729 * SYSRESETREQ or VECTRESET have been possibly triggered
1730 * so reset processing should continue */
1732 /* I do not know why this is necessary, but it
1733 * fixes strange effects (step/resume cause NMI
1734 * after reset) on LM3S6918 -- Michael Schwingen
1737 mem_ap_read_atomic_u32(armv7m
->debug_ap
, NVIC_AIRCR
, &tmp
);
1741 target
->state
= TARGET_RESET
;
1744 register_cache_invalidate(cortex_m
->armv7m
.arm
.core_cache
);
1746 /* now return stored error code if any */
1747 if (retval
!= ERROR_OK
)
1750 if (target
->reset_halt
&& target_was_examined(target
)) {
1751 retval
= target_halt(target
);
1752 if (retval
!= ERROR_OK
)
1759 static int cortex_m_deassert_reset(struct target
*target
)
1761 struct armv7m_common
*armv7m
= &target_to_cm(target
)->armv7m
;
1763 LOG_TARGET_DEBUG(target
, "target->state: %s,%s examined",
1764 target_state_name(target
),
1765 target_was_examined(target
) ? "" : " not");
1767 /* deassert reset lines */
1768 adapter_deassert_reset();
1770 enum reset_types jtag_reset_config
= jtag_get_reset_config();
1772 if ((jtag_reset_config
& RESET_HAS_SRST
) &&
1773 !(jtag_reset_config
& RESET_SRST_NO_GATING
) &&
1776 int retval
= dap_dp_init_or_reconnect(armv7m
->debug_ap
->dap
);
1777 if (retval
!= ERROR_OK
) {
1778 LOG_TARGET_ERROR(target
, "DP initialisation failed");
1786 int cortex_m_set_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1789 unsigned int fp_num
= 0;
1790 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1791 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1793 if (breakpoint
->is_set
) {
1794 LOG_TARGET_WARNING(target
, "breakpoint (BPID: %" PRIu32
") already set", breakpoint
->unique_id
);
1798 if (breakpoint
->type
== BKPT_HARD
) {
1799 uint32_t fpcr_value
;
1800 while (comparator_list
[fp_num
].used
&& (fp_num
< cortex_m
->fp_num_code
))
1802 if (fp_num
>= cortex_m
->fp_num_code
) {
1803 LOG_TARGET_ERROR(target
, "Can not find free FPB Comparator!");
1804 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1806 breakpoint_hw_set(breakpoint
, fp_num
);
1807 fpcr_value
= breakpoint
->address
| 1;
1808 if (cortex_m
->fp_rev
== 0) {
1809 if (breakpoint
->address
> 0x1FFFFFFF) {
1810 LOG_TARGET_ERROR(target
, "Cortex-M Flash Patch Breakpoint rev.1 "
1811 "cannot handle HW breakpoint above address 0x1FFFFFFE");
1815 hilo
= (breakpoint
->address
& 0x2) ? FPCR_REPLACE_BKPT_HIGH
: FPCR_REPLACE_BKPT_LOW
;
1816 fpcr_value
= (fpcr_value
& 0x1FFFFFFC) | hilo
| 1;
1817 } else if (cortex_m
->fp_rev
> 1) {
1818 LOG_TARGET_ERROR(target
, "Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
1821 comparator_list
[fp_num
].used
= true;
1822 comparator_list
[fp_num
].fpcr_value
= fpcr_value
;
1823 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1824 comparator_list
[fp_num
].fpcr_value
);
1825 LOG_TARGET_DEBUG(target
, "fpc_num %i fpcr_value 0x%" PRIx32
"",
1827 comparator_list
[fp_num
].fpcr_value
);
1828 if (!cortex_m
->fpb_enabled
) {
1829 LOG_TARGET_DEBUG(target
, "FPB wasn't enabled, do it now");
1830 retval
= cortex_m_enable_fpb(target
);
1831 if (retval
!= ERROR_OK
) {
1832 LOG_TARGET_ERROR(target
, "Failed to enable the FPB");
1836 cortex_m
->fpb_enabled
= true;
1838 } else if (breakpoint
->type
== BKPT_SOFT
) {
1841 /* NOTE: on ARMv6-M and ARMv7-M, BKPT(0xab) is used for
1842 * semihosting; don't use that. Otherwise the BKPT
1843 * parameter is arbitrary.
1845 buf_set_u32(code
, 0, 32, ARMV5_T_BKPT(0x11));
1846 retval
= target_read_memory(target
,
1847 breakpoint
->address
& 0xFFFFFFFE,
1848 breakpoint
->length
, 1,
1849 breakpoint
->orig_instr
);
1850 if (retval
!= ERROR_OK
)
1852 retval
= target_write_memory(target
,
1853 breakpoint
->address
& 0xFFFFFFFE,
1854 breakpoint
->length
, 1,
1856 if (retval
!= ERROR_OK
)
1858 breakpoint
->is_set
= true;
1861 LOG_TARGET_DEBUG(target
, "BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (n=%u)",
1862 breakpoint
->unique_id
,
1863 (int)(breakpoint
->type
),
1864 breakpoint
->address
,
1866 (breakpoint
->type
== BKPT_SOFT
) ? 0 : breakpoint
->number
);
1871 int cortex_m_unset_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1874 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1875 struct cortex_m_fp_comparator
*comparator_list
= cortex_m
->fp_comparator_list
;
1877 if (!breakpoint
->is_set
) {
1878 LOG_TARGET_WARNING(target
, "breakpoint not set");
1882 LOG_TARGET_DEBUG(target
, "BPID: %" PRIu32
", Type: %d, Address: " TARGET_ADDR_FMT
" Length: %d (n=%u)",
1883 breakpoint
->unique_id
,
1884 (int)(breakpoint
->type
),
1885 breakpoint
->address
,
1887 (breakpoint
->type
== BKPT_SOFT
) ? 0 : breakpoint
->number
);
1889 if (breakpoint
->type
== BKPT_HARD
) {
1890 unsigned int fp_num
= breakpoint
->number
;
1891 if (fp_num
>= cortex_m
->fp_num_code
) {
1892 LOG_TARGET_DEBUG(target
, "Invalid FP Comparator number in breakpoint");
1895 comparator_list
[fp_num
].used
= false;
1896 comparator_list
[fp_num
].fpcr_value
= 0;
1897 target_write_u32(target
, comparator_list
[fp_num
].fpcr_address
,
1898 comparator_list
[fp_num
].fpcr_value
);
1900 /* restore original instruction (kept in target endianness) */
1901 retval
= target_write_memory(target
, breakpoint
->address
& 0xFFFFFFFE,
1902 breakpoint
->length
, 1,
1903 breakpoint
->orig_instr
);
1904 if (retval
!= ERROR_OK
)
1907 breakpoint
->is_set
= false;
1912 int cortex_m_add_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1914 if (breakpoint
->length
== 3) {
1915 LOG_TARGET_DEBUG(target
, "Using a two byte breakpoint for 32bit Thumb-2 request");
1916 breakpoint
->length
= 2;
1919 if ((breakpoint
->length
!= 2)) {
1920 LOG_TARGET_INFO(target
, "only breakpoints of two bytes length supported");
1921 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
1924 return cortex_m_set_breakpoint(target
, breakpoint
);
1927 int cortex_m_remove_breakpoint(struct target
*target
, struct breakpoint
*breakpoint
)
1929 if (!breakpoint
->is_set
)
1932 return cortex_m_unset_breakpoint(target
, breakpoint
);
1935 static int cortex_m_set_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
1937 unsigned int dwt_num
= 0;
1938 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
1940 /* REVISIT Don't fully trust these "not used" records ... users
1941 * may set up breakpoints by hand, e.g. dual-address data value
1942 * watchpoint using comparator #1; comparator #0 matching cycle
1943 * count; send data trace info through ITM and TPIU; etc
1945 struct cortex_m_dwt_comparator
*comparator
;
1947 for (comparator
= cortex_m
->dwt_comparator_list
;
1948 comparator
->used
&& dwt_num
< cortex_m
->dwt_num_comp
;
1949 comparator
++, dwt_num
++)
1951 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
1952 LOG_TARGET_ERROR(target
, "Can not find free DWT Comparator");
1955 comparator
->used
= true;
1956 watchpoint_set(watchpoint
, dwt_num
);
1958 comparator
->comp
= watchpoint
->address
;
1959 target_write_u32(target
, comparator
->dwt_comparator_address
+ 0,
1962 if ((cortex_m
->dwt_devarch
& 0x1FFFFF) != DWT_DEVARCH_ARMV8M_V2_0
1963 && (cortex_m
->dwt_devarch
& 0x1FFFFF) != DWT_DEVARCH_ARMV8M_V2_1
) {
1964 uint32_t mask
= 0, temp
;
1966 /* watchpoint params were validated earlier */
1967 temp
= watchpoint
->length
;
1974 comparator
->mask
= mask
;
1975 target_write_u32(target
, comparator
->dwt_comparator_address
+ 4,
1978 switch (watchpoint
->rw
) {
1980 comparator
->function
= 5;
1983 comparator
->function
= 6;
1986 comparator
->function
= 7;
1990 uint32_t data_size
= watchpoint
->length
>> 1;
1991 comparator
->mask
= (watchpoint
->length
>> 1) | 1;
1993 switch (watchpoint
->rw
) {
1995 comparator
->function
= 4;
1998 comparator
->function
= 5;
2001 comparator
->function
= 6;
2004 comparator
->function
= comparator
->function
| (1 << 4) |
2008 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
2009 comparator
->function
);
2011 LOG_TARGET_DEBUG(target
, "Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
2012 watchpoint
->unique_id
, dwt_num
,
2013 (unsigned) comparator
->comp
,
2014 (unsigned) comparator
->mask
,
2015 (unsigned) comparator
->function
);
2019 static int cortex_m_unset_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
2021 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2022 struct cortex_m_dwt_comparator
*comparator
;
2024 if (!watchpoint
->is_set
) {
2025 LOG_TARGET_WARNING(target
, "watchpoint (wpid: %d) not set",
2026 watchpoint
->unique_id
);
2030 unsigned int dwt_num
= watchpoint
->number
;
2032 LOG_TARGET_DEBUG(target
, "Watchpoint (ID %d) DWT%u address: 0x%08x clear",
2033 watchpoint
->unique_id
, dwt_num
,
2034 (unsigned) watchpoint
->address
);
2036 if (dwt_num
>= cortex_m
->dwt_num_comp
) {
2037 LOG_TARGET_DEBUG(target
, "Invalid DWT Comparator number in watchpoint");
2041 comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
2042 comparator
->used
= false;
2043 comparator
->function
= 0;
2044 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8,
2045 comparator
->function
);
2047 watchpoint
->is_set
= false;
2052 int cortex_m_add_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
2054 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2056 if (cortex_m
->dwt_comp_available
< 1) {
2057 LOG_TARGET_DEBUG(target
, "no comparators?");
2058 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2061 /* REVISIT This DWT may well be able to watch for specific data
2062 * values. Requires comparator #1 to set DATAVMATCH and match
2063 * the data, and another comparator (DATAVADDR0) matching addr.
2065 * NOTE: hardware doesn't support data value masking, so we'll need
2066 * to check that mask is zero
2068 if (watchpoint
->mask
!= WATCHPOINT_IGNORE_DATA_VALUE_MASK
) {
2069 LOG_TARGET_DEBUG(target
, "watchpoint value masks not supported");
2070 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2073 /* hardware allows address masks of up to 32K */
2076 for (mask
= 0; mask
< 16; mask
++) {
2077 if ((1u << mask
) == watchpoint
->length
)
2081 LOG_TARGET_DEBUG(target
, "unsupported watchpoint length");
2082 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2084 if (watchpoint
->address
& ((1 << mask
) - 1)) {
2085 LOG_TARGET_DEBUG(target
, "watchpoint address is unaligned");
2086 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
2089 cortex_m
->dwt_comp_available
--;
2090 LOG_TARGET_DEBUG(target
, "dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
2095 int cortex_m_remove_watchpoint(struct target
*target
, struct watchpoint
*watchpoint
)
2097 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2099 /* REVISIT why check? DWT can be updated with core running ... */
2100 if (target
->state
!= TARGET_HALTED
) {
2101 LOG_TARGET_ERROR(target
, "not halted");
2102 return ERROR_TARGET_NOT_HALTED
;
2105 if (watchpoint
->is_set
)
2106 cortex_m_unset_watchpoint(target
, watchpoint
);
2108 cortex_m
->dwt_comp_available
++;
2109 LOG_TARGET_DEBUG(target
, "dwt_comp_available: %d", cortex_m
->dwt_comp_available
);
2114 static int cortex_m_hit_watchpoint(struct target
*target
, struct watchpoint
**hit_watchpoint
)
2116 if (target
->debug_reason
!= DBG_REASON_WATCHPOINT
)
2119 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2121 for (struct watchpoint
*wp
= target
->watchpoints
; wp
; wp
= wp
->next
) {
2125 unsigned int dwt_num
= wp
->number
;
2126 struct cortex_m_dwt_comparator
*comparator
= cortex_m
->dwt_comparator_list
+ dwt_num
;
2128 uint32_t dwt_function
;
2129 int retval
= target_read_u32(target
, comparator
->dwt_comparator_address
+ 8, &dwt_function
);
2130 if (retval
!= ERROR_OK
)
2133 /* check the MATCHED bit */
2134 if (dwt_function
& BIT(24)) {
2135 *hit_watchpoint
= wp
;
2143 void cortex_m_enable_watchpoints(struct target
*target
)
2145 struct watchpoint
*watchpoint
= target
->watchpoints
;
2147 /* set any pending watchpoints */
2148 while (watchpoint
) {
2149 if (!watchpoint
->is_set
)
2150 cortex_m_set_watchpoint(target
, watchpoint
);
2151 watchpoint
= watchpoint
->next
;
2155 static int cortex_m_read_memory(struct target
*target
, target_addr_t address
,
2156 uint32_t size
, uint32_t count
, uint8_t *buffer
)
2158 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2160 if (armv7m
->arm
.arch
== ARM_ARCH_V6M
) {
2161 /* armv6m does not handle unaligned memory access */
2162 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2163 return ERROR_TARGET_UNALIGNED_ACCESS
;
2166 return mem_ap_read_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
2169 static int cortex_m_write_memory(struct target
*target
, target_addr_t address
,
2170 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
2172 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2174 if (armv7m
->arm
.arch
== ARM_ARCH_V6M
) {
2175 /* armv6m does not handle unaligned memory access */
2176 if (((size
== 4) && (address
& 0x3u
)) || ((size
== 2) && (address
& 0x1u
)))
2177 return ERROR_TARGET_UNALIGNED_ACCESS
;
2180 return mem_ap_write_buf(armv7m
->debug_ap
, buffer
, size
, count
, address
);
2183 static int cortex_m_init_target(struct command_context
*cmd_ctx
,
2184 struct target
*target
)
2186 armv7m_build_reg_cache(target
);
2187 arm_semihosting_init(target
);
2191 void cortex_m_deinit_target(struct target
*target
)
2193 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2194 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2196 if (!armv7m
->is_hla_target
&& armv7m
->debug_ap
)
2197 dap_put_ap(armv7m
->debug_ap
);
2199 free(cortex_m
->fp_comparator_list
);
2201 cortex_m_dwt_free(target
);
2202 armv7m_free_reg_cache(target
);
2204 free(target
->private_config
);
2208 int cortex_m_profiling(struct target
*target
, uint32_t *samples
,
2209 uint32_t max_num_samples
, uint32_t *num_samples
, uint32_t seconds
)
2211 struct timeval timeout
, now
;
2212 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2216 retval
= target_read_u32(target
, DWT_PCSR
, ®_value
);
2217 if (retval
!= ERROR_OK
) {
2218 LOG_TARGET_ERROR(target
, "Error while reading PCSR");
2221 if (reg_value
== 0) {
2222 LOG_TARGET_INFO(target
, "PCSR sampling not supported on this processor.");
2223 return target_profiling_default(target
, samples
, max_num_samples
, num_samples
, seconds
);
2226 gettimeofday(&timeout
, NULL
);
2227 timeval_add_time(&timeout
, seconds
, 0);
2229 LOG_TARGET_INFO(target
, "Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
2231 /* Make sure the target is running */
2232 target_poll(target
);
2233 if (target
->state
== TARGET_HALTED
)
2234 retval
= target_resume(target
, 1, 0, 0, 0);
2236 if (retval
!= ERROR_OK
) {
2237 LOG_TARGET_ERROR(target
, "Error while resuming target");
2241 uint32_t sample_count
= 0;
2244 if (armv7m
&& armv7m
->debug_ap
) {
2245 uint32_t read_count
= max_num_samples
- sample_count
;
2246 if (read_count
> 1024)
2249 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
,
2250 (void *)&samples
[sample_count
],
2251 4, read_count
, DWT_PCSR
);
2252 sample_count
+= read_count
;
2254 target_read_u32(target
, DWT_PCSR
, &samples
[sample_count
++]);
2257 if (retval
!= ERROR_OK
) {
2258 LOG_TARGET_ERROR(target
, "Error while reading PCSR");
2263 gettimeofday(&now
, NULL
);
2264 if (sample_count
>= max_num_samples
|| timeval_compare(&now
, &timeout
) > 0) {
2265 LOG_TARGET_INFO(target
, "Profiling completed. %" PRIu32
" samples.", sample_count
);
2270 *num_samples
= sample_count
;
2275 /* REVISIT cache valid/dirty bits are unmaintained. We could set "valid"
2276 * on r/w if the core is not running, and clear on resume or reset ... or
2277 * at least, in a post_restore_context() method.
2280 struct dwt_reg_state
{
2281 struct target
*target
;
2283 uint8_t value
[4]; /* scratch/cache */
2286 static int cortex_m_dwt_get_reg(struct reg
*reg
)
2288 struct dwt_reg_state
*state
= reg
->arch_info
;
2291 int retval
= target_read_u32(state
->target
, state
->addr
, &tmp
);
2292 if (retval
!= ERROR_OK
)
2295 buf_set_u32(state
->value
, 0, 32, tmp
);
2299 static int cortex_m_dwt_set_reg(struct reg
*reg
, uint8_t *buf
)
2301 struct dwt_reg_state
*state
= reg
->arch_info
;
2303 return target_write_u32(state
->target
, state
->addr
,
2304 buf_get_u32(buf
, 0, reg
->size
));
2313 static const struct dwt_reg dwt_base_regs
[] = {
2314 { DWT_CTRL
, "dwt_ctrl", 32, },
2315 /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
2316 * increments while the core is asleep.
2318 { DWT_CYCCNT
, "dwt_cyccnt", 32, },
2319 /* plus some 8 bit counters, useful for profiling with TPIU */
2322 static const struct dwt_reg dwt_comp
[] = {
2323 #define DWT_COMPARATOR(i) \
2324 { DWT_COMP0 + 0x10 * (i), "dwt_" #i "_comp", 32, }, \
2325 { DWT_MASK0 + 0x10 * (i), "dwt_" #i "_mask", 4, }, \
2326 { DWT_FUNCTION0 + 0x10 * (i), "dwt_" #i "_function", 32, }
2343 #undef DWT_COMPARATOR
2346 static const struct reg_arch_type dwt_reg_type
= {
2347 .get
= cortex_m_dwt_get_reg
,
2348 .set
= cortex_m_dwt_set_reg
,
2351 static void cortex_m_dwt_addreg(struct target
*t
, struct reg
*r
, const struct dwt_reg
*d
)
2353 struct dwt_reg_state
*state
;
2355 state
= calloc(1, sizeof(*state
));
2358 state
->addr
= d
->addr
;
2363 r
->value
= state
->value
;
2364 r
->arch_info
= state
;
2365 r
->type
= &dwt_reg_type
;
2368 static void cortex_m_dwt_setup(struct cortex_m_common
*cm
, struct target
*target
)
2371 struct reg_cache
*cache
;
2372 struct cortex_m_dwt_comparator
*comparator
;
2375 target_read_u32(target
, DWT_CTRL
, &dwtcr
);
2376 LOG_TARGET_DEBUG(target
, "DWT_CTRL: 0x%" PRIx32
, dwtcr
);
2378 LOG_TARGET_DEBUG(target
, "no DWT");
2382 target_read_u32(target
, DWT_DEVARCH
, &cm
->dwt_devarch
);
2383 LOG_TARGET_DEBUG(target
, "DWT_DEVARCH: 0x%" PRIx32
, cm
->dwt_devarch
);
2385 cm
->dwt_num_comp
= (dwtcr
>> 28) & 0xF;
2386 cm
->dwt_comp_available
= cm
->dwt_num_comp
;
2387 cm
->dwt_comparator_list
= calloc(cm
->dwt_num_comp
,
2388 sizeof(struct cortex_m_dwt_comparator
));
2389 if (!cm
->dwt_comparator_list
) {
2391 cm
->dwt_num_comp
= 0;
2392 LOG_TARGET_ERROR(target
, "out of mem");
2396 cache
= calloc(1, sizeof(*cache
));
2399 free(cm
->dwt_comparator_list
);
2402 cache
->name
= "Cortex-M DWT registers";
2403 cache
->num_regs
= 2 + cm
->dwt_num_comp
* 3;
2404 cache
->reg_list
= calloc(cache
->num_regs
, sizeof(*cache
->reg_list
));
2405 if (!cache
->reg_list
) {
2410 for (reg
= 0; reg
< 2; reg
++)
2411 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2412 dwt_base_regs
+ reg
);
2414 comparator
= cm
->dwt_comparator_list
;
2415 for (unsigned int i
= 0; i
< cm
->dwt_num_comp
; i
++, comparator
++) {
2418 comparator
->dwt_comparator_address
= DWT_COMP0
+ 0x10 * i
;
2419 for (j
= 0; j
< 3; j
++, reg
++)
2420 cortex_m_dwt_addreg(target
, cache
->reg_list
+ reg
,
2421 dwt_comp
+ 3 * i
+ j
);
2423 /* make sure we clear any watchpoints enabled on the target */
2424 target_write_u32(target
, comparator
->dwt_comparator_address
+ 8, 0);
2427 *register_get_last_cache_p(&target
->reg_cache
) = cache
;
2428 cm
->dwt_cache
= cache
;
2430 LOG_TARGET_DEBUG(target
, "DWT dwtcr 0x%" PRIx32
", comp %d, watch%s",
2431 dwtcr
, cm
->dwt_num_comp
,
2432 (dwtcr
& (0xf << 24)) ? " only" : "/trigger");
2434 /* REVISIT: if num_comp > 1, check whether comparator #1 can
2435 * implement single-address data value watchpoints ... so we
2436 * won't need to check it later, when asked to set one up.
2440 static void cortex_m_dwt_free(struct target
*target
)
2442 struct cortex_m_common
*cm
= target_to_cm(target
);
2443 struct reg_cache
*cache
= cm
->dwt_cache
;
2445 free(cm
->dwt_comparator_list
);
2446 cm
->dwt_comparator_list
= NULL
;
2447 cm
->dwt_num_comp
= 0;
2450 register_unlink_cache(&target
->reg_cache
, cache
);
2452 if (cache
->reg_list
) {
2453 for (size_t i
= 0; i
< cache
->num_regs
; i
++)
2454 free(cache
->reg_list
[i
].arch_info
);
2455 free(cache
->reg_list
);
2459 cm
->dwt_cache
= NULL
;
2462 static bool cortex_m_has_tz(struct target
*target
)
2464 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2465 uint32_t dauthstatus
;
2467 if (armv7m
->arm
.arch
!= ARM_ARCH_V8M
)
2470 int retval
= target_read_u32(target
, DAUTHSTATUS
, &dauthstatus
);
2471 if (retval
!= ERROR_OK
) {
2472 LOG_WARNING("Error reading DAUTHSTATUS register");
2475 return (dauthstatus
& DAUTHSTATUS_SID_MASK
) != 0;
2478 #define MVFR0 0xe000ef40
2479 #define MVFR1 0xe000ef44
2481 #define MVFR0_DEFAULT_M4 0x10110021
2482 #define MVFR1_DEFAULT_M4 0x11000011
2484 #define MVFR0_DEFAULT_M7_SP 0x10110021
2485 #define MVFR0_DEFAULT_M7_DP 0x10110221
2486 #define MVFR1_DEFAULT_M7_SP 0x11000011
2487 #define MVFR1_DEFAULT_M7_DP 0x12000011
2489 static int cortex_m_find_mem_ap(struct adiv5_dap
*swjdp
,
2490 struct adiv5_ap
**debug_ap
)
2492 if (dap_find_get_ap(swjdp
, AP_TYPE_AHB3_AP
, debug_ap
) == ERROR_OK
)
2495 return dap_find_get_ap(swjdp
, AP_TYPE_AHB5_AP
, debug_ap
);
2498 int cortex_m_examine(struct target
*target
)
2501 uint32_t cpuid
, fpcr
, mvfr0
, mvfr1
;
2502 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2503 struct adiv5_dap
*swjdp
= cortex_m
->armv7m
.arm
.dap
;
2504 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2506 /* hla_target shares the examine handler but does not support
2508 if (!armv7m
->is_hla_target
) {
2509 if (!armv7m
->debug_ap
) {
2510 if (cortex_m
->apsel
== DP_APSEL_INVALID
) {
2511 /* Search for the MEM-AP */
2512 retval
= cortex_m_find_mem_ap(swjdp
, &armv7m
->debug_ap
);
2513 if (retval
!= ERROR_OK
) {
2514 LOG_TARGET_ERROR(target
, "Could not find MEM-AP to control the core");
2518 armv7m
->debug_ap
= dap_get_ap(swjdp
, cortex_m
->apsel
);
2519 if (!armv7m
->debug_ap
) {
2520 LOG_ERROR("Cannot get AP");
2526 armv7m
->debug_ap
->memaccess_tck
= 8;
2528 retval
= mem_ap_init(armv7m
->debug_ap
);
2529 if (retval
!= ERROR_OK
)
2533 if (!target_was_examined(target
)) {
2534 target_set_examined(target
);
2536 /* Read from Device Identification Registers */
2537 retval
= target_read_u32(target
, CPUID
, &cpuid
);
2538 if (retval
!= ERROR_OK
)
2541 /* Inspect implementor/part to look for recognized cores */
2542 unsigned int impl_part
= cpuid
& (ARM_CPUID_IMPLEMENTOR_MASK
| ARM_CPUID_PARTNO_MASK
);
2544 for (unsigned int n
= 0; n
< ARRAY_SIZE(cortex_m_parts
); n
++) {
2545 if (impl_part
== cortex_m_parts
[n
].impl_part
) {
2546 cortex_m
->core_info
= &cortex_m_parts
[n
];
2551 if (!cortex_m
->core_info
) {
2552 LOG_TARGET_ERROR(target
, "Cortex-M CPUID: 0x%x is unrecognized", cpuid
);
2556 armv7m
->arm
.arch
= cortex_m
->core_info
->arch
;
2558 LOG_TARGET_INFO(target
, "%s r%" PRId8
"p%" PRId8
" processor detected",
2559 cortex_m
->core_info
->name
,
2560 (uint8_t)((cpuid
>> 20) & 0xf),
2561 (uint8_t)((cpuid
>> 0) & 0xf));
2563 cortex_m
->maskints_erratum
= false;
2564 if (impl_part
== CORTEX_M7_PARTNO
) {
2566 rev
= (cpuid
>> 20) & 0xf;
2567 patch
= (cpuid
>> 0) & 0xf;
2568 if ((rev
== 0) && (patch
< 2)) {
2569 LOG_TARGET_WARNING(target
, "Silicon bug: single stepping may enter pending exception handler!");
2570 cortex_m
->maskints_erratum
= true;
2573 LOG_TARGET_DEBUG(target
, "cpuid: 0x%8.8" PRIx32
"", cpuid
);
2575 if (cortex_m
->core_info
->flags
& CORTEX_M_F_HAS_FPV4
) {
2576 target_read_u32(target
, MVFR0
, &mvfr0
);
2577 target_read_u32(target
, MVFR1
, &mvfr1
);
2579 /* test for floating point feature on Cortex-M4 */
2580 if ((mvfr0
== MVFR0_DEFAULT_M4
) && (mvfr1
== MVFR1_DEFAULT_M4
)) {
2581 LOG_TARGET_DEBUG(target
, "%s floating point feature FPv4_SP found", cortex_m
->core_info
->name
);
2582 armv7m
->fp_feature
= FPV4_SP
;
2584 } else if (cortex_m
->core_info
->flags
& CORTEX_M_F_HAS_FPV5
) {
2585 target_read_u32(target
, MVFR0
, &mvfr0
);
2586 target_read_u32(target
, MVFR1
, &mvfr1
);
2588 /* test for floating point features on Cortex-M7 */
2589 if ((mvfr0
== MVFR0_DEFAULT_M7_SP
) && (mvfr1
== MVFR1_DEFAULT_M7_SP
)) {
2590 LOG_TARGET_DEBUG(target
, "%s floating point feature FPv5_SP found", cortex_m
->core_info
->name
);
2591 armv7m
->fp_feature
= FPV5_SP
;
2592 } else if ((mvfr0
== MVFR0_DEFAULT_M7_DP
) && (mvfr1
== MVFR1_DEFAULT_M7_DP
)) {
2593 LOG_TARGET_DEBUG(target
, "%s floating point feature FPv5_DP found", cortex_m
->core_info
->name
);
2594 armv7m
->fp_feature
= FPV5_DP
;
2598 /* VECTRESET is supported only on ARMv7-M cores */
2599 cortex_m
->vectreset_supported
= armv7m
->arm
.arch
== ARM_ARCH_V7M
;
2601 /* Check for FPU, otherwise mark FPU register as non-existent */
2602 if (armv7m
->fp_feature
== FP_NONE
)
2603 for (size_t idx
= ARMV7M_FPU_FIRST_REG
; idx
<= ARMV7M_FPU_LAST_REG
; idx
++)
2604 armv7m
->arm
.core_cache
->reg_list
[idx
].exist
= false;
2606 if (!cortex_m_has_tz(target
))
2607 for (size_t idx
= ARMV8M_FIRST_REG
; idx
<= ARMV8M_LAST_REG
; idx
++)
2608 armv7m
->arm
.core_cache
->reg_list
[idx
].exist
= false;
2610 if (!armv7m
->is_hla_target
) {
2611 if (cortex_m
->core_info
->flags
& CORTEX_M_F_TAR_AUTOINCR_BLOCK_4K
)
2612 /* Cortex-M3/M4 have 4096 bytes autoincrement range,
2613 * s. ARM IHI 0031C: MEM-AP 7.2.2 */
2614 armv7m
->debug_ap
->tar_autoincr_block
= (1 << 12);
2617 retval
= target_read_u32(target
, DCB_DHCSR
, &cortex_m
->dcb_dhcsr
);
2618 if (retval
!= ERROR_OK
)
2621 /* Don't cumulate sticky S_RESET_ST at the very first read of DHCSR
2622 * as S_RESET_ST may indicate a reset that happened long time ago
2623 * (most probably the power-on reset before OpenOCD was started).
2624 * As we are just initializing the debug system we do not need
2625 * to call cortex_m_endreset_event() in the following poll.
2627 if (!cortex_m
->dcb_dhcsr_sticky_is_recent
) {
2628 cortex_m
->dcb_dhcsr_sticky_is_recent
= true;
2629 if (cortex_m
->dcb_dhcsr
& S_RESET_ST
) {
2630 LOG_TARGET_DEBUG(target
, "reset happened some time ago, ignore");
2631 cortex_m
->dcb_dhcsr
&= ~S_RESET_ST
;
2634 cortex_m_cumulate_dhcsr_sticky(cortex_m
, cortex_m
->dcb_dhcsr
);
2636 if (!(cortex_m
->dcb_dhcsr
& C_DEBUGEN
)) {
2637 /* Enable debug requests */
2638 uint32_t dhcsr
= (cortex_m
->dcb_dhcsr
| C_DEBUGEN
) & ~(C_HALT
| C_STEP
| C_MASKINTS
);
2640 retval
= target_write_u32(target
, DCB_DHCSR
, DBGKEY
| (dhcsr
& 0x0000FFFFUL
));
2641 if (retval
!= ERROR_OK
)
2643 cortex_m
->dcb_dhcsr
= dhcsr
;
2646 /* Configure trace modules */
2647 retval
= target_write_u32(target
, DCB_DEMCR
, TRCENA
| armv7m
->demcr
);
2648 if (retval
!= ERROR_OK
)
2651 if (armv7m
->trace_config
.itm_deferred_config
)
2652 armv7m_trace_itm_config(target
);
2654 /* NOTE: FPB and DWT are both optional. */
2657 target_read_u32(target
, FP_CTRL
, &fpcr
);
2658 /* bits [14:12] and [7:4] */
2659 cortex_m
->fp_num_code
= ((fpcr
>> 8) & 0x70) | ((fpcr
>> 4) & 0xF);
2660 cortex_m
->fp_num_lit
= (fpcr
>> 8) & 0xF;
2661 /* Detect flash patch revision, see RM DDI 0403E.b page C1-817.
2662 Revision is zero base, fp_rev == 1 means Rev.2 ! */
2663 cortex_m
->fp_rev
= (fpcr
>> 28) & 0xf;
2664 free(cortex_m
->fp_comparator_list
);
2665 cortex_m
->fp_comparator_list
= calloc(
2666 cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
,
2667 sizeof(struct cortex_m_fp_comparator
));
2668 cortex_m
->fpb_enabled
= fpcr
& 1;
2669 for (unsigned int i
= 0; i
< cortex_m
->fp_num_code
+ cortex_m
->fp_num_lit
; i
++) {
2670 cortex_m
->fp_comparator_list
[i
].type
=
2671 (i
< cortex_m
->fp_num_code
) ? FPCR_CODE
: FPCR_LITERAL
;
2672 cortex_m
->fp_comparator_list
[i
].fpcr_address
= FP_COMP0
+ 4 * i
;
2674 /* make sure we clear any breakpoints enabled on the target */
2675 target_write_u32(target
, cortex_m
->fp_comparator_list
[i
].fpcr_address
, 0);
2677 LOG_TARGET_DEBUG(target
, "FPB fpcr 0x%" PRIx32
", numcode %i, numlit %i",
2679 cortex_m
->fp_num_code
,
2680 cortex_m
->fp_num_lit
);
2683 cortex_m_dwt_free(target
);
2684 cortex_m_dwt_setup(cortex_m
, target
);
2686 /* These hardware breakpoints only work for code in flash! */
2687 LOG_TARGET_INFO(target
, "target has %d breakpoints, %d watchpoints",
2688 cortex_m
->fp_num_code
,
2689 cortex_m
->dwt_num_comp
);
2695 static int cortex_m_dcc_read(struct target
*target
, uint8_t *value
, uint8_t *ctrl
)
2697 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
2702 retval
= mem_ap_read_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2703 if (retval
!= ERROR_OK
)
2706 dcrdr
= target_buffer_get_u16(target
, buf
);
2707 *ctrl
= (uint8_t)dcrdr
;
2708 *value
= (uint8_t)(dcrdr
>> 8);
2710 LOG_TARGET_DEBUG(target
, "data 0x%x ctrl 0x%x", *value
, *ctrl
);
2712 /* write ack back to software dcc register
2713 * signify we have read data */
2714 if (dcrdr
& (1 << 0)) {
2715 target_buffer_set_u16(target
, buf
, 0);
2716 retval
= mem_ap_write_buf_noincr(armv7m
->debug_ap
, buf
, 2, 1, DCB_DCRDR
);
2717 if (retval
!= ERROR_OK
)
2724 static int cortex_m_target_request_data(struct target
*target
,
2725 uint32_t size
, uint8_t *buffer
)
2731 for (i
= 0; i
< (size
* 4); i
++) {
2732 int retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2733 if (retval
!= ERROR_OK
)
2741 static int cortex_m_handle_target_request(void *priv
)
2743 struct target
*target
= priv
;
2744 if (!target_was_examined(target
))
2747 if (!target
->dbg_msg_enabled
)
2750 if (target
->state
== TARGET_RUNNING
) {
2755 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2756 if (retval
!= ERROR_OK
)
2759 /* check if we have data */
2760 if (ctrl
& (1 << 0)) {
2763 /* we assume target is quick enough */
2765 for (int i
= 1; i
<= 3; i
++) {
2766 retval
= cortex_m_dcc_read(target
, &data
, &ctrl
);
2767 if (retval
!= ERROR_OK
)
2769 request
|= ((uint32_t)data
<< (i
* 8));
2771 target_request(target
, request
);
2778 static int cortex_m_init_arch_info(struct target
*target
,
2779 struct cortex_m_common
*cortex_m
, struct adiv5_dap
*dap
)
2781 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2783 armv7m_init_arch_info(target
, armv7m
);
2785 /* default reset mode is to use srst if fitted
2786 * if not it will use CORTEX_M3_RESET_VECTRESET */
2787 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2789 armv7m
->arm
.dap
= dap
;
2791 /* register arch-specific functions */
2792 armv7m
->examine_debug_reason
= cortex_m_examine_debug_reason
;
2794 armv7m
->post_debug_entry
= NULL
;
2796 armv7m
->pre_restore_context
= NULL
;
2798 armv7m
->load_core_reg_u32
= cortex_m_load_core_reg_u32
;
2799 armv7m
->store_core_reg_u32
= cortex_m_store_core_reg_u32
;
2801 target_register_timer_callback(cortex_m_handle_target_request
, 1,
2802 TARGET_TIMER_TYPE_PERIODIC
, target
);
2807 static int cortex_m_target_create(struct target
*target
, Jim_Interp
*interp
)
2809 struct adiv5_private_config
*pc
;
2811 pc
= (struct adiv5_private_config
*)target
->private_config
;
2812 if (adiv5_verify_config(pc
) != ERROR_OK
)
2815 struct cortex_m_common
*cortex_m
= calloc(1, sizeof(struct cortex_m_common
));
2817 LOG_TARGET_ERROR(target
, "No memory creating target");
2821 cortex_m
->common_magic
= CORTEX_M_COMMON_MAGIC
;
2822 cortex_m
->apsel
= pc
->ap_num
;
2824 cortex_m_init_arch_info(target
, cortex_m
, pc
->dap
);
2829 /*--------------------------------------------------------------------------*/
2831 static int cortex_m_verify_pointer(struct command_invocation
*cmd
,
2832 struct cortex_m_common
*cm
)
2834 if (!is_cortex_m_with_dap_access(cm
)) {
2835 command_print(cmd
, "target is not a Cortex-M");
2836 return ERROR_TARGET_INVALID
;
2842 * Only stuff below this line should need to verify that its target
2843 * is a Cortex-M3. Everything else should have indirected through the
2844 * cortexm3_target structure, which is only used with CM3 targets.
2847 COMMAND_HANDLER(handle_cortex_m_vector_catch_command
)
2849 struct target
*target
= get_current_target(CMD_CTX
);
2850 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2851 struct armv7m_common
*armv7m
= &cortex_m
->armv7m
;
2855 static const struct {
2859 { "hard_err", VC_HARDERR
, },
2860 { "int_err", VC_INTERR
, },
2861 { "bus_err", VC_BUSERR
, },
2862 { "state_err", VC_STATERR
, },
2863 { "chk_err", VC_CHKERR
, },
2864 { "nocp_err", VC_NOCPERR
, },
2865 { "mm_err", VC_MMERR
, },
2866 { "reset", VC_CORERESET
, },
2869 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2870 if (retval
!= ERROR_OK
)
2873 if (!target_was_examined(target
)) {
2874 LOG_TARGET_ERROR(target
, "Target not examined yet");
2878 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2879 if (retval
!= ERROR_OK
)
2885 if (CMD_ARGC
== 1) {
2886 if (strcmp(CMD_ARGV
[0], "all") == 0) {
2887 catch = VC_HARDERR
| VC_INTERR
| VC_BUSERR
2888 | VC_STATERR
| VC_CHKERR
| VC_NOCPERR
2889 | VC_MMERR
| VC_CORERESET
;
2891 } else if (strcmp(CMD_ARGV
[0], "none") == 0)
2894 while (CMD_ARGC
-- > 0) {
2896 for (i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2897 if (strcmp(CMD_ARGV
[CMD_ARGC
], vec_ids
[i
].name
) != 0)
2899 catch |= vec_ids
[i
].mask
;
2902 if (i
== ARRAY_SIZE(vec_ids
)) {
2903 LOG_TARGET_ERROR(target
, "No CM3 vector '%s'", CMD_ARGV
[CMD_ARGC
]);
2904 return ERROR_COMMAND_SYNTAX_ERROR
;
2908 /* For now, armv7m->demcr only stores vector catch flags. */
2909 armv7m
->demcr
= catch;
2914 /* write, but don't assume it stuck (why not??) */
2915 retval
= mem_ap_write_u32(armv7m
->debug_ap
, DCB_DEMCR
, demcr
);
2916 if (retval
!= ERROR_OK
)
2918 retval
= mem_ap_read_atomic_u32(armv7m
->debug_ap
, DCB_DEMCR
, &demcr
);
2919 if (retval
!= ERROR_OK
)
2922 /* FIXME be sure to clear DEMCR on clean server shutdown.
2923 * Otherwise the vector catch hardware could fire when there's
2924 * no debugger hooked up, causing much confusion...
2928 for (unsigned i
= 0; i
< ARRAY_SIZE(vec_ids
); i
++) {
2929 command_print(CMD
, "%9s: %s", vec_ids
[i
].name
,
2930 (demcr
& vec_ids
[i
].mask
) ? "catch" : "ignore");
2936 COMMAND_HANDLER(handle_cortex_m_mask_interrupts_command
)
2938 struct target
*target
= get_current_target(CMD_CTX
);
2939 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2942 static const struct nvp nvp_maskisr_modes
[] = {
2943 { .name
= "auto", .value
= CORTEX_M_ISRMASK_AUTO
},
2944 { .name
= "off", .value
= CORTEX_M_ISRMASK_OFF
},
2945 { .name
= "on", .value
= CORTEX_M_ISRMASK_ON
},
2946 { .name
= "steponly", .value
= CORTEX_M_ISRMASK_STEPONLY
},
2947 { .name
= NULL
, .value
= -1 },
2949 const struct nvp
*n
;
2952 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2953 if (retval
!= ERROR_OK
)
2956 if (target
->state
!= TARGET_HALTED
) {
2957 command_print(CMD
, "Error: target must be stopped for \"%s\" command", CMD_NAME
);
2958 return ERROR_TARGET_NOT_HALTED
;
2962 n
= nvp_name2value(nvp_maskisr_modes
, CMD_ARGV
[0]);
2964 return ERROR_COMMAND_SYNTAX_ERROR
;
2965 cortex_m
->isrmasking_mode
= n
->value
;
2966 cortex_m_set_maskints_for_halt(target
);
2969 n
= nvp_value2name(nvp_maskisr_modes
, cortex_m
->isrmasking_mode
);
2970 command_print(CMD
, "cortex_m interrupt mask %s", n
->name
);
2975 COMMAND_HANDLER(handle_cortex_m_reset_config_command
)
2977 struct target
*target
= get_current_target(CMD_CTX
);
2978 struct cortex_m_common
*cortex_m
= target_to_cm(target
);
2982 retval
= cortex_m_verify_pointer(CMD
, cortex_m
);
2983 if (retval
!= ERROR_OK
)
2987 if (strcmp(*CMD_ARGV
, "sysresetreq") == 0)
2988 cortex_m
->soft_reset_config
= CORTEX_M_RESET_SYSRESETREQ
;
2990 else if (strcmp(*CMD_ARGV
, "vectreset") == 0) {
2991 if (target_was_examined(target
)
2992 && !cortex_m
->vectreset_supported
)
2993 LOG_TARGET_WARNING(target
, "VECTRESET is not supported on your Cortex-M core!");
2995 cortex_m
->soft_reset_config
= CORTEX_M_RESET_VECTRESET
;
2998 return ERROR_COMMAND_SYNTAX_ERROR
;
3001 switch (cortex_m
->soft_reset_config
) {
3002 case CORTEX_M_RESET_SYSRESETREQ
:
3003 reset_config
= "sysresetreq";
3006 case CORTEX_M_RESET_VECTRESET
:
3007 reset_config
= "vectreset";
3011 reset_config
= "unknown";
3015 command_print(CMD
, "cortex_m reset_config %s", reset_config
);
3020 static const struct command_registration cortex_m_exec_command_handlers
[] = {
3023 .handler
= handle_cortex_m_mask_interrupts_command
,
3024 .mode
= COMMAND_EXEC
,
3025 .help
= "mask cortex_m interrupts",
3026 .usage
= "['auto'|'on'|'off'|'steponly']",
3029 .name
= "vector_catch",
3030 .handler
= handle_cortex_m_vector_catch_command
,
3031 .mode
= COMMAND_EXEC
,
3032 .help
= "configure hardware vectors to trigger debug entry",
3033 .usage
= "['all'|'none'|('bus_err'|'chk_err'|...)*]",
3036 .name
= "reset_config",
3037 .handler
= handle_cortex_m_reset_config_command
,
3038 .mode
= COMMAND_ANY
,
3039 .help
= "configure software reset handling",
3040 .usage
= "['sysresetreq'|'vectreset']",
3043 .chain
= smp_command_handlers
,
3045 COMMAND_REGISTRATION_DONE
3047 static const struct command_registration cortex_m_command_handlers
[] = {
3049 .chain
= armv7m_command_handlers
,
3052 .chain
= armv7m_trace_command_handlers
,
3054 /* START_DEPRECATED_TPIU */
3056 .chain
= arm_tpiu_deprecated_command_handlers
,
3058 /* END_DEPRECATED_TPIU */
3061 .mode
= COMMAND_EXEC
,
3062 .help
= "Cortex-M command group",
3064 .chain
= cortex_m_exec_command_handlers
,
3067 .chain
= rtt_target_command_handlers
,
3069 COMMAND_REGISTRATION_DONE
3072 struct target_type cortexm_target
= {
3075 .poll
= cortex_m_poll
,
3076 .arch_state
= armv7m_arch_state
,
3078 .target_request_data
= cortex_m_target_request_data
,
3080 .halt
= cortex_m_halt
,
3081 .resume
= cortex_m_resume
,
3082 .step
= cortex_m_step
,
3084 .assert_reset
= cortex_m_assert_reset
,
3085 .deassert_reset
= cortex_m_deassert_reset
,
3086 .soft_reset_halt
= cortex_m_soft_reset_halt
,
3088 .get_gdb_arch
= arm_get_gdb_arch
,
3089 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
3091 .read_memory
= cortex_m_read_memory
,
3092 .write_memory
= cortex_m_write_memory
,
3093 .checksum_memory
= armv7m_checksum_memory
,
3094 .blank_check_memory
= armv7m_blank_check_memory
,
3096 .run_algorithm
= armv7m_run_algorithm
,
3097 .start_algorithm
= armv7m_start_algorithm
,
3098 .wait_algorithm
= armv7m_wait_algorithm
,
3100 .add_breakpoint
= cortex_m_add_breakpoint
,
3101 .remove_breakpoint
= cortex_m_remove_breakpoint
,
3102 .add_watchpoint
= cortex_m_add_watchpoint
,
3103 .remove_watchpoint
= cortex_m_remove_watchpoint
,
3104 .hit_watchpoint
= cortex_m_hit_watchpoint
,
3106 .commands
= cortex_m_command_handlers
,
3107 .target_create
= cortex_m_target_create
,
3108 .target_jim_configure
= adiv5_jim_configure
,
3109 .init_target
= cortex_m_init_target
,
3110 .examine
= cortex_m_examine
,
3111 .deinit_target
= cortex_m_deinit_target
,
3113 .profiling
= cortex_m_profiling
,