1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2009 by Dirk Behme *
12 * dirk.behme@gmail.com - copy from cortex_m3 *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
29 * Cortex-A8(tm) TRM, ARM DDI 0344H *
31 ***************************************************************************/
36 #include "cortex_a8.h"
37 #include "target_request.h"
38 #include "target_type.h"
42 int cortex_a8_register_commands(struct command_context_s
*cmd_ctx
);
44 /* forward declarations */
45 int cortex_a8_target_create(struct target_s
*target
, Jim_Interp
*interp
);
47 target_type_t cortexa8_target
=
52 .arch_state
= armv7m_arch_state
,
54 .target_request_data
= NULL
,
61 .deassert_reset
= NULL
,
62 .soft_reset_halt
= NULL
,
64 .get_gdb_reg_list
= armv7m_get_gdb_reg_list
,
66 .read_memory
= cortex_a8_read_memory
,
67 .write_memory
= cortex_a8_write_memory
,
68 .bulk_write_memory
= NULL
,
69 .checksum_memory
= NULL
,
70 .blank_check_memory
= NULL
,
72 .run_algorithm
= armv7m_run_algorithm
,
74 .add_breakpoint
= NULL
,
75 .remove_breakpoint
= NULL
,
76 .add_watchpoint
= NULL
,
77 .remove_watchpoint
= NULL
,
79 .register_commands
= cortex_a8_register_commands
,
80 .target_create
= cortex_a8_target_create
,
86 int cortex_a8_dcc_read(swjdp_common_t
*swjdp
, uint8_t *value
, uint8_t *ctrl
)
90 mem_ap_read_buf_u16( swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
91 *ctrl
= (uint8_t)dcrdr
;
92 *value
= (uint8_t)(dcrdr
>> 8);
94 LOG_DEBUG("data 0x%x ctrl 0x%x", *value
, *ctrl
);
96 /* write ack back to software dcc register
97 * signify we have read data */
101 mem_ap_write_buf_u16( swjdp
, (uint8_t*)&dcrdr
, 1, DCB_DCRDR
);
107 int cortex_a8_read_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
109 /* get pointers to arch-specific information */
110 armv7m_common_t
*armv7m
= target
->arch_info
;
111 swjdp_common_t
*swjdp
= &armv7m
->swjdp_info
;
114 /* sanitize arguments */
115 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
116 return ERROR_INVALID_ARGUMENTS
;
118 /* cortex_a8 handles unaligned memory access */
123 retval
= mem_ap_read_buf_u32(swjdp
, buffer
, 4 * count
, address
);
126 retval
= mem_ap_read_buf_u16(swjdp
, buffer
, 2 * count
, address
);
129 retval
= mem_ap_read_buf_u8(swjdp
, buffer
, count
, address
);
132 LOG_ERROR("BUG: we shouldn't get here");
139 int cortex_a8_write_memory(struct target_s
*target
, uint32_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
)
141 /* get pointers to arch-specific information */
142 armv7m_common_t
*armv7m
= target
->arch_info
;
143 swjdp_common_t
*swjdp
= &armv7m
->swjdp_info
;
146 /* sanitize arguments */
147 if (((size
!= 4) && (size
!= 2) && (size
!= 1)) || (count
== 0) || !(buffer
))
148 return ERROR_INVALID_ARGUMENTS
;
153 retval
= mem_ap_write_buf_u32(swjdp
, buffer
, 4 * count
, address
);
156 retval
= mem_ap_write_buf_u16(swjdp
, buffer
, 2 * count
, address
);
159 retval
= mem_ap_write_buf_u8(swjdp
, buffer
, count
, address
);
162 LOG_ERROR("BUG: we shouldn't get here");
169 int cortex_a8_handle_target_request(void *priv
)
171 target_t
*target
= priv
;
172 if (!target_was_examined(target
))
174 armv7m_common_t
*armv7m
= target
->arch_info
;
175 swjdp_common_t
*swjdp
= &armv7m
->swjdp_info
;
177 if (!target
->dbg_msg_enabled
)
180 if (target
->state
== TARGET_RUNNING
)
185 cortex_a8_dcc_read(swjdp
, &data
, &ctrl
);
187 /* check if we have data */
192 /* we assume target is quick enough */
194 cortex_a8_dcc_read(swjdp
, &data
, &ctrl
);
195 request
|= (data
<< 8);
196 cortex_a8_dcc_read(swjdp
, &data
, &ctrl
);
197 request
|= (data
<< 16);
198 cortex_a8_dcc_read(swjdp
, &data
, &ctrl
);
199 request
|= (data
<< 24);
200 target_request(target
, request
);
207 int cortex_a8_init_arch_info(target_t
*target
, cortex_a8_common_t
*cortex_a8
, jtag_tap_t
*tap
)
209 armv7m_common_t
*armv7m
;
210 armv7m
= &cortex_a8
->armv7m
;
212 /* prepare JTAG information for the new target */
213 cortex_a8
->jtag_info
.tap
= tap
;
214 cortex_a8
->jtag_info
.scann_size
= 4;
216 armv7m
->swjdp_info
.dp_select_value
= -1;
217 armv7m
->swjdp_info
.ap_csw_value
= -1;
218 armv7m
->swjdp_info
.ap_tar_value
= -1;
219 armv7m
->swjdp_info
.jtag_info
= &cortex_a8
->jtag_info
;
221 /* initialize arch-specific breakpoint handling */
223 cortex_a8
->common_magic
= CORTEX_A8_COMMON_MAGIC
;
224 cortex_a8
->arch_info
= NULL
;
226 /* register arch-specific functions */
227 armv7m
->examine_debug_reason
= NULL
;
229 armv7m
->pre_debug_entry
= NULL
;
230 armv7m
->post_debug_entry
= NULL
;
232 armv7m
->pre_restore_context
= NULL
;
233 armv7m
->post_restore_context
= NULL
;
235 armv7m_init_arch_info(target
, armv7m
);
236 armv7m
->arch_info
= cortex_a8
;
237 armv7m
->load_core_reg_u32
= NULL
;
238 armv7m
->store_core_reg_u32
= NULL
;
240 target_register_timer_callback(cortex_a8_handle_target_request
, 1, 1, target
);
245 int cortex_a8_target_create(struct target_s
*target
, Jim_Interp
*interp
)
247 cortex_a8_common_t
*cortex_a8
= calloc(1,sizeof(cortex_a8_common_t
));
249 cortex_a8_init_arch_info(target
, cortex_a8
, target
->tap
);
254 int cortex_a8_register_commands(struct command_context_s
*cmd_ctx
)
258 retval
= armv7m_register_commands(cmd_ctx
);
260 register_command(cmd_ctx
, NULL
, "cortex_a8", NULL
, COMMAND_ANY
, "cortex_a8 specific commands");
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