src/target/armv8_opcodes.h

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 /*
   4  * Copyright (C) 2015 by pierrr kuo <vichy.kuo@gmail.com>
   5  */
   6
   7 #ifndef OPENOCD_TARGET_ARMV8_OPCODES_H
   8 #define OPENOCD_TARGET_ARMV8_OPCODES_H
   9
  10 #include "arm_opcodes.h"
  11
  12 #define SYSTEM_CUREL_MASK               0xC0
  13 #define SYSTEM_CUREL_SHIFT              6
  14 #define SYSTEM_CUREL_EL0                0x0
  15 #define SYSTEM_CUREL_EL1                0x1
  16 #define SYSTEM_CUREL_EL2                0x2
  17 #define SYSTEM_CUREL_EL3                0x3
  18 #define SYSTEM_CUREL_NONCH              0xF
  19 #define SYSTEM_AARCH64                  0x1
  20
  21 #define SYSTEM_AAR64_MODE_EL0T  0x0
  22 #define SYSTEM_AAR64_MODE_EL1T  0x4
  23 #define SYSTEM_AAR64_MODE_EL1H  0x5
  24 #define SYSTEM_AAR64_MODE_EL2T  0x8
  25 #define SYSTEM_AAR64_MODE_EL2H  0x9
  26 #define SYSTEM_AAR64_MODE_EL3T  0xC
  27 #define SYSTEM_AAR64_MODE_EL3H  0xd
  28
  29 #define SYSTEM_DAIF                     0b1101101000010001
  30 #define SYSTEM_DAIF_MASK                0x3C0
  31 #define SYSTEM_DAIF_SHIFT               6
  32
  33 #define SYSTEM_ELR_EL1                  0b1100001000000001
  34 #define SYSTEM_ELR_EL2                  0b1110001000000001
  35 #define SYSTEM_ELR_EL3                  0b1111001000000001
  36
  37 #define SYSTEM_SCTLR_EL1        0b1100000010000000
  38 #define SYSTEM_SCTLR_EL2        0b1110000010000000
  39 #define SYSTEM_SCTLR_EL3        0b1111000010000000
  40
  41 #define SYSTEM_FPCR                     0b1101101000100000
  42 #define SYSTEM_FPSR                     0b1101101000100001
  43 #define SYSTEM_DAIF                     0b1101101000010001
  44 #define SYSTEM_NZCV                     0b1101101000010000
  45 #define SYSTEM_SP_EL0                   0b1100001000001000
  46 #define SYSTEM_SP_EL1                   0b1110001000001000
  47 #define SYSTEM_SP_EL2                   0b1111001000001000
  48 #define SYSTEM_SP_SEL                   0b1100001000010000
  49 #define SYSTEM_SPSR_ABT                 0b1110001000011001
  50 #define SYSTEM_SPSR_FIQ                 0b1110001000011011
  51 #define SYSTEM_SPSR_IRQ                 0b1110001000011000
  52 #define SYSTEM_SPSR_UND                 0b1110001000011010
  53
  54 #define SYSTEM_SPSR_EL1                 0b1100001000000000
  55 #define SYSTEM_SPSR_EL2                 0b1110001000000000
  56 #define SYSTEM_SPSR_EL3                 0b1111001000000000
  57
  58 #define SYSTEM_ISR_EL1                  0b1100011000001000
  59
  60 #define SYSTEM_DBG_DSPSR_EL0    0b1101101000101000
  61 #define SYSTEM_DBG_DLR_EL0              0b1101101000101001
  62 #define SYSTEM_DBG_DTRRX_EL0    0b1001100000101000
  63 #define SYSTEM_DBG_DTRTX_EL0    0b1001100000101000
  64 #define SYSTEM_DBG_DBGDTR_EL0   0b1001100000100000
  65
  66 #define SYSTEM_CCSIDR                   0b1100100000000000
  67 #define SYSTEM_CLIDR                    0b1100100000000001
  68 #define SYSTEM_CSSELR                   0b1101000000000000
  69 #define SYSTEM_CTYPE                    0b1101100000000001
  70 #define SYSTEM_CTR                              0b1101100000000001
  71
  72 #define SYSTEM_DCCISW                   0b0100001111110010
  73 #define SYSTEM_DCCSW                    0b0100001111010010
  74 #define SYSTEM_ICIVAU                   0b0101101110101001
  75 #define SYSTEM_DCCVAU                   0b0101101111011001
  76 #define SYSTEM_DCCIVAC                  0b0101101111110001
  77
  78 #define SYSTEM_MPIDR                    0b1100000000000101
  79
  80 #define SYSTEM_TCR_EL1                  0b1100000100000010
  81 #define SYSTEM_TCR_EL2                  0b1110000100000010
  82 #define SYSTEM_TCR_EL3                  0b1111000100000010
  83
  84 #define SYSTEM_TTBR0_EL1                0b1100000100000000
  85 #define SYSTEM_TTBR0_EL2                0b1110000100000000
  86 #define SYSTEM_TTBR0_EL3                0b1111000100000000
  87 #define SYSTEM_TTBR1_EL1                0b1100000100000001
  88
  89 /* ARMv8 address translation */
  90 #define SYSTEM_PAR_EL1                  0b1100001110100000
  91 #define SYSTEM_ATS12E0R                 0b0110001111000110
  92 #define SYSTEM_ATS12E1R                 0b0110001111000100
  93 #define SYSTEM_ATS1E2R                  0b0110001111000000
  94 #define SYSTEM_ATS1E3R                  0b0111001111000000
  95
  96 /* fault status and fault address */
  97 #define SYSTEM_FAR_EL1                  0b1100001100000000
  98 #define SYSTEM_FAR_EL2                  0b1110001100000000
  99 #define SYSTEM_FAR_EL3                  0b1111001100000000
 100 #define SYSTEM_ESR_EL1                  0b1100001010010000
 101 #define SYSTEM_ESR_EL2                  0b1110001010010000
 102 #define SYSTEM_ESR_EL3                  0b1111001010010000
 103
 104 #define ARMV8_MRS_DSPSR(rt)     (0xd53b4500 | (rt))
 105 #define ARMV8_MSR_DSPSR(rt)     (0xd51b4500 | (rt))
 106 #define ARMV8_MRS_DLR(rt)       (0xd53b4520 | (rt))
 107 #define ARMV8_MSR_DLR(rt)       (0xd51b4520 | (rt))
 108
 109 /* T32 instruction to access coprocessor registers */
 110 #define ARMV8_MCR_T1(cp, crn, opc1, crm, opc2, rt) ARMV4_5_MCR(cp, opc1, rt, crn, crm, opc2)
 111 #define ARMV8_MRC_T1(cp, crn, opc1, crm, opc2, rt) ARMV4_5_MRC(cp, opc1, rt, crn, crm, opc2)
 112
 113 /* T32 instructions to access DSPSR and DLR */
 114 #define ARMV8_MRC_DSPSR(rt) ARMV8_MRC_T1(15, 4, 3, 5, 0, rt)
 115 #define ARMV8_MCR_DSPSR(rt) ARMV8_MCR_T1(15, 4, 3, 5, 0, rt)
 116 #define ARMV8_MRC_DLR(rt)       ARMV8_MRC_T1(15, 4, 3, 5, 1, rt)
 117 #define ARMV8_MCR_DLR(rt)       ARMV8_MCR_T1(15, 4, 3, 5, 1, rt)
 118
 119 #define ARMV8_DCPS1(im)         (0xd4a00001 | (((im) & 0xFFFF) << 5))
 120 #define ARMV8_DCPS2(im)         (0xd4a00002 | (((im) & 0xFFFF) << 5))
 121 #define ARMV8_DCPS3(im)         (0xd4a00003 | (((im) & 0xFFFF) << 5))
 122 #define ARMV8_DCPS(el, im)      (0xd4a00000 | (((im) & 0xFFFF) << 5) | el)
 123 #define ARMV8_DCPS_T1(el)       (0xf78f8000 | el)
 124 #define ARMV8_DRPS              0xd6bf03e0
 125 #define ARMV8_ERET_T1           0xf3de8f00
 126
 127 #define ARMV8_DSB_SY                            0xd5033F9F
 128 #define ARMV8_DSB_SY_T1                         0xf3bf8f4f
 129 #define ARMV8_ISB                               0xd5033fdf
 130 #define ARMV8_ISB_SY_T1                         0xf3bf8f6f
 131
 132 #define ARMV8_MRS(system, rt)   (0xd5300000 | ((system) << 5) | (rt))
 133 /* ARM V8 Move to system register. */
 134 #define ARMV8_MSR_GP(system, rt) \
 135         (0xd5100000 | ((system) << 5) | (rt))
 136 /* ARM V8 Move immediate to process state field. */
 137 #define ARMV8_MSR_IM(op1, crm, op2) \
 138         (0xd500401f | ((op1) << 16)  | ((crm) << 8) | ((op2) << 5))
 139
 140 #define ARMV8_MRS_T1(r, m1, rd, m) (0xF3E08020 | (r << 20) | (m1 << 16) | (rd << 8) | (m << 4))
 141 #define ARMV8_MRS_xPSR_T1(r, rd) (0xF3EF8000 | (r << 20) | (rd << 8))
 142 #define ARMV8_MSR_GP_T1(r, m1, rd, m) (0xF3808020 | (r << 20) | (m1 << 8) | (rd << 16) | (m << 4))
 143 #define ARMV8_MSR_GP_xPSR_T1(r, rn, mask) (0xF3808000 | (r << 20) | (rn << 16) | (mask << 8))
 144
 145 #define ARMV8_BKPT(im) (0xD4200000 | ((im & 0xffff) << 5))
 146 #define ARMV8_HLT(im) (0x0D4400000 | ((im & 0xffff) << 5))
 147 #define ARMV8_HLT_A1(im) (0xE1000070 | ((im & 0xFFF0) << 4) | (im & 0xF))
 148 #define ARMV8_HLT_T1(im) (0xba80 | (im & 0x3f))
 149
 150 #define ARMV8_MOVFSP_64(rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (rt))
 151 #define ARMV8_MOVTSP_64(rt) ((1 << 31) | 0x11000000 | (rt << 5) | (0x1F))
 152 #define ARMV8_MOVFSP_32(rt) (0x11000000 | (0x1f << 5) | (rt))
 153 #define ARMV8_MOVTSP_32(rt) (0x11000000 | (rt << 5) | (0x1F))
 154
 155 #define ARMV8_LDRB_IP(rd, rn) (0x38401400 | (rn << 5) | rd)
 156 #define ARMV8_LDRH_IP(rd, rn) (0x78402400 | (rn << 5) | rd)
 157 #define ARMV8_LDRW_IP(rd, rn) (0xb8404400 | (rn << 5) | rd)
 158
 159 #define ARMV8_LDRB_IP_T3(rd, rn) (0xf8100b01 | (rn << 16) | (rd << 12))
 160 #define ARMV8_LDRH_IP_T3(rd, rn) (0xf8300b02 | (rn << 16) | (rd << 12))
 161 #define ARMV8_LDRW_IP_T3(rd, rn) (0xf8500b04 | (rn << 16) | (rd << 12))
 162
 163 #define ARMV8_STRB_IP(rd, rn) (0x38001400 | (rn << 5) | rd)
 164 #define ARMV8_STRH_IP(rd, rn) (0x78002400 | (rn << 5) | rd)
 165 #define ARMV8_STRW_IP(rd, rn) (0xb8004400 | (rn << 5) | rd)
 166
 167 #define ARMV8_STRB_IP_T3(rd, rn) (0xf8000b01 | (rn << 16) | (rd << 12))
 168 #define ARMV8_STRH_IP_T3(rd, rn) (0xf8200b02 | (rn << 16) | (rd << 12))
 169 #define ARMV8_STRW_IP_T3(rd, rn) (0xf8400b04 | (rn << 16) | (rd << 12))
 170
 171 #define ARMV8_MOV_GPR_VFP(rd, rn, index) (0x4e083c00 | (index << 20) | (rn << 5) | rd)
 172 #define ARMV8_MOV_VFP_GPR(rd, rn, index) (0x4e081c00 | (index << 20) | (rn << 5) | rd)
 173
 174 #define ARMV8_MRS_FPCR(rt)      (0xd53b4400 | (rt))
 175 #define ARMV8_MRS_FPSR(rt)      (0xd53b4420 | (rt))
 176 #define ARMV8_MSR_FPCR(rt)      (0xd51b4400 | (rt))
 177 #define ARMV8_MSR_FPSR(rt)      (0xd51b4420 | (rt))
 178
 179 #define ARMV8_SYS(system, rt) (0xD5080000 | ((system) << 5) | rt)
 180
 181 enum armv8_opcode {
 182         READ_REG_CTR,
 183         READ_REG_CLIDR,
 184         READ_REG_CSSELR,
 185         READ_REG_CCSIDR,
 186         WRITE_REG_CSSELR,
 187         READ_REG_MPIDR,
 188         READ_REG_DTRRX,
 189         WRITE_REG_DTRTX,
 190         WRITE_REG_DSPSR,
 191         READ_REG_DSPSR,
 192         ARMV8_OPC_DSB_SY,
 193         ARMV8_OPC_DCPS,
 194         ARMV8_OPC_DRPS,
 195         ARMV8_OPC_ISB_SY,
 196         ARMV8_OPC_DCCISW,
 197         ARMV8_OPC_DCCIVAC,
 198         ARMV8_OPC_ICIVAU,
 199         ARMV8_OPC_HLT,
 200         ARMV8_OPC_STRB_IP,
 201         ARMV8_OPC_STRH_IP,
 202         ARMV8_OPC_STRW_IP,
 203         ARMV8_OPC_LDRB_IP,
 204         ARMV8_OPC_LDRH_IP,
 205         ARMV8_OPC_LDRW_IP,
 206         ARMV8_OPC_NUM,
 207 };
 208
 209 extern uint32_t armv8_opcode(struct armv8_common *armv8, enum armv8_opcode);
 210 extern void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64);
 211
 212 #endif /* OPENOCD_TARGET_ARMV8_OPCODES_H */