1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * This program is free software; you can redistribute it and/or modify *
12 * it under the terms of the GNU General Public License as published by *
13 * the Free Software Foundation; either version 2 of the License, or *
14 * (at your option) any later version. *
16 * This program is distributed in the hope that it will be useful, *
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
19 * GNU General Public License for more details. *
21 * You should have received a copy of the GNU General Public License *
22 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
23 ***************************************************************************/
25 #ifndef OPENOCD_TARGET_ARMV7M_H
26 #define OPENOCD_TARGET_ARMV7M_H
28 #include "arm_adi_v5.h"
30 #include "armv7m_trace.h"
32 extern const int armv7m_psp_reg_map
[];
33 extern const int armv7m_msp_reg_map
[];
35 const char *armv7m_exception_string(int number
);
37 /* Cortex-M DCRSR.REGSEL selectors */
57 ARMV7M_REGSEL_PC
= 15,
59 ARMV7M_REGSEL_xPSR
= 16,
63 ARMV8M_REGSEL_MSP_NS
= 0x18,
67 ARMV8M_REGSEL_MSPLIM_S
,
68 ARMV8M_REGSEL_PSPLIM_S
,
69 ARMV8M_REGSEL_MSPLIM_NS
,
70 ARMV8M_REGSEL_PSPLIM_NS
,
72 ARMV7M_REGSEL_PMSK_BPRI_FLTMSK_CTRL
= 0x14,
73 ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_S
= 0x22,
74 ARMV8M_REGSEL_PMSK_BPRI_FLTMSK_CTRL_NS
= 0x23,
75 ARMV7M_REGSEL_FPSCR
= 0x21,
77 /* 32bit Floating-point registers */
78 ARMV7M_REGSEL_S0
= 0x40,
112 /* offsets into armv7m core register cache */
114 /* for convenience, the first set of indices match
115 * the Cortex-M DCRSR.REGSEL selectors
117 ARMV7M_R0
= ARMV7M_REGSEL_R0
,
118 ARMV7M_R1
= ARMV7M_REGSEL_R1
,
119 ARMV7M_R2
= ARMV7M_REGSEL_R2
,
120 ARMV7M_R3
= ARMV7M_REGSEL_R3
,
122 ARMV7M_R4
= ARMV7M_REGSEL_R4
,
123 ARMV7M_R5
= ARMV7M_REGSEL_R5
,
124 ARMV7M_R6
= ARMV7M_REGSEL_R6
,
125 ARMV7M_R7
= ARMV7M_REGSEL_R7
,
127 ARMV7M_R8
= ARMV7M_REGSEL_R8
,
128 ARMV7M_R9
= ARMV7M_REGSEL_R9
,
129 ARMV7M_R10
= ARMV7M_REGSEL_R10
,
130 ARMV7M_R11
= ARMV7M_REGSEL_R11
,
132 ARMV7M_R12
= ARMV7M_REGSEL_R12
,
133 ARMV7M_R13
= ARMV7M_REGSEL_R13
,
134 ARMV7M_R14
= ARMV7M_REGSEL_R14
,
135 ARMV7M_PC
= ARMV7M_REGSEL_PC
,
137 ARMV7M_xPSR
= ARMV7M_REGSEL_xPSR
,
138 ARMV7M_MSP
= ARMV7M_REGSEL_MSP
,
139 ARMV7M_PSP
= ARMV7M_REGSEL_PSP
,
141 /* following indices are arbitrary, do not match DCRSR.REGSEL selectors */
143 /* A block of container and contained registers follows:
144 * THE ORDER IS IMPORTANT to the end of the block ! */
145 /* working register for packing/unpacking special regs, hidden from gdb */
146 ARMV7M_PMSK_BPRI_FLTMSK_CTRL
,
148 /* WARNING: If you use armv7m_write_core_reg() on one of 4 following
149 * special registers, the new data go to ARMV7M_PMSK_BPRI_FLTMSK_CTRL
150 * cache only and are not flushed to CPU HW register.
151 * To trigger write to CPU HW register, add
152 * armv7m_write_core_reg(,,ARMV7M_PMSK_BPRI_FLTMSK_CTRL,);
158 /* The end of block of container and contained registers */
160 /* ARMv8-M specific registers */
170 /* A block of container and contained registers follows:
171 * THE ORDER IS IMPORTANT to the end of the block ! */
172 ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S
,
177 /* The end of block of container and contained registers */
179 /* A block of container and contained registers follows:
180 * THE ORDER IS IMPORTANT to the end of the block ! */
181 ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS
,
186 /* The end of block of container and contained registers */
188 /* 64bit Floating-point registers */
206 /* Floating-point status register */
209 /* for convenience add registers' block delimiters */
211 ARMV7M_CORE_FIRST_REG
= ARMV7M_R0
,
212 ARMV7M_CORE_LAST_REG
= ARMV7M_xPSR
,
213 ARMV7M_FPU_FIRST_REG
= ARMV7M_D0
,
214 ARMV7M_FPU_LAST_REG
= ARMV7M_FPSCR
,
215 ARMV8M_FIRST_REG
= ARMV8M_MSP_NS
,
216 ARMV8M_LAST_REG
= ARMV8M_CONTROL_NS
,
226 #define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1)
228 #define ARMV7M_COMMON_MAGIC 0x2A452A45
230 struct armv7m_common
{
234 int exception_number
;
236 /* AP this processor is connected to in the DAP */
237 struct adiv5_ap
*debug_ap
;
242 /* stlink is a high level adapter, does not support all functions */
245 struct armv7m_trace_config trace_config
;
247 /* Direct processor core register read and writes */
248 int (*load_core_reg_u32
)(struct target
*target
, uint32_t regsel
, uint32_t *value
);
249 int (*store_core_reg_u32
)(struct target
*target
, uint32_t regsel
, uint32_t value
);
251 int (*examine_debug_reason
)(struct target
*target
);
252 int (*post_debug_entry
)(struct target
*target
);
254 void (*pre_restore_context
)(struct target
*target
);
257 static inline struct armv7m_common
*
258 target_to_armv7m(struct target
*target
)
260 return container_of(target
->arch_info
, struct armv7m_common
, arm
);
263 static inline bool is_armv7m(const struct armv7m_common
*armv7m
)
265 return armv7m
->common_magic
== ARMV7M_COMMON_MAGIC
;
268 struct armv7m_algorithm
{
271 enum arm_mode core_mode
;
273 uint32_t context
[ARMV7M_LAST_REG
]; /* ARMV7M_NUM_REGS */
276 struct reg_cache
*armv7m_build_reg_cache(struct target
*target
);
277 void armv7m_free_reg_cache(struct target
*target
);
279 enum armv7m_mode
armv7m_number_to_mode(int number
);
280 int armv7m_mode_to_number(enum armv7m_mode mode
);
282 int armv7m_arch_state(struct target
*target
);
283 int armv7m_get_gdb_reg_list(struct target
*target
,
284 struct reg
**reg_list
[], int *reg_list_size
,
285 enum target_register_class reg_class
);
287 int armv7m_init_arch_info(struct target
*target
, struct armv7m_common
*armv7m
);
289 int armv7m_run_algorithm(struct target
*target
,
290 int num_mem_params
, struct mem_param
*mem_params
,
291 int num_reg_params
, struct reg_param
*reg_params
,
292 target_addr_t entry_point
, target_addr_t exit_point
,
293 int timeout_ms
, void *arch_info
);
295 int armv7m_start_algorithm(struct target
*target
,
296 int num_mem_params
, struct mem_param
*mem_params
,
297 int num_reg_params
, struct reg_param
*reg_params
,
298 target_addr_t entry_point
, target_addr_t exit_point
,
301 int armv7m_wait_algorithm(struct target
*target
,
302 int num_mem_params
, struct mem_param
*mem_params
,
303 int num_reg_params
, struct reg_param
*reg_params
,
304 target_addr_t exit_point
, int timeout_ms
,
307 int armv7m_invalidate_core_regs(struct target
*target
);
309 int armv7m_restore_context(struct target
*target
);
311 int armv7m_checksum_memory(struct target
*target
,
312 target_addr_t address
, uint32_t count
, uint32_t *checksum
);
313 int armv7m_blank_check_memory(struct target
*target
,
314 struct target_memory_check_block
*blocks
, int num_blocks
, uint8_t erased_value
);
316 int armv7m_maybe_skip_bkpt_inst(struct target
*target
, bool *inst_found
);
318 extern const struct command_registration armv7m_command_handlers
[];
320 #endif /* OPENOCD_TARGET_ARMV7M_H */
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