1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * Copyright (C) 2006 by Magnus Lundin *
8 * Copyright (C) 2008 by Spencer Oliver *
9 * spen@spen-soft.co.uk *
11 * Copyright (C) 2007,2008 Øyvind Harboe *
12 * oyvind.harboe@zylin.com *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program; if not, write to the *
26 * Free Software Foundation, Inc., *
27 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
29 * ARMv7-M Architecture, Application Level Reference Manual *
30 * ARM DDI 0405C (September 2008) *
32 ***************************************************************************/
37 #include "breakpoints.h"
39 #include "algorithm.h"
44 #define _DEBUG_INSTRUCTION_EXECUTION_
47 /** Maps from enum armv7m_mode (except ARMV7M_MODE_ANY) to name. */
48 char *armv7m_mode_strings
[] =
50 "Thread", "Thread (User)", "Handler",
53 static char *armv7m_exception_strings
[] =
55 "", "Reset", "NMI", "HardFault",
56 "MemManage", "BusFault", "UsageFault", "RESERVED",
57 "RESERVED", "RESERVED", "RESERVED", "SVCall",
58 "DebugMonitor", "RESERVED", "PendSV", "SysTick"
61 #ifdef ARMV7_GDB_HACKS
62 uint8_t armv7m_gdb_dummy_cpsr_value
[] = {0, 0, 0, 0};
64 struct reg armv7m_gdb_dummy_cpsr_reg
=
66 .name
= "GDB dummy cpsr register",
67 .value
= armv7m_gdb_dummy_cpsr_value
,
76 * These registers are not memory-mapped. The ARMv7-M profile includes
77 * memory mapped registers too, such as for the NVIC (interrupt controller)
78 * and SysTick (timer) modules; those can mostly be treated as peripherals.
80 * The ARMv6-M profile is almost identical in this respect, except that it
81 * doesn't include basepri or faultmask registers.
88 { ARMV7M_R0
, "r0", 32 },
89 { ARMV7M_R1
, "r1", 32 },
90 { ARMV7M_R2
, "r2", 32 },
91 { ARMV7M_R3
, "r3", 32 },
93 { ARMV7M_R4
, "r4", 32 },
94 { ARMV7M_R5
, "r5", 32 },
95 { ARMV7M_R6
, "r6", 32 },
96 { ARMV7M_R7
, "r7", 32 },
98 { ARMV7M_R8
, "r8", 32 },
99 { ARMV7M_R9
, "r9", 32 },
100 { ARMV7M_R10
, "r10", 32 },
101 { ARMV7M_R11
, "r11", 32 },
103 { ARMV7M_R12
, "r12", 32 },
104 { ARMV7M_R13
, "sp", 32 },
105 { ARMV7M_R14
, "lr", 32 },
106 { ARMV7M_PC
, "pc", 32 },
108 { ARMV7M_xPSR
, "xPSR", 32 },
109 { ARMV7M_MSP
, "msp", 32 },
110 { ARMV7M_PSP
, "psp", 32 },
112 { ARMV7M_PRIMASK
, "primask", 1 },
113 { ARMV7M_BASEPRI
, "basepri", 8 },
114 { ARMV7M_FAULTMASK
, "faultmask", 1 },
115 { ARMV7M_CONTROL
, "control", 2 },
118 #define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
121 * Restores target context using the cache of core registers set up
122 * by armv7m_build_reg_cache(), calling optional core-specific hooks.
124 int armv7m_restore_context(struct target
*target
)
127 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
131 if (armv7m
->pre_restore_context
)
132 armv7m
->pre_restore_context(target
);
134 for (i
= ARMV7M_NUM_REGS
- 1; i
>= 0; i
--)
136 if (armv7m
->core_cache
->reg_list
[i
].dirty
)
138 armv7m
->write_core_reg(target
, i
);
142 if (armv7m
->post_restore_context
)
143 armv7m
->post_restore_context(target
);
148 /* Core state functions */
151 * Maps ISR number (from xPSR) to name.
152 * Note that while names and meanings for the first sixteen are standardized
153 * (with zero not a true exception), external interrupts are only numbered.
154 * They are assigned by vendors, which generally assign different numbers to
155 * peripherals (such as UART0 or a USB peripheral controller).
157 char *armv7m_exception_string(int number
)
159 static char enamebuf
[32];
161 if ((number
< 0) | (number
> 511))
162 return "Invalid exception";
164 return armv7m_exception_strings
[number
];
165 sprintf(enamebuf
, "External Interrupt(%i)", number
- 16);
169 static int armv7m_get_core_reg(struct reg
*reg
)
172 struct armv7m_core_reg
*armv7m_reg
= reg
->arch_info
;
173 struct target
*target
= armv7m_reg
->target
;
174 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
176 if (target
->state
!= TARGET_HALTED
)
178 return ERROR_TARGET_NOT_HALTED
;
181 retval
= armv7m
->read_core_reg(target
, armv7m_reg
->num
);
186 static int armv7m_set_core_reg(struct reg
*reg
, uint8_t *buf
)
188 struct armv7m_core_reg
*armv7m_reg
= reg
->arch_info
;
189 struct target
*target
= armv7m_reg
->target
;
190 uint32_t value
= buf_get_u32(buf
, 0, 32);
192 if (target
->state
!= TARGET_HALTED
)
194 return ERROR_TARGET_NOT_HALTED
;
197 buf_set_u32(reg
->value
, 0, 32, value
);
204 static int armv7m_read_core_reg(struct target
*target
, unsigned num
)
208 struct armv7m_core_reg
* armv7m_core_reg
;
209 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
211 if (num
>= ARMV7M_NUM_REGS
)
212 return ERROR_INVALID_ARGUMENTS
;
214 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
215 retval
= armv7m
->load_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, ®_value
);
216 buf_set_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32, reg_value
);
217 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
218 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
223 static int armv7m_write_core_reg(struct target
*target
, unsigned num
)
227 struct armv7m_core_reg
*armv7m_core_reg
;
228 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
230 if (num
>= ARMV7M_NUM_REGS
)
231 return ERROR_INVALID_ARGUMENTS
;
233 reg_value
= buf_get_u32(armv7m
->core_cache
->reg_list
[num
].value
, 0, 32);
234 armv7m_core_reg
= armv7m
->core_cache
->reg_list
[num
].arch_info
;
235 retval
= armv7m
->store_core_reg_u32(target
, armv7m_core_reg
->type
, armv7m_core_reg
->num
, reg_value
);
236 if (retval
!= ERROR_OK
)
238 LOG_ERROR("JTAG failure");
239 armv7m
->core_cache
->reg_list
[num
].dirty
= armv7m
->core_cache
->reg_list
[num
].valid
;
240 return ERROR_JTAG_DEVICE_ERROR
;
242 LOG_DEBUG("write core reg %i value 0x%" PRIx32
"", num
, reg_value
);
243 armv7m
->core_cache
->reg_list
[num
].valid
= 1;
244 armv7m
->core_cache
->reg_list
[num
].dirty
= 0;
250 * Returns generic ARM userspace registers to GDB.
251 * GDB doesn't quite understand that most ARMs don't have floating point
252 * hardware, so this also fakes a set of long-obsolete FPA registers that
253 * are not used in EABI based software stacks.
255 int armv7m_get_gdb_reg_list(struct target
*target
, struct reg
**reg_list
[], int *reg_list_size
)
257 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
261 *reg_list
= malloc(sizeof(struct reg
*) * (*reg_list_size
));
264 * GDB register packet format for ARM:
265 * - the first 16 registers are r0..r15
266 * - (obsolete) 8 FPA registers
267 * - (obsolete) FPA status
270 for (i
= 0; i
< 16; i
++)
272 (*reg_list
)[i
] = &armv7m
->core_cache
->reg_list
[i
];
275 for (i
= 16; i
< 24; i
++)
276 (*reg_list
)[i
] = &arm_gdb_dummy_fp_reg
;
277 (*reg_list
)[24] = &arm_gdb_dummy_fps_reg
;
279 #ifdef ARMV7_GDB_HACKS
280 /* use dummy cpsr reg otherwise gdb may try and set the thumb bit */
281 (*reg_list
)[25] = &armv7m_gdb_dummy_cpsr_reg
;
283 /* ARMV7M is always in thumb mode, try to make GDB understand this
284 * if it does not support this arch */
285 *((char*)armv7m
->arm
.pc
->value
) |= 1;
287 (*reg_list
)[25] = &armv7m
->core_cache
->reg_list
[ARMV7M_xPSR
];
293 /* run to exit point. return error if exit point was not reached. */
294 static int armv7m_run_and_wait(struct target
*target
, uint32_t entry_point
, int timeout_ms
, uint32_t exit_point
, struct armv7m_common
*armv7m
)
298 /* This code relies on the target specific resume() and poll()->debug_entry()
299 * sequence to write register values to the processor and the read them back */
300 if ((retval
= target_resume(target
, 0, entry_point
, 1, 1)) != ERROR_OK
)
305 retval
= target_wait_state(target
, TARGET_HALTED
, timeout_ms
);
306 /* If the target fails to halt due to the breakpoint, force a halt */
307 if (retval
!= ERROR_OK
|| target
->state
!= TARGET_HALTED
)
309 if ((retval
= target_halt(target
)) != ERROR_OK
)
311 if ((retval
= target_wait_state(target
, TARGET_HALTED
, 500)) != ERROR_OK
)
315 return ERROR_TARGET_TIMEOUT
;
318 armv7m
->load_core_reg_u32(target
, ARMV7M_REGISTER_CORE_GP
, 15, &pc
);
319 if (pc
!= exit_point
)
321 LOG_DEBUG("failed algoritm halted at 0x%" PRIx32
" ", pc
);
322 return ERROR_TARGET_TIMEOUT
;
328 /** Runs a Thumb algorithm in the target. */
329 int armv7m_run_algorithm(struct target
*target
,
330 int num_mem_params
, struct mem_param
*mem_params
,
331 int num_reg_params
, struct reg_param
*reg_params
,
332 uint32_t entry_point
, uint32_t exit_point
,
333 int timeout_ms
, void *arch_info
)
335 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
336 struct armv7m_algorithm
*armv7m_algorithm_info
= arch_info
;
337 enum armv7m_mode core_mode
= armv7m
->core_mode
;
338 int retval
= ERROR_OK
;
339 uint32_t context
[ARMV7M_NUM_REGS
];
341 /* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
342 * at the exit point */
344 if (armv7m_algorithm_info
->common_magic
!= ARMV7M_COMMON_MAGIC
)
346 LOG_ERROR("current target isn't an ARMV7M target");
347 return ERROR_TARGET_INVALID
;
350 if (target
->state
!= TARGET_HALTED
)
352 LOG_WARNING("target not halted");
353 return ERROR_TARGET_NOT_HALTED
;
356 /* refresh core register cache */
357 /* Not needed if core register cache is always consistent with target process state */
358 for (unsigned i
= 0; i
< ARMV7M_NUM_REGS
; i
++)
360 if (!armv7m
->core_cache
->reg_list
[i
].valid
)
361 armv7m
->read_core_reg(target
, i
);
362 context
[i
] = buf_get_u32(armv7m
->core_cache
->reg_list
[i
].value
, 0, 32);
365 for (int i
= 0; i
< num_mem_params
; i
++)
367 if ((retval
= target_write_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
)) != ERROR_OK
)
371 for (int i
= 0; i
< num_reg_params
; i
++)
373 struct reg
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
374 // uint32_t regvalue;
378 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
379 return ERROR_INVALID_ARGUMENTS
;
382 if (reg
->size
!= reg_params
[i
].size
)
384 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
385 return ERROR_INVALID_ARGUMENTS
;
388 // regvalue = buf_get_u32(reg_params[i].value, 0, 32);
389 armv7m_set_core_reg(reg
, reg_params
[i
].value
);
392 if (armv7m_algorithm_info
->core_mode
!= ARMV7M_MODE_ANY
)
394 LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info
->core_mode
);
395 buf_set_u32(armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].value
,
396 0, 1, armv7m_algorithm_info
->core_mode
);
397 armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].dirty
= 1;
398 armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].valid
= 1;
401 retval
= armv7m_run_and_wait(target
, entry_point
, timeout_ms
, exit_point
, armv7m
);
403 if (retval
!= ERROR_OK
)
408 /* Read memory values to mem_params[] */
409 for (int i
= 0; i
< num_mem_params
; i
++)
411 if (mem_params
[i
].direction
!= PARAM_OUT
)
412 if ((retval
= target_read_buffer(target
, mem_params
[i
].address
, mem_params
[i
].size
, mem_params
[i
].value
)) != ERROR_OK
)
418 /* Copy core register values to reg_params[] */
419 for (int i
= 0; i
< num_reg_params
; i
++)
421 if (reg_params
[i
].direction
!= PARAM_OUT
)
423 struct reg
*reg
= register_get_by_name(armv7m
->core_cache
, reg_params
[i
].reg_name
, 0);
427 LOG_ERROR("BUG: register '%s' not found", reg_params
[i
].reg_name
);
428 return ERROR_INVALID_ARGUMENTS
;
431 if (reg
->size
!= reg_params
[i
].size
)
433 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size", reg_params
[i
].reg_name
);
434 return ERROR_INVALID_ARGUMENTS
;
437 buf_set_u32(reg_params
[i
].value
, 0, 32, buf_get_u32(reg
->value
, 0, 32));
441 for (int i
= ARMV7M_NUM_REGS
- 1; i
>= 0; i
--)
444 regvalue
= buf_get_u32(armv7m
->core_cache
->reg_list
[i
].value
, 0, 32);
445 if (regvalue
!= context
[i
])
447 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32
,
448 armv7m
->core_cache
->reg_list
[i
].name
, context
[i
]);
449 buf_set_u32(armv7m
->core_cache
->reg_list
[i
].value
,
451 armv7m
->core_cache
->reg_list
[i
].valid
= 1;
452 armv7m
->core_cache
->reg_list
[i
].dirty
= 1;
456 armv7m
->core_mode
= core_mode
;
461 /** Logs summary of ARMv7-M state for a halted target. */
462 int armv7m_arch_state(struct target
*target
)
464 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
465 struct arm
*arm
= &armv7m
->arm
;
468 ctrl
= buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_CONTROL
].value
, 0, 32);
469 sp
= buf_get_u32(armv7m
->core_cache
->reg_list
[ARMV7M_R13
].value
, 0, 32);
471 LOG_USER("target halted due to %s, current mode: %s %s\n"
472 "xPSR: %#8.8" PRIx32
" pc: %#8.8" PRIx32
" %csp: %#8.8" PRIx32
,
473 debug_reason_name(target
),
474 armv7m_mode_strings
[armv7m
->core_mode
],
475 armv7m_exception_string(armv7m
->exception_number
),
476 buf_get_u32(arm
->cpsr
->value
, 0, 32),
477 buf_get_u32(arm
->pc
->value
, 0, 32),
478 (ctrl
& 0x02) ? 'p' : 'm',
483 static const struct reg_arch_type armv7m_reg_type
= {
484 .get
= armv7m_get_core_reg
,
485 .set
= armv7m_set_core_reg
,
488 /** Builds cache of architecturally defined registers. */
489 struct reg_cache
*armv7m_build_reg_cache(struct target
*target
)
491 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
492 struct arm
*arm
= &armv7m
->arm
;
493 int num_regs
= ARMV7M_NUM_REGS
;
494 struct reg_cache
**cache_p
= register_get_last_cache_p(&target
->reg_cache
);
495 struct reg_cache
*cache
= malloc(sizeof(struct reg_cache
));
496 struct reg
*reg_list
= calloc(num_regs
, sizeof(struct reg
));
497 struct armv7m_core_reg
*arch_info
= calloc(num_regs
, sizeof(struct armv7m_core_reg
));
500 #ifdef ARMV7_GDB_HACKS
501 register_init_dummy(&armv7m_gdb_dummy_cpsr_reg
);
504 /* Build the process context cache */
505 cache
->name
= "arm v7m registers";
507 cache
->reg_list
= reg_list
;
508 cache
->num_regs
= num_regs
;
510 armv7m
->core_cache
= cache
;
512 for (i
= 0; i
< num_regs
; i
++)
514 arch_info
[i
].num
= armv7m_regs
[i
].id
;
515 arch_info
[i
].target
= target
;
516 arch_info
[i
].armv7m_common
= armv7m
;
517 reg_list
[i
].name
= armv7m_regs
[i
].name
;
518 reg_list
[i
].size
= armv7m_regs
[i
].bits
;
519 reg_list
[i
].value
= calloc(1, 4);
520 reg_list
[i
].dirty
= 0;
521 reg_list
[i
].valid
= 0;
522 reg_list
[i
].type
= &armv7m_reg_type
;
523 reg_list
[i
].arch_info
= &arch_info
[i
];
526 arm
->cpsr
= reg_list
+ ARMV7M_xPSR
;
527 arm
->pc
= reg_list
+ ARMV7M_PC
;
528 arm
->core_cache
= cache
;
532 /** Sets up target as a generic ARMv7-M core */
533 int armv7m_init_arch_info(struct target
*target
, struct armv7m_common
*armv7m
)
535 struct arm
*arm
= &armv7m
->arm
;
537 armv7m
->common_magic
= ARMV7M_COMMON_MAGIC
;
539 arm
->core_type
= ARM_MODE_THREAD
;
540 arm
->arch_info
= armv7m
;
542 /* FIXME remove v7m-specific r/w core_reg functions;
543 * use the generic ARM core support..
545 armv7m
->read_core_reg
= armv7m_read_core_reg
;
546 armv7m
->write_core_reg
= armv7m_write_core_reg
;
548 return arm_init_arch_info(target
, arm
);
551 /** Generates a CRC32 checksum of a memory region. */
552 int armv7m_checksum_memory(struct target
*target
,
553 uint32_t address
, uint32_t count
, uint32_t* checksum
)
555 struct working_area
*crc_algorithm
;
556 struct armv7m_algorithm armv7m_info
;
557 struct reg_param reg_params
[2];
560 static const uint16_t cortex_m3_crc_code
[] = {
561 0x4602, /* mov r2, r0 */
562 0xF04F, 0x30FF, /* mov r0, #0xffffffff */
563 0x460B, /* mov r3, r1 */
564 0xF04F, 0x0400, /* mov r4, #0 */
565 0xE013, /* b ncomp */
567 0x5D11, /* ldrb r1, [r2, r4] */
568 0xF8DF, 0x7028, /* ldr r7, CRC32XOR */
569 0xEA80, 0x6001, /* eor r0, r0, r1, asl #24 */
571 0xF04F, 0x0500, /* mov r5, #0 */
573 0x2800, /* cmp r0, #0 */
574 0xEA4F, 0x0640, /* mov r6, r0, asl #1 */
575 0xF105, 0x0501, /* add r5, r5, #1 */
576 0x4630, /* mov r0, r6 */
578 0xEA86, 0x0007, /* eor r0, r6, r7 */
579 0x2D08, /* cmp r5, #8 */
580 0xD1F4, /* bne loop */
582 0xF104, 0x0401, /* add r4, r4, #1 */
584 0x429C, /* cmp r4, r3 */
585 0xD1E9, /* bne nbyte */
586 0xBE00, /* bkpt #0 */
587 0x1DB7, 0x04C1 /* CRC32XOR: .word 0x04C11DB7 */
592 if (target_alloc_working_area(target
, sizeof(cortex_m3_crc_code
), &crc_algorithm
) != ERROR_OK
)
594 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
597 /* convert flash writing code into a buffer in target endianness */
598 for (i
= 0; i
< ARRAY_SIZE(cortex_m3_crc_code
); i
++)
599 if ((retval
= target_write_u16(target
, crc_algorithm
->address
+ i
*sizeof(uint16_t), cortex_m3_crc_code
[i
])) != ERROR_OK
)
604 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
605 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
607 init_reg_param(®_params
[0], "r0", 32, PARAM_IN_OUT
);
608 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
610 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
611 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
613 if ((retval
= target_run_algorithm(target
, 0, NULL
, 2, reg_params
,
614 crc_algorithm
->address
, crc_algorithm
->address
+ (sizeof(cortex_m3_crc_code
)-6), 20000, &armv7m_info
)) != ERROR_OK
)
616 LOG_ERROR("error executing cortex_m3 crc algorithm");
617 destroy_reg_param(®_params
[0]);
618 destroy_reg_param(®_params
[1]);
619 target_free_working_area(target
, crc_algorithm
);
623 *checksum
= buf_get_u32(reg_params
[0].value
, 0, 32);
625 destroy_reg_param(®_params
[0]);
626 destroy_reg_param(®_params
[1]);
628 target_free_working_area(target
, crc_algorithm
);
633 /** Checks whether a memory region is zeroed. */
634 int armv7m_blank_check_memory(struct target
*target
,
635 uint32_t address
, uint32_t count
, uint32_t* blank
)
637 struct working_area
*erase_check_algorithm
;
638 struct reg_param reg_params
[3];
639 struct armv7m_algorithm armv7m_info
;
643 static const uint16_t erase_check_code
[] =
646 0xF810, 0x3B01, /* ldrb r3, [r0], #1 */
647 0xEA02, 0x0203, /* and r2, r2, r3 */
648 0x3901, /* subs r1, r1, #1 */
649 0xD1F9, /* bne loop */
650 0xBE00, /* bkpt #0 */
653 /* make sure we have a working area */
654 if (target_alloc_working_area(target
, sizeof(erase_check_code
), &erase_check_algorithm
) != ERROR_OK
)
656 return ERROR_TARGET_RESOURCE_NOT_AVAILABLE
;
659 /* convert flash writing code into a buffer in target endianness */
660 for (i
= 0; i
< ARRAY_SIZE(erase_check_code
); i
++)
661 target_write_u16(target
, erase_check_algorithm
->address
+ i
*sizeof(uint16_t), erase_check_code
[i
]);
663 armv7m_info
.common_magic
= ARMV7M_COMMON_MAGIC
;
664 armv7m_info
.core_mode
= ARMV7M_MODE_ANY
;
666 init_reg_param(®_params
[0], "r0", 32, PARAM_OUT
);
667 buf_set_u32(reg_params
[0].value
, 0, 32, address
);
669 init_reg_param(®_params
[1], "r1", 32, PARAM_OUT
);
670 buf_set_u32(reg_params
[1].value
, 0, 32, count
);
672 init_reg_param(®_params
[2], "r2", 32, PARAM_IN_OUT
);
673 buf_set_u32(reg_params
[2].value
, 0, 32, 0xff);
675 if ((retval
= target_run_algorithm(target
, 0, NULL
, 3, reg_params
,
676 erase_check_algorithm
->address
, erase_check_algorithm
->address
+ (sizeof(erase_check_code
)-2), 10000, &armv7m_info
)) != ERROR_OK
)
678 destroy_reg_param(®_params
[0]);
679 destroy_reg_param(®_params
[1]);
680 destroy_reg_param(®_params
[2]);
681 target_free_working_area(target
, erase_check_algorithm
);
685 *blank
= buf_get_u32(reg_params
[2].value
, 0, 32);
687 destroy_reg_param(®_params
[0]);
688 destroy_reg_param(®_params
[1]);
689 destroy_reg_param(®_params
[2]);
691 target_free_working_area(target
, erase_check_algorithm
);
696 int armv7m_maybe_skip_bkpt_inst(struct target
*target
, bool *inst_found
)
698 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
699 struct reg
*r
= armv7m
->arm
.pc
;
703 /* if we halted last time due to a bkpt instruction
704 * then we have to manually step over it, otherwise
705 * the core will break again */
707 if (target
->debug_reason
== DBG_REASON_BREAKPOINT
)
710 uint32_t pc
= buf_get_u32(r
->value
, 0, 32);
713 if (target_read_u16(target
, pc
, &op
) == ERROR_OK
)
715 if ((op
& 0xFF00) == 0xBE00)
717 pc
= buf_get_u32(r
->value
, 0, 32) + 2;
718 buf_set_u32(r
->value
, 0, 32, pc
);
722 LOG_DEBUG("Skipping over BKPT instruction");
728 *inst_found
= result
;
734 /*--------------------------------------------------------------------------*/
737 * Only stuff below this line should need to verify that its target
738 * is an ARMv7-M node.
743 * Return the debug ap baseaddress in hexadecimal;
744 * no extra output to simplify script processing
746 COMMAND_HANDLER(handle_dap_baseaddr_command
)
748 struct target
*target
= get_current_target(CMD_CTX
);
749 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
750 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
752 if (!is_armv7m(armv7m
)) {
753 command_print(CMD_CTX
, "current target isn't an ARM7-M");
754 return ERROR_TARGET_INVALID
;
757 return CALL_COMMAND_HANDLER(dap_baseaddr_command
, swjdp
);
761 * Return the debug ap id in hexadecimal;
762 * no extra output to simplify script processing
764 COMMAND_HANDLER(handle_dap_apid_command
)
766 struct target
*target
= get_current_target(CMD_CTX
);
767 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
768 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
770 if (!is_armv7m(armv7m
)) {
771 command_print(CMD_CTX
, "current target isn't an ARM7-M");
772 return ERROR_TARGET_INVALID
;
775 return CALL_COMMAND_HANDLER(dap_apid_command
, swjdp
);
778 COMMAND_HANDLER(handle_dap_apsel_command
)
780 struct target
*target
= get_current_target(CMD_CTX
);
781 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
782 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
784 if (!is_armv7m(armv7m
)) {
785 command_print(CMD_CTX
, "current target isn't an ARM7-M");
786 return ERROR_TARGET_INVALID
;
789 return CALL_COMMAND_HANDLER(dap_apsel_command
, swjdp
);
792 COMMAND_HANDLER(handle_dap_memaccess_command
)
794 struct target
*target
= get_current_target(CMD_CTX
);
795 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
796 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
798 if (!is_armv7m(armv7m
)) {
799 command_print(CMD_CTX
, "current target isn't an ARM7-M");
800 return ERROR_TARGET_INVALID
;
803 return CALL_COMMAND_HANDLER(dap_memaccess_command
, swjdp
);
807 COMMAND_HANDLER(handle_dap_info_command
)
809 struct target
*target
= get_current_target(CMD_CTX
);
810 struct armv7m_common
*armv7m
= target_to_armv7m(target
);
811 struct swjdp_common
*swjdp
= &armv7m
->swjdp_info
;
814 if (!is_armv7m(armv7m
)) {
815 command_print(CMD_CTX
, "current target isn't an ARM7-M");
816 return ERROR_TARGET_INVALID
;
821 apsel
= swjdp
->apsel
;
824 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], apsel
);
827 return ERROR_COMMAND_SYNTAX_ERROR
;
830 return dap_info_command(CMD_CTX
, swjdp
, apsel
);
833 /* FIXME this table should be part of generic DAP support, and
834 * be shared by the ARMv7-A/R and ARMv7-M support ...
836 static const struct command_registration armv7m_exec_command_handlers
[] = {
839 .handler
= handle_dap_info_command
,
840 .mode
= COMMAND_EXEC
,
841 .help
= "display ROM table for MEM-AP "
842 "(default currently selected AP)",
847 .handler
= handle_dap_apsel_command
,
848 .mode
= COMMAND_EXEC
,
849 .help
= "Set the currently selected AP (default 0) "
850 "and display the result",
855 .handler
= handle_dap_apid_command
,
856 .mode
= COMMAND_EXEC
,
857 .help
= "return ID register from AP "
858 "(default currently selected AP)",
863 .handler
= handle_dap_baseaddr_command
,
864 .mode
= COMMAND_EXEC
,
865 .help
= "return debug base address from MEM-AP "
866 "(default currently selected AP)",
871 .handler
= handle_dap_memaccess_command
,
872 .mode
= COMMAND_EXEC
,
873 .help
= "set/get number of extra tck for MEM-AP memory "
874 "bus access [0-255]",
877 COMMAND_REGISTRATION_DONE
879 const struct command_registration armv7m_command_handlers
[] = {
882 .mode
= COMMAND_EXEC
,
883 .help
= "Cortex DAP command group",
884 .chain
= armv7m_exec_command_handlers
,
886 COMMAND_REGISTRATION_DONE
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