1 /***************************************************************************
2 * Copyright (C) 2015 by Oleksij Rempel *
3 * linux@rempel-privat.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
14 ***************************************************************************/
20 #include "jtag/interface.h"
23 #include "armv7a_cache.h"
24 #include <helper/time_support.h>
26 #include "target_type.h"
28 static int arm7a_l2x_sanity_check(struct target
*target
)
30 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
31 struct armv7a_l2x_cache
*l2x_cache
= (struct armv7a_l2x_cache
*)
32 (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
);
34 if (target
->state
!= TARGET_HALTED
) {
35 LOG_ERROR("%s: target not halted", __func__
);
36 return ERROR_TARGET_NOT_HALTED
;
39 if (!l2x_cache
|| !l2x_cache
->base
) {
40 LOG_DEBUG("l2x is not configured!");
47 * clean and invalidate complete l2x cache
49 static int arm7a_l2x_flush_all_data(struct target
*target
)
51 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
52 struct armv7a_l2x_cache
*l2x_cache
= (struct armv7a_l2x_cache
*)
53 (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
);
57 retval
= arm7a_l2x_sanity_check(target
);
61 l2_way_val
= (1 << l2x_cache
->way
) - 1;
63 return target_write_phys_memory(target
,
64 l2x_cache
->base
+ L2X0_CLEAN_INV_WAY
,
65 4, 1, (uint8_t *)&l2_way_val
);
68 int armv7a_l2x_cache_flush_virt(struct target
*target
, uint32_t virt
,
71 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
72 struct armv7a_l2x_cache
*l2x_cache
= (struct armv7a_l2x_cache
*)
73 (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
);
74 /* FIXME: different controllers have different linelen? */
75 uint32_t i
, linelen
= 32;
78 retval
= arm7a_l2x_sanity_check(target
);
82 for (i
= 0; i
< size
; i
+= linelen
) {
83 uint32_t pa
, offs
= virt
+ i
;
85 /* FIXME: use less verbose virt2phys? */
86 retval
= target
->type
->virt2phys(target
, offs
, &pa
);
87 if (retval
!= ERROR_OK
)
90 retval
= target_write_phys_memory(target
,
91 l2x_cache
->base
+ L2X0_CLEAN_INV_LINE_PA
,
92 4, 1, (uint8_t *)&pa
);
93 if (retval
!= ERROR_OK
)
99 LOG_ERROR("d-cache invalidate failed");
104 static int armv7a_l2x_cache_inval_virt(struct target
*target
, uint32_t virt
,
107 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
108 struct armv7a_l2x_cache
*l2x_cache
= (struct armv7a_l2x_cache
*)
109 (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
);
110 /* FIXME: different controllers have different linelen */
111 uint32_t i
, linelen
= 32;
114 retval
= arm7a_l2x_sanity_check(target
);
118 for (i
= 0; i
< size
; i
+= linelen
) {
119 uint32_t pa
, offs
= virt
+ i
;
121 /* FIXME: use less verbose virt2phys? */
122 retval
= target
->type
->virt2phys(target
, offs
, &pa
);
123 if (retval
!= ERROR_OK
)
126 retval
= target_write_phys_memory(target
,
127 l2x_cache
->base
+ L2X0_INV_LINE_PA
,
128 4, 1, (uint8_t *)&pa
);
129 if (retval
!= ERROR_OK
)
135 LOG_ERROR("d-cache invalidate failed");
140 static int armv7a_l2x_cache_clean_virt(struct target
*target
, uint32_t virt
,
143 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
144 struct armv7a_l2x_cache
*l2x_cache
= (struct armv7a_l2x_cache
*)
145 (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
);
146 /* FIXME: different controllers have different linelen */
147 uint32_t i
, linelen
= 32;
150 retval
= arm7a_l2x_sanity_check(target
);
154 for (i
= 0; i
< size
; i
+= linelen
) {
155 uint32_t pa
, offs
= virt
+ i
;
157 /* FIXME: use less verbose virt2phys? */
158 retval
= target
->type
->virt2phys(target
, offs
, &pa
);
159 if (retval
!= ERROR_OK
)
162 retval
= target_write_phys_memory(target
,
163 l2x_cache
->base
+ L2X0_CLEAN_LINE_PA
,
164 4, 1, (uint8_t *)&pa
);
165 if (retval
!= ERROR_OK
)
171 LOG_ERROR("d-cache invalidate failed");
176 static int arm7a_handle_l2x_cache_info_command(struct command_context
*cmd_ctx
,
177 struct armv7a_cache_common
*armv7a_cache
)
179 struct armv7a_l2x_cache
*l2x_cache
= (struct armv7a_l2x_cache
*)
180 (armv7a_cache
->outer_cache
);
182 if (armv7a_cache
->ctype
== -1) {
183 command_print(cmd_ctx
, "cache not yet identified");
187 command_print(cmd_ctx
,
188 "L2 unified cache Base Address 0x%" PRIx32
", %" PRId32
" ways",
189 l2x_cache
->base
, l2x_cache
->way
);
194 static int armv7a_l2x_cache_init(struct target
*target
, uint32_t base
, uint32_t way
)
196 struct armv7a_l2x_cache
*l2x_cache
;
197 struct target_list
*head
= target
->head
;
200 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
201 if (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
) {
202 LOG_ERROR("L2 cache was already initialised\n");
206 l2x_cache
= calloc(1, sizeof(struct armv7a_l2x_cache
));
207 l2x_cache
->base
= base
;
208 l2x_cache
->way
= way
;
209 armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
= l2x_cache
;
211 /* initialize all targets in this cluster (smp target)
212 * l2 cache must be configured after smp declaration */
213 while (head
!= (struct target_list
*)NULL
) {
215 if (curr
!= target
) {
216 armv7a
= target_to_armv7a(curr
);
217 if (armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
) {
218 LOG_ERROR("smp target : cache l2 already initialized\n");
221 armv7a
->armv7a_mmu
.armv7a_cache
.outer_cache
= l2x_cache
;
228 COMMAND_HANDLER(arm7a_l2x_cache_info_command
)
230 struct target
*target
= get_current_target(CMD_CTX
);
231 struct armv7a_common
*armv7a
= target_to_armv7a(target
);
234 retval
= arm7a_l2x_sanity_check(target
);
238 return arm7a_handle_l2x_cache_info_command(CMD_CTX
,
239 &armv7a
->armv7a_mmu
.armv7a_cache
);
242 COMMAND_HANDLER(arm7a_l2x_cache_flush_all_command
)
244 struct target
*target
= get_current_target(CMD_CTX
);
246 return arm7a_l2x_flush_all_data(target
);
249 COMMAND_HANDLER(arm7a_l2x_cache_flush_virt_cmd
)
251 struct target
*target
= get_current_target(CMD_CTX
);
254 if (CMD_ARGC
== 0 || CMD_ARGC
> 2)
255 return ERROR_COMMAND_SYNTAX_ERROR
;
258 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], size
);
262 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], virt
);
264 return armv7a_l2x_cache_flush_virt(target
, virt
, size
);
267 COMMAND_HANDLER(arm7a_l2x_cache_inval_virt_cmd
)
269 struct target
*target
= get_current_target(CMD_CTX
);
272 if (CMD_ARGC
== 0 || CMD_ARGC
> 2)
273 return ERROR_COMMAND_SYNTAX_ERROR
;
276 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], size
);
280 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], virt
);
282 return armv7a_l2x_cache_inval_virt(target
, virt
, size
);
285 COMMAND_HANDLER(arm7a_l2x_cache_clean_virt_cmd
)
287 struct target
*target
= get_current_target(CMD_CTX
);
290 if (CMD_ARGC
== 0 || CMD_ARGC
> 2)
291 return ERROR_COMMAND_SYNTAX_ERROR
;
294 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], size
);
298 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], virt
);
300 return armv7a_l2x_cache_clean_virt(target
, virt
, size
);
303 /* FIXME: should we configure way size? or controller type? */
304 COMMAND_HANDLER(armv7a_l2x_cache_conf_cmd
)
306 struct target
*target
= get_current_target(CMD_CTX
);
310 return ERROR_COMMAND_SYNTAX_ERROR
;
312 /* command_print(CMD_CTX, "%s %s", CMD_ARGV[0], CMD_ARGV[1]); */
313 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[0], base
);
314 COMMAND_PARSE_NUMBER(u32
, CMD_ARGV
[1], way
);
316 /* AP address is in bits 31:24 of DP_SELECT */
317 return armv7a_l2x_cache_init(target
, base
, way
);
320 static const struct command_registration arm7a_l2x_cache_commands
[] = {
323 .handler
= armv7a_l2x_cache_conf_cmd
,
325 .help
= "configure l2x cache ",
326 .usage
= "<base_addr> <number_of_way>",
330 .handler
= arm7a_l2x_cache_info_command
,
332 .help
= "print cache realted information",
337 .handler
= arm7a_l2x_cache_flush_all_command
,
339 .help
= "flush complete l2x cache",
344 .handler
= arm7a_l2x_cache_flush_virt_cmd
,
346 .help
= "flush (clean and invalidate) l2x cache by virtual address offset and range size",
347 .usage
= "<virt_addr> [size]",
351 .handler
= arm7a_l2x_cache_inval_virt_cmd
,
353 .help
= "invalidate l2x cache by virtual address offset and range size",
354 .usage
= "<virt_addr> [size]",
358 .handler
= arm7a_l2x_cache_clean_virt_cmd
,
360 .help
= "clean l2x cache by virtual address address offset and range size",
361 .usage
= "<virt_addr> [size]",
363 COMMAND_REGISTRATION_DONE
366 const struct command_registration arm7a_l2x_cache_command_handler
[] = {
370 .help
= "l2x cache command group",
372 .chain
= arm7a_l2x_cache_commands
,
374 COMMAND_REGISTRATION_DONE
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