1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program; if not, write to the *
17 * Free Software Foundation, Inc., *
18 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
19 ***************************************************************************/
24 #include "arm7_9_common.h"
27 #include "armv4_5_mmu.h"
32 u32
armv4mmu_translate_va(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, u32 va
, int *type
, u32
*cb
, int *domain
, u32
*ap
);
33 int armv4_5_mmu_read_physical(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
34 int armv4_5_mmu_write_physical(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, u32 address
, u32 size
, u32 count
, u8
*buffer
);
36 char* armv4_5_mmu_page_type_names
[] =
38 "section", "large page", "small page", "tiny page"
41 u32
armv4_5_mmu_translate_va(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, u32 va
, int *type
, u32
*cb
, int *domain
, u32
*ap
)
43 u32 first_lvl_descriptor
= 0x0;
44 u32 second_lvl_descriptor
= 0x0;
45 u32 ttb
= armv4_5_mmu
->get_ttb(target
);
47 armv4_5_mmu_read_physical(target
, armv4_5_mmu
,
48 (ttb
& 0xffffc000) | ((va
& 0xfff00000) >> 18),
49 4, 1, (u8
*)&first_lvl_descriptor
);
50 first_lvl_descriptor
= target_buffer_get_u32(target
, (u8
*)&first_lvl_descriptor
);
52 LOG_DEBUG("1st lvl desc: %8.8x", first_lvl_descriptor
);
54 if ((first_lvl_descriptor
& 0x3) == 0)
57 LOG_ERROR("Address translation failure");
58 return ERROR_TARGET_TRANSLATION_FAULT
;
61 if (!armv4_5_mmu
->has_tiny_pages
&& ((first_lvl_descriptor
& 0x3) == 3))
64 LOG_ERROR("Address translation failure");
65 return ERROR_TARGET_TRANSLATION_FAULT
;
68 /* domain is always specified in bits 8-5 */
69 *domain
= (first_lvl_descriptor
& 0x1e0) >> 5;
71 if ((first_lvl_descriptor
& 0x3) == 2)
73 /* section descriptor */
74 *type
= ARMV4_5_SECTION
;
75 *cb
= (first_lvl_descriptor
& 0xc) >> 2;
76 *ap
= (first_lvl_descriptor
& 0xc00) >> 10;
77 return (first_lvl_descriptor
& 0xfff00000) | (va
& 0x000fffff);
80 if ((first_lvl_descriptor
& 0x3) == 1)
82 /* coarse page table */
83 armv4_5_mmu_read_physical(target
, armv4_5_mmu
,
84 (first_lvl_descriptor
& 0xfffffc00) | ((va
& 0x000ff000) >> 10),
85 4, 1, (u8
*)&second_lvl_descriptor
);
87 else if ((first_lvl_descriptor
& 0x3) == 3)
90 armv4_5_mmu_read_physical(target
, armv4_5_mmu
,
91 (first_lvl_descriptor
& 0xfffff000) | ((va
& 0x000ffc00) >> 8),
92 4, 1, (u8
*)&second_lvl_descriptor
);
95 second_lvl_descriptor
= target_buffer_get_u32(target
, (u8
*)&second_lvl_descriptor
);
97 LOG_DEBUG("2nd lvl desc: %8.8x", second_lvl_descriptor
);
99 if ((second_lvl_descriptor
& 0x3) == 0)
102 LOG_ERROR("Address translation failure");
103 return ERROR_TARGET_TRANSLATION_FAULT
;
106 /* cacheable/bufferable is always specified in bits 3-2 */
107 *cb
= (second_lvl_descriptor
& 0xc) >> 2;
109 if ((second_lvl_descriptor
& 0x3) == 1)
111 /* large page descriptor */
112 *type
= ARMV4_5_LARGE_PAGE
;
113 *ap
= (second_lvl_descriptor
& 0xff0) >> 4;
114 return (second_lvl_descriptor
& 0xffff0000) | (va
& 0x0000ffff);
117 if ((second_lvl_descriptor
& 0x3) == 2)
119 /* small page descriptor */
120 *type
= ARMV4_5_SMALL_PAGE
;
121 *ap
= (second_lvl_descriptor
& 0xff0) >> 4;
122 return (second_lvl_descriptor
& 0xfffff000) | (va
& 0x00000fff);
125 if ((second_lvl_descriptor
& 0x3) == 3)
127 /* tiny page descriptor */
128 *type
= ARMV4_5_TINY_PAGE
;
129 *ap
= (second_lvl_descriptor
& 0x30) >> 4;
130 return (second_lvl_descriptor
& 0xfffffc00) | (va
& 0x000003ff);
133 /* should not happen */
135 LOG_ERROR("Address translation failure");
136 return ERROR_TARGET_TRANSLATION_FAULT
;
139 int armv4_5_mmu_read_physical(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
143 if (target
->state
!= TARGET_HALTED
)
144 return ERROR_TARGET_NOT_HALTED
;
146 /* disable MMU and data (or unified) cache */
147 armv4_5_mmu
->disable_mmu_caches(target
, 1, 1, 0);
149 retval
= armv4_5_mmu
->read_memory(target
, address
, size
, count
, buffer
);
151 /* reenable MMU / cache */
152 armv4_5_mmu
->enable_mmu_caches(target
, armv4_5_mmu
->mmu_enabled
,
153 armv4_5_mmu
->armv4_5_cache
.d_u_cache_enabled
,
154 armv4_5_mmu
->armv4_5_cache
.i_cache_enabled
);
159 int armv4_5_mmu_write_physical(target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
, u32 address
, u32 size
, u32 count
, u8
*buffer
)
163 if (target
->state
!= TARGET_HALTED
)
164 return ERROR_TARGET_NOT_HALTED
;
166 /* disable MMU and data (or unified) cache */
167 armv4_5_mmu
->disable_mmu_caches(target
, 1, 1, 0);
169 retval
= armv4_5_mmu
->write_memory(target
, address
, size
, count
, buffer
);
171 /* reenable MMU / cache */
172 armv4_5_mmu
->enable_mmu_caches(target
, armv4_5_mmu
->mmu_enabled
,
173 armv4_5_mmu
->armv4_5_cache
.d_u_cache_enabled
,
174 armv4_5_mmu
->armv4_5_cache
.i_cache_enabled
);
179 int armv4_5_mmu_handle_virt2phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
, target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
)
188 if (target
->state
!= TARGET_HALTED
)
190 command_print(cmd_ctx
, "target must be stopped for \"virt2phys\" command");
196 command_print(cmd_ctx
, "usage: virt2phys <virtual address>");
202 va
= strtoul(args
[0], NULL
, 0);
203 pa
= armv4_5_mmu_translate_va(target
, armv4_5_mmu
, va
, &type
, &cb
, &domain
, &ap
);
208 case ERROR_TARGET_TRANSLATION_FAULT
:
209 command_print(cmd_ctx
, "no valid translation for 0x%8.8x", va
);
212 command_print(cmd_ctx
, "unknown translation error");
217 command_print(cmd_ctx
, "0x%8.8x -> 0x%8.8x, type: %s, cb: %i, domain: %i, ap: %2.2x",
218 va
, pa
, armv4_5_mmu_page_type_names
[type
], cb
, domain
, ap
);
224 int armv4_5_mmu_handle_md_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
, target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
)
238 if (target
->state
!= TARGET_HALTED
)
240 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
248 count
= strtoul(args
[1], NULL
, 0);
250 address
= strtoul(args
[0], NULL
, 0);
267 buffer
= calloc(count
, size
);
268 if ((retval
= armv4_5_mmu_read_physical(target
, armv4_5_mmu
, address
, size
, count
, buffer
)) != ERROR_OK
)
272 case ERROR_TARGET_UNALIGNED_ACCESS
:
273 command_print(cmd_ctx
, "error: address not aligned");
275 case ERROR_TARGET_NOT_HALTED
:
276 command_print(cmd_ctx
, "error: target must be halted for memory accesses");
278 case ERROR_TARGET_DATA_ABORT
:
279 command_print(cmd_ctx
, "error: access caused data abort, system possibly corrupted");
282 command_print(cmd_ctx
, "error: unknown error");
288 for (i
= 0; i
< count
; i
++)
291 output_len
+= snprintf(output
+ output_len
, 128 - output_len
, "0x%8.8x: ", address
+ (i
*size
));
296 output_len
+= snprintf(output
+ output_len
, 128 - output_len
, "%8.8x ", target_buffer_get_u32(target
, &buffer
[i
*4]));
299 output_len
+= snprintf(output
+ output_len
, 128 - output_len
, "%4.4x ", target_buffer_get_u16(target
, &buffer
[i
*2]));
302 output_len
+= snprintf(output
+ output_len
, 128 - output_len
, "%2.2x ", buffer
[i
*1]);
306 if ((i
% 8 == 7) || (i
== count
- 1))
308 command_print(cmd_ctx
, output
);
318 int armv4_5_mmu_handle_mw_phys_command(command_context_t
*cmd_ctx
, char *cmd
, char **args
, int argc
, target_t
*target
, armv4_5_mmu_common_t
*armv4_5_mmu
)
325 if (target
->state
!= TARGET_HALTED
)
327 command_print(cmd_ctx
, "target must be stopped for \"%s\" command", cmd
);
334 address
= strtoul(args
[0], NULL
, 0);
335 value
= strtoul(args
[1], NULL
, 0);
340 target_buffer_set_u32(target
, value_buf
, value
);
341 retval
= armv4_5_mmu_write_physical(target
, armv4_5_mmu
, address
, 4, 1, value_buf
);
344 target_buffer_set_u16(target
, value_buf
, value
);
345 retval
= armv4_5_mmu_write_physical(target
, armv4_5_mmu
, address
, 2, 1, value_buf
);
348 value_buf
[0] = value
;
349 retval
= armv4_5_mmu_write_physical(target
, armv4_5_mmu
, address
, 1, 1, value_buf
);
357 case ERROR_TARGET_UNALIGNED_ACCESS
:
358 command_print(cmd_ctx
, "error: address not aligned");
360 case ERROR_TARGET_DATA_ABORT
:
361 command_print(cmd_ctx
, "error: access caused data abort, system possibly corrupted");
363 case ERROR_TARGET_NOT_HALTED
:
364 command_print(cmd_ctx
, "error: target must be halted for memory accesses");
369 command_print(cmd_ctx
, "error: unknown error");
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)