1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
5 * This program is free software; you can redistribute it and/or modify *
6 * it under the terms of the GNU General Public License as published by *
7 * the Free Software Foundation; either version 2 of the License, or *
8 * (at your option) any later version. *
10 * This program is distributed in the hope that it will be useful, *
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
13 * GNU General Public License for more details. *
15 * You should have received a copy of the GNU General Public License *
16 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
17 ***************************************************************************/
23 #include <helper/log.h>
25 #include "armv4_5_mmu.h"
27 int armv4_5_mmu_translate_va(struct target
*target
,
28 struct armv4_5_mmu_common
*armv4_5_mmu
, uint32_t va
, uint32_t *cb
, uint32_t *val
)
30 uint32_t first_lvl_descriptor
= 0x0;
31 uint32_t second_lvl_descriptor
= 0x0;
34 retval
= armv4_5_mmu
->get_ttb(target
, &ttb
);
35 if (retval
!= ERROR_OK
)
38 retval
= armv4_5_mmu_read_physical(target
, armv4_5_mmu
,
39 (ttb
& 0xffffc000) | ((va
& 0xfff00000) >> 18),
40 4, 1, (uint8_t *)&first_lvl_descriptor
);
41 if (retval
!= ERROR_OK
)
43 first_lvl_descriptor
= target_buffer_get_u32(target
, (uint8_t *)&first_lvl_descriptor
);
45 LOG_DEBUG("1st lvl desc: %8.8" PRIx32
"", first_lvl_descriptor
);
47 if ((first_lvl_descriptor
& 0x3) == 0) {
48 LOG_ERROR("Address translation failure");
49 return ERROR_TARGET_TRANSLATION_FAULT
;
52 if (!armv4_5_mmu
->has_tiny_pages
&& ((first_lvl_descriptor
& 0x3) == 3)) {
53 LOG_ERROR("Address translation failure");
54 return ERROR_TARGET_TRANSLATION_FAULT
;
57 if ((first_lvl_descriptor
& 0x3) == 2) {
58 /* section descriptor */
59 *cb
= (first_lvl_descriptor
& 0xc) >> 2;
60 *val
= (first_lvl_descriptor
& 0xfff00000) | (va
& 0x000fffff);
64 if ((first_lvl_descriptor
& 0x3) == 1) {
65 /* coarse page table */
66 retval
= armv4_5_mmu_read_physical(target
, armv4_5_mmu
,
67 (first_lvl_descriptor
& 0xfffffc00) | ((va
& 0x000ff000) >> 10),
68 4, 1, (uint8_t *)&second_lvl_descriptor
);
69 if (retval
!= ERROR_OK
)
71 } else if ((first_lvl_descriptor
& 0x3) == 3) {
73 retval
= armv4_5_mmu_read_physical(target
, armv4_5_mmu
,
74 (first_lvl_descriptor
& 0xfffff000) | ((va
& 0x000ffc00) >> 8),
75 4, 1, (uint8_t *)&second_lvl_descriptor
);
76 if (retval
!= ERROR_OK
)
80 second_lvl_descriptor
= target_buffer_get_u32(target
, (uint8_t *)&second_lvl_descriptor
);
82 LOG_DEBUG("2nd lvl desc: %8.8" PRIx32
"", second_lvl_descriptor
);
84 if ((second_lvl_descriptor
& 0x3) == 0) {
85 LOG_ERROR("Address translation failure");
86 return ERROR_TARGET_TRANSLATION_FAULT
;
89 /* cacheable/bufferable is always specified in bits 3-2 */
90 *cb
= (second_lvl_descriptor
& 0xc) >> 2;
92 if ((second_lvl_descriptor
& 0x3) == 1) {
93 /* large page descriptor */
94 *val
= (second_lvl_descriptor
& 0xffff0000) | (va
& 0x0000ffff);
98 if ((second_lvl_descriptor
& 0x3) == 2) {
99 /* small page descriptor */
100 *val
= (second_lvl_descriptor
& 0xfffff000) | (va
& 0x00000fff);
104 if ((second_lvl_descriptor
& 0x3) == 3) {
105 /* tiny page descriptor */
106 *val
= (second_lvl_descriptor
& 0xfffffc00) | (va
& 0x000003ff);
110 /* should not happen */
111 LOG_ERROR("Address translation failure");
112 return ERROR_TARGET_TRANSLATION_FAULT
;
115 int armv4_5_mmu_read_physical(struct target
*target
,
116 struct armv4_5_mmu_common
*armv4_5_mmu
, uint32_t address
,
117 uint32_t size
, uint32_t count
, uint8_t *buffer
)
121 if (target
->state
!= TARGET_HALTED
)
122 return ERROR_TARGET_NOT_HALTED
;
124 /* disable MMU and data (or unified) cache */
125 retval
= armv4_5_mmu
->disable_mmu_caches(target
, 1, 1, 0);
126 if (retval
!= ERROR_OK
)
129 retval
= armv4_5_mmu
->read_memory(target
, address
, size
, count
, buffer
);
130 if (retval
!= ERROR_OK
)
133 /* reenable MMU / cache */
134 retval
= armv4_5_mmu
->enable_mmu_caches(target
, armv4_5_mmu
->mmu_enabled
,
135 armv4_5_mmu
->armv4_5_cache
.d_u_cache_enabled
,
136 armv4_5_mmu
->armv4_5_cache
.i_cache_enabled
);
137 if (retval
!= ERROR_OK
)
143 int armv4_5_mmu_write_physical(struct target
*target
,
144 struct armv4_5_mmu_common
*armv4_5_mmu
, uint32_t address
,
145 uint32_t size
, uint32_t count
, const uint8_t *buffer
)
149 if (target
->state
!= TARGET_HALTED
)
150 return ERROR_TARGET_NOT_HALTED
;
152 /* disable MMU and data (or unified) cache */
153 retval
= armv4_5_mmu
->disable_mmu_caches(target
, 1, 1, 0);
154 if (retval
!= ERROR_OK
)
157 retval
= armv4_5_mmu
->write_memory(target
, address
, size
, count
, buffer
);
158 if (retval
!= ERROR_OK
)
161 /* reenable MMU / cache */
162 retval
= armv4_5_mmu
->enable_mmu_caches(target
, armv4_5_mmu
->mmu_enabled
,
163 armv4_5_mmu
->armv4_5_cache
.d_u_cache_enabled
,
164 armv4_5_mmu
->armv4_5_cache
.i_cache_enabled
);
165 if (retval
!= ERROR_OK
)
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