src/target/armv4_5.h

   1 /***************************************************************************
   2  *   Copyright (C) 2005 by Dominic Rath                                    *
   3  *   Dominic.Rath@gmx.de                                                   *
   4  *                                                                         *
   5  *   Copyright (C) 2008 by Spencer Oliver                                  *
   6  *   spen@spen-soft.co.uk                                                  *
   7  *                                                                         *
   8  *   Copyright (C) 2009 by Øyvind Harboe                                   *
   9  *   oyvind.harboe@zylin.com                                               *
  10  *                                                                         *
  11  *   This program is free software; you can redistribute it and/or modify  *
  12  *   it under the terms of the GNU General Public License as published by  *
  13  *   the Free Software Foundation; either version 2 of the License, or     *
  14  *   (at your option) any later version.                                   *
  15  *                                                                         *
  16  *   This program is distributed in the hope that it will be useful,       *
  17  *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
  18  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
  19  *   GNU General Public License for more details.                          *
  20  *                                                                         *
  21  *   You should have received a copy of the GNU General Public License     *
  22  *   along with this program; if not, write to the                         *
  23  *   Free Software Foundation, Inc.,                                       *
  24  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  25  ***************************************************************************/
  26 #ifndef ARMV4_5_H
  27 #define ARMV4_5_H
  28
  29 #include <target/target.h>
  30 #include <helper/command.h>
  31
  32
  33 /* These numbers match the five low bits of the *PSR registers on
  34  * "classic ARM" processors, which build on the ARMv4 processor
  35  * modes and register set.
  36  */
  37 enum arm_mode {
  38         ARM_MODE_USR = 16,
  39         ARM_MODE_FIQ = 17,
  40         ARM_MODE_IRQ = 18,
  41         ARM_MODE_SVC = 19,
  42         ARM_MODE_ABT = 23,
  43         ARM_MODE_MON = 26,
  44         ARM_MODE_UND = 27,
  45         ARM_MODE_SYS = 31,
  46         ARM_MODE_ANY = -1
  47 };
  48
  49 const char *arm_mode_name(unsigned psr_mode);
  50 bool is_arm_mode(unsigned psr_mode);
  51
  52 /* The PSR "T" and "J" bits define the mode of "classic ARM" cores */
  53 enum arm_state {
  54         ARM_STATE_ARM,
  55         ARM_STATE_THUMB,
  56         ARM_STATE_JAZELLE,
  57         ARM_STATE_THUMB_EE,
  58 };
  59
  60 extern const char *arm_state_strings[];
  61
  62 /* OBSOLETE, DO NOT USE IN NEW CODE!  The "number" of an arm_mode is an
  63  * index into the armv4_5_core_reg_map array.  Its remaining users are
  64  * remnants which could as easily walk * the register cache directly as
  65  * use the expensive ARMV4_5_CORE_REG_MODE() macro.
  66  */
  67 int arm_mode_to_number(enum arm_mode mode);
  68 enum arm_mode armv4_5_number_to_mode(int number);
  69
  70 extern const int armv4_5_core_reg_map[8][17];
  71
  72 #define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
  73                 cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]]
  74
  75 /* offset into armv4_5 core register cache -- OBSOLETE, DO NOT USE! */
  76 enum { ARMV4_5_CPSR = 31, };
  77
  78 #define ARM_COMMON_MAGIC 0x0A450A45
  79
  80 /**
  81  * Represents a generic ARM core, with standard application registers.
  82  *
  83  * There are sixteen application registers (including PC, SP, LR) and a PSR.
  84  * Cortex-M series cores do not support as many core states or shadowed
  85  * registers as traditional ARM cores, and only support Thumb2 instructions.
  86  */
  87 struct arm
  88 {
  89         int common_magic;
  90         struct reg_cache *core_cache;
  91
  92         /** Handle to the CPSR; valid in all core modes. */
  93         struct reg *cpsr;
  94
  95         /** Handle to the SPSR; valid only in core modes with an SPSR. */
  96         struct reg *spsr;
  97
  98         const int *map;
  99
 100         /**
 101          * Indicates what registers are in the ARM state core register set.
 102          * ARM_MODE_ANY indicates the standard set of 37 registers,
 103          * seen on for example ARM7TDMI cores.  ARM_MODE_MON indicates three
 104          * more registers are shadowed, for "Secure Monitor" mode.
 105          */
 106         enum arm_mode core_type;
 107
 108         enum arm_mode core_mode;
 109         enum arm_state core_state;
 110
 111         /** Flag reporting unavailability of the BKPT instruction. */
 112         bool is_armv4;
 113
 114         /** Flag reporting whether semihosting is active. */
 115         bool is_semihosting;
 116
 117         /** Value to be returned by semihosting SYS_ERRNO request. */
 118         int semihosting_errno;
 119
 120         /** Backpointer to the target. */
 121         struct target *target;
 122
 123         /** Handle for the debug module, if one is present. */
 124         struct arm_dpm *dpm;
 125
 126         /** Handle for the Embedded Trace Module, if one is present. */
 127         struct etm_context *etm;
 128
 129         /* FIXME all these methods should take "struct arm *" not target */
 130
 131         int (*full_context)(struct target *target);
 132         int (*read_core_reg)(struct target *target, struct reg *reg,
 133                         int num, enum arm_mode mode);
 134         int (*write_core_reg)(struct target *target, struct reg *reg,
 135                         int num, enum arm_mode mode, uint32_t value);
 136
 137         /** Read coprocessor register.  */
 138         int (*mrc)(struct target *target, int cpnum,
 139                         uint32_t op1, uint32_t op2,
 140                         uint32_t CRn, uint32_t CRm,
 141                         uint32_t *value);
 142
 143         /* Write coprocessor register.  */
 144         int (*mcr)(struct target *target, int cpnum,
 145                         uint32_t op1, uint32_t op2,
 146                         uint32_t CRn, uint32_t CRm,
 147                         uint32_t value);
 148
 149         void *arch_info;
 150 };
 151
 152 /** Convert target handle to generic ARM target state handle. */
 153 static inline struct arm *target_to_arm(struct target *target)
 154 {
 155         return target->arch_info;
 156 }
 157
 158 static inline bool is_arm(struct arm *arm)
 159 {
 160         return arm && arm->common_magic == ARM_COMMON_MAGIC;
 161 }
 162
 163 struct arm_algorithm
 164 {
 165         int common_magic;
 166
 167         enum arm_mode core_mode;
 168         enum arm_state core_state;
 169 };
 170
 171 struct arm_reg
 172 {
 173         int num;
 174         enum arm_mode mode;
 175         struct target *target;
 176         struct arm *armv4_5_common;
 177         uint32_t value;
 178 };
 179
 180 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm);
 181
 182 int armv4_5_arch_state(struct target *target);
 183 int armv4_5_get_gdb_reg_list(struct target *target,
 184                 struct reg **reg_list[], int *reg_list_size);
 185
 186 extern const struct command_registration arm_command_handlers[];
 187
 188 int armv4_5_init_arch_info(struct target *target, struct arm *armv4_5);
 189
 190 int armv4_5_run_algorithm(struct target *target,
 191                 int num_mem_params, struct mem_param *mem_params,
 192                 int num_reg_params, struct reg_param *reg_params,
 193                 uint32_t entry_point, uint32_t exit_point,
 194                 int timeout_ms, void *arch_info);
 195
 196 int arm_checksum_memory(struct target *target,
 197                 uint32_t address, uint32_t count, uint32_t *checksum);
 198 int arm_blank_check_memory(struct target *target,
 199                 uint32_t address, uint32_t count, uint32_t *blank);
 200
 201 void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
 202 struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
 203
 204 extern struct reg arm_gdb_dummy_fp_reg;
 205 extern struct reg arm_gdb_dummy_fps_reg;
 206
 207 /* ARM mode instructions
 208  */
 209
 210 /* Store multiple increment after
 211  * Rn: base register
 212  * List: for each bit in list: store register
 213  * S: in priviledged mode: store user-mode registers
 214  * W = 1: update the base register. W = 0: leave the base register untouched
 215  */
 216 #define ARMV4_5_STMIA(Rn, List, S, W)   (0xe8800000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 217
 218 /* Load multiple increment after
 219  * Rn: base register
 220  * List: for each bit in list: store register
 221  * S: in priviledged mode: store user-mode registers
 222  * W = 1: update the base register. W = 0: leave the base register untouched
 223  */
 224 #define ARMV4_5_LDMIA(Rn, List, S, W)   (0xe8900000 | ((S) << 22) | ((W) << 21) | ((Rn) << 16) | (List))
 225
 226 /* MOV r8, r8 */
 227 #define ARMV4_5_NOP                                     (0xe1a08008)
 228
 229 /* Move PSR to general purpose register
 230  * R = 1: SPSR R = 0: CPSR
 231  * Rn: target register
 232  */
 233 #define ARMV4_5_MRS(Rn, R)                      (0xe10f0000 | ((R) << 22) | ((Rn) << 12))
 234
 235 /* Store register
 236  * Rd: register to store
 237  * Rn: base register
 238  */
 239 #define ARMV4_5_STR(Rd, Rn)                     (0xe5800000 | ((Rd) << 12) | ((Rn) << 16))
 240
 241 /* Load register
 242  * Rd: register to load
 243  * Rn: base register
 244  */
 245 #define ARMV4_5_LDR(Rd, Rn)                     (0xe5900000 | ((Rd) << 12) | ((Rn) << 16))
 246
 247 /* Move general purpose register to PSR
 248  * R = 1: SPSR R = 0: CPSR
 249  * Field: Field mask
 250  * 1: control field 2: extension field 4: status field 8: flags field
 251  * Rm: source register
 252  */
 253 #define ARMV4_5_MSR_GP(Rm, Field, R)    (0xe120f000 | (Rm) | ((Field) << 16) | ((R) << 22))
 254 #define ARMV4_5_MSR_IM(Im, Rotate, Field, R)    (0xe320f000 | (Im)  | ((Rotate) << 8) | ((Field) << 16) | ((R) << 22))
 255
 256 /* Load Register Halfword Immediate Post-Index
 257  * Rd: register to load
 258  * Rn: base register
 259  */
 260 #define ARMV4_5_LDRH_IP(Rd, Rn) (0xe0d000b2 | ((Rd) << 12) | ((Rn) << 16))
 261
 262 /* Load Register Byte Immediate Post-Index
 263  * Rd: register to load
 264  * Rn: base register
 265  */
 266 #define ARMV4_5_LDRB_IP(Rd, Rn) (0xe4d00001 | ((Rd) << 12) | ((Rn) << 16))
 267
 268 /* Store register Halfword Immediate Post-Index
 269  * Rd: register to store
 270  * Rn: base register
 271  */
 272 #define ARMV4_5_STRH_IP(Rd, Rn) (0xe0c000b2 | ((Rd) << 12) | ((Rn) << 16))
 273
 274 /* Store register Byte Immediate Post-Index
 275  * Rd: register to store
 276  * Rn: base register
 277  */
 278 #define ARMV4_5_STRB_IP(Rd, Rn) (0xe4c00001 | ((Rd) << 12) | ((Rn) << 16))
 279
 280 /* Branch (and Link)
 281  * Im: Branch target (left-shifted by 2 bits, added to PC)
 282  * L: 1: branch and link 0: branch only
 283  */
 284 #define ARMV4_5_B(Im, L) (0xea000000 | (Im) | ((L) << 24))
 285
 286 /* Branch and exchange (ARM state)
 287  * Rm: register holding branch target address
 288  */
 289 #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm))
 290
 291 /* Move to ARM register from coprocessor
 292  * CP: Coprocessor number
 293  * op1: Coprocessor opcode
 294  * Rd: destination register
 295  * CRn: first coprocessor operand
 296  * CRm: second coprocessor operand
 297  * op2: Second coprocessor opcode
 298  */
 299 #define ARMV4_5_MRC(CP, op1, Rd, CRn, CRm, op2) (0xee100010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 300
 301 /* Move to coprocessor from ARM register
 302  * CP: Coprocessor number
 303  * op1: Coprocessor opcode
 304  * Rd: destination register
 305  * CRn: first coprocessor operand
 306  * CRm: second coprocessor operand
 307  * op2: Second coprocessor opcode
 308  */
 309 #define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
 310
 311 /* Breakpoint instruction (ARMv5)
 312  * Im: 16-bit immediate
 313  */
 314 #define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
 315
 316
 317 /* Thumb mode instructions
 318  */
 319
 320 /* Store register (Thumb mode)
 321  * Rd: source register
 322  * Rn: base register
 323  */
 324 #define ARMV4_5_T_STR(Rd, Rn)   ((0x6000 | (Rd) | ((Rn) << 3)) | ((0x6000 | (Rd) | ((Rn) << 3)) << 16))
 325
 326 /* Load register (Thumb state)
 327  * Rd: destination register
 328  * Rn: base register
 329  */
 330 #define ARMV4_5_T_LDR(Rd, Rn)   ((0x6800 | ((Rn) << 3) | (Rd)) | ((0x6800 | ((Rn) << 3) | (Rd)) << 16))
 331
 332 /* Load multiple (Thumb state)
 333  * Rn: base register
 334  * List: for each bit in list: store register
 335  */
 336 #define ARMV4_5_T_LDMIA(Rn, List) ((0xc800 | ((Rn) << 8) | (List)) | ((0xc800 | ((Rn) << 8) | List) << 16))
 337
 338 /* Load register with PC relative addressing
 339  * Rd: register to load
 340  */
 341 #define ARMV4_5_T_LDR_PCREL(Rd) ((0x4800 | ((Rd) << 8)) | ((0x4800 | ((Rd) << 8)) << 16))
 342
 343 /* Move hi register (Thumb mode)
 344  * Rd: destination register
 345  * Rm: source register
 346  */
 347 #define ARMV4_5_T_MOV(Rd, Rm)   ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) | ((0x4600 | ((Rd) & 0x7) | (((Rd) & 0x8) << 4) | (((Rm) & 0x7) << 3) | (((Rm) & 0x8) << 3)) << 16))
 348
 349 /* No operation (Thumb mode)
 350  */
 351 #define ARMV4_5_T_NOP   (0x46c0 | (0x46c0 << 16))
 352
 353 /* Move immediate to register (Thumb state)
 354  * Rd: destination register
 355  * Im: 8-bit immediate value
 356  */
 357 #define ARMV4_5_T_MOV_IM(Rd, Im)        ((0x2000 | ((Rd) << 8) | (Im)) | ((0x2000 | ((Rd) << 8) | (Im)) << 16))
 358
 359 /* Branch and Exchange
 360  * Rm: register containing branch target
 361  */
 362 #define ARMV4_5_T_BX(Rm)                ((0x4700 | ((Rm) << 3)) | ((0x4700 | ((Rm) << 3)) << 16))
 363
 364 /* Branch (Thumb state)
 365  * Imm: Branch target
 366  */
 367 #define ARMV4_5_T_B(Imm)        ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
 368
 369 /* Breakpoint instruction (ARMv5) (Thumb state)
 370  * Im: 8-bit immediate
 371  */
 372 #define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
 373
 374 /* build basic mrc/mcr opcode */
 375
 376 static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
 377 {
 378         uint32_t t = 0;
 379         t|=op1<<21;
 380         t|=op2<<5;
 381         t|=CRn<<16;
 382         t|=CRm<<0;
 383         return t;
 384 }
 385
 386 #endif /* ARMV4_5_H */