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armv7a: access monitor registers only with security extensions
[openocd.git] / src / target / armv4_5.c
1 /***************************************************************************
2 * Copyright (C) 2005 by Dominic Rath *
3 * Dominic.Rath@gmx.de *
4 * *
5 * Copyright (C) 2008 by Spencer Oliver *
6 * spen@spen-soft.co.uk *
7 * *
8 * Copyright (C) 2008 by Oyvind Harboe *
9 * oyvind.harboe@zylin.com *
10 * *
11 * Copyright (C) 2018 by Liviu Ionescu *
12 * <ilg@livius.net> *
13 * *
14 * This program is free software; you can redistribute it and/or modify *
15 * it under the terms of the GNU General Public License as published by *
16 * the Free Software Foundation; either version 2 of the License, or *
17 * (at your option) any later version. *
18 * *
19 * This program is distributed in the hope that it will be useful, *
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
22 * GNU General Public License for more details. *
23 * *
24 * You should have received a copy of the GNU General Public License *
25 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
26 ***************************************************************************/
27
28 #ifdef HAVE_CONFIG_H
29 #include "config.h"
30 #endif
31
32 #include "arm.h"
33 #include "armv4_5.h"
34 #include "arm_jtag.h"
35 #include "breakpoints.h"
36 #include "arm_disassembler.h"
37 #include <helper/binarybuffer.h>
38 #include "algorithm.h"
39 #include "register.h"
40 #include "semihosting_common.h"
41
42 /* offsets into armv4_5 core register cache */
43 enum {
44 /* ARMV4_5_CPSR = 31, */
45 ARMV4_5_SPSR_FIQ = 32,
46 ARMV4_5_SPSR_IRQ = 33,
47 ARMV4_5_SPSR_SVC = 34,
48 ARMV4_5_SPSR_ABT = 35,
49 ARMV4_5_SPSR_UND = 36,
50 ARM_SPSR_MON = 41,
51 };
52
53 static const uint8_t arm_usr_indices[17] = {
54 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, ARMV4_5_CPSR,
55 };
56
57 static const uint8_t arm_fiq_indices[8] = {
58 16, 17, 18, 19, 20, 21, 22, ARMV4_5_SPSR_FIQ,
59 };
60
61 static const uint8_t arm_irq_indices[3] = {
62 23, 24, ARMV4_5_SPSR_IRQ,
63 };
64
65 static const uint8_t arm_svc_indices[3] = {
66 25, 26, ARMV4_5_SPSR_SVC,
67 };
68
69 static const uint8_t arm_abt_indices[3] = {
70 27, 28, ARMV4_5_SPSR_ABT,
71 };
72
73 static const uint8_t arm_und_indices[3] = {
74 29, 30, ARMV4_5_SPSR_UND,
75 };
76
77 static const uint8_t arm_mon_indices[3] = {
78 39, 40, ARM_SPSR_MON,
79 };
80
81 static const struct {
82 const char *name;
83 unsigned short psr;
84 /* For user and system modes, these list indices for all registers.
85 * otherwise they're just indices for the shadow registers and SPSR.
86 */
87 unsigned short n_indices;
88 const uint8_t *indices;
89 } arm_mode_data[] = {
90 /* Seven modes are standard from ARM7 on. "System" and "User" share
91 * the same registers; other modes shadow from 3 to 8 registers.
92 */
93 {
94 .name = "User",
95 .psr = ARM_MODE_USR,
96 .n_indices = ARRAY_SIZE(arm_usr_indices),
97 .indices = arm_usr_indices,
98 },
99 {
100 .name = "FIQ",
101 .psr = ARM_MODE_FIQ,
102 .n_indices = ARRAY_SIZE(arm_fiq_indices),
103 .indices = arm_fiq_indices,
104 },
105 {
106 .name = "Supervisor",
107 .psr = ARM_MODE_SVC,
108 .n_indices = ARRAY_SIZE(arm_svc_indices),
109 .indices = arm_svc_indices,
110 },
111 {
112 .name = "Abort",
113 .psr = ARM_MODE_ABT,
114 .n_indices = ARRAY_SIZE(arm_abt_indices),
115 .indices = arm_abt_indices,
116 },
117 {
118 .name = "IRQ",
119 .psr = ARM_MODE_IRQ,
120 .n_indices = ARRAY_SIZE(arm_irq_indices),
121 .indices = arm_irq_indices,
122 },
123 {
124 .name = "Undefined instruction",
125 .psr = ARM_MODE_UND,
126 .n_indices = ARRAY_SIZE(arm_und_indices),
127 .indices = arm_und_indices,
128 },
129 {
130 .name = "System",
131 .psr = ARM_MODE_SYS,
132 .n_indices = ARRAY_SIZE(arm_usr_indices),
133 .indices = arm_usr_indices,
134 },
135 /* TrustZone "Security Extensions" add a secure monitor mode.
136 * This is distinct from a "debug monitor" which can support
137 * non-halting debug, in conjunction with some debuggers.
138 */
139 {
140 .name = "Secure Monitor",
141 .psr = ARM_MODE_MON,
142 .n_indices = ARRAY_SIZE(arm_mon_indices),
143 .indices = arm_mon_indices,
144 },
145 {
146 .name = "Secure Monitor ARM1176JZF-S",
147 .psr = ARM_MODE_1176_MON,
148 .n_indices = ARRAY_SIZE(arm_mon_indices),
149 .indices = arm_mon_indices,
150 },
151
152 /* These special modes are currently only supported
153 * by ARMv6M and ARMv7M profiles */
154 {
155 .name = "Thread",
156 .psr = ARM_MODE_THREAD,
157 },
158 {
159 .name = "Thread (User)",
160 .psr = ARM_MODE_USER_THREAD,
161 },
162 {
163 .name = "Handler",
164 .psr = ARM_MODE_HANDLER,
165 },
166 };
167
168 /** Map PSR mode bits to the name of an ARM processor operating mode. */
169 const char *arm_mode_name(unsigned psr_mode)
170 {
171 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
172 if (arm_mode_data[i].psr == psr_mode)
173 return arm_mode_data[i].name;
174 }
175 LOG_ERROR("unrecognized psr mode: %#02x", psr_mode);
176 return "UNRECOGNIZED";
177 }
178
179 /** Return true iff the parameter denotes a valid ARM processor mode. */
180 bool is_arm_mode(unsigned psr_mode)
181 {
182 for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
183 if (arm_mode_data[i].psr == psr_mode)
184 return true;
185 }
186 return false;
187 }
188
189 /** Map PSR mode bits to linear number indexing armv4_5_core_reg_map */
190 int arm_mode_to_number(enum arm_mode mode)
191 {
192 switch (mode) {
193 case ARM_MODE_ANY:
194 /* map MODE_ANY to user mode */
195 case ARM_MODE_USR:
196 return 0;
197 case ARM_MODE_FIQ:
198 return 1;
199 case ARM_MODE_IRQ:
200 return 2;
201 case ARM_MODE_SVC:
202 return 3;
203 case ARM_MODE_ABT:
204 return 4;
205 case ARM_MODE_UND:
206 return 5;
207 case ARM_MODE_SYS:
208 return 6;
209 case ARM_MODE_MON:
210 case ARM_MODE_1176_MON:
211 return 7;
212 default:
213 LOG_ERROR("invalid mode value encountered %d", mode);
214 return -1;
215 }
216 }
217
218 /** Map linear number indexing armv4_5_core_reg_map to PSR mode bits. */
219 enum arm_mode armv4_5_number_to_mode(int number)
220 {
221 switch (number) {
222 case 0:
223 return ARM_MODE_USR;
224 case 1:
225 return ARM_MODE_FIQ;
226 case 2:
227 return ARM_MODE_IRQ;
228 case 3:
229 return ARM_MODE_SVC;
230 case 4:
231 return ARM_MODE_ABT;
232 case 5:
233 return ARM_MODE_UND;
234 case 6:
235 return ARM_MODE_SYS;
236 case 7:
237 return ARM_MODE_MON;
238 default:
239 LOG_ERROR("mode index out of bounds %d", number);
240 return ARM_MODE_ANY;
241 }
242 }
243
244 static const char *arm_state_strings[] = {
245 "ARM", "Thumb", "Jazelle", "ThumbEE",
246 };
247
248 /* Templates for ARM core registers.
249 *
250 * NOTE: offsets in this table are coupled to the arm_mode_data
251 * table above, the armv4_5_core_reg_map array below, and also to
252 * the ARMV4_5_CPSR symbol (which should vanish after ARM11 updates).
253 */
254 static const struct {
255 /* The name is used for e.g. the "regs" command. */
256 const char *name;
257
258 /* The {cookie, mode} tuple uniquely identifies one register.
259 * In a given mode, cookies 0..15 map to registers R0..R15,
260 * with R13..R15 usually called SP, LR, PC.
261 *
262 * MODE_ANY is used as *input* to the mapping, and indicates
263 * various special cases (sigh) and errors.
264 *
265 * Cookie 16 is (currently) confusing, since it indicates
266 * CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
267 * (Exception modes have both CPSR and SPSR registers ...)
268 */
269 unsigned cookie;
270 unsigned gdb_index;
271 enum arm_mode mode;
272 } arm_core_regs[] = {
273 /* IMPORTANT: we guarantee that the first eight cached registers
274 * correspond to r0..r7, and the fifteenth to PC, so that callers
275 * don't need to map them.
276 */
277 [0] = { .name = "r0", .cookie = 0, .mode = ARM_MODE_ANY, .gdb_index = 0, },
278 [1] = { .name = "r1", .cookie = 1, .mode = ARM_MODE_ANY, .gdb_index = 1, },
279 [2] = { .name = "r2", .cookie = 2, .mode = ARM_MODE_ANY, .gdb_index = 2, },
280 [3] = { .name = "r3", .cookie = 3, .mode = ARM_MODE_ANY, .gdb_index = 3, },
281 [4] = { .name = "r4", .cookie = 4, .mode = ARM_MODE_ANY, .gdb_index = 4, },
282 [5] = { .name = "r5", .cookie = 5, .mode = ARM_MODE_ANY, .gdb_index = 5, },
283 [6] = { .name = "r6", .cookie = 6, .mode = ARM_MODE_ANY, .gdb_index = 6, },
284 [7] = { .name = "r7", .cookie = 7, .mode = ARM_MODE_ANY, .gdb_index = 7, },
285
286 /* NOTE: regs 8..12 might be shadowed by FIQ ... flagging
287 * them as MODE_ANY creates special cases. (ANY means
288 * "not mapped" elsewhere; here it's "everything but FIQ".)
289 */
290 [8] = { .name = "r8", .cookie = 8, .mode = ARM_MODE_ANY, .gdb_index = 8, },
291 [9] = { .name = "r9", .cookie = 9, .mode = ARM_MODE_ANY, .gdb_index = 9, },
292 [10] = { .name = "r10", .cookie = 10, .mode = ARM_MODE_ANY, .gdb_index = 10, },
293 [11] = { .name = "r11", .cookie = 11, .mode = ARM_MODE_ANY, .gdb_index = 11, },
294 [12] = { .name = "r12", .cookie = 12, .mode = ARM_MODE_ANY, .gdb_index = 12, },
295
296 /* Historical GDB mapping of indices:
297 * - 13-14 are sp and lr, but banked counterparts are used
298 * - 16-24 are left for deprecated 8 FPA + 1 FPS
299 * - 25 is the cpsr
300 */
301
302 /* NOTE all MODE_USR registers are equivalent to MODE_SYS ones */
303 [13] = { .name = "sp_usr", .cookie = 13, .mode = ARM_MODE_USR, .gdb_index = 26, },
304 [14] = { .name = "lr_usr", .cookie = 14, .mode = ARM_MODE_USR, .gdb_index = 27, },
305
306 /* guaranteed to be at index 15 */
307 [15] = { .name = "pc", .cookie = 15, .mode = ARM_MODE_ANY, .gdb_index = 15, },
308 [16] = { .name = "r8_fiq", .cookie = 8, .mode = ARM_MODE_FIQ, .gdb_index = 28, },
309 [17] = { .name = "r9_fiq", .cookie = 9, .mode = ARM_MODE_FIQ, .gdb_index = 29, },
310 [18] = { .name = "r10_fiq", .cookie = 10, .mode = ARM_MODE_FIQ, .gdb_index = 30, },
311 [19] = { .name = "r11_fiq", .cookie = 11, .mode = ARM_MODE_FIQ, .gdb_index = 31, },
312 [20] = { .name = "r12_fiq", .cookie = 12, .mode = ARM_MODE_FIQ, .gdb_index = 32, },
313
314 [21] = { .name = "sp_fiq", .cookie = 13, .mode = ARM_MODE_FIQ, .gdb_index = 33, },
315 [22] = { .name = "lr_fiq", .cookie = 14, .mode = ARM_MODE_FIQ, .gdb_index = 34, },
316
317 [23] = { .name = "sp_irq", .cookie = 13, .mode = ARM_MODE_IRQ, .gdb_index = 35, },
318 [24] = { .name = "lr_irq", .cookie = 14, .mode = ARM_MODE_IRQ, .gdb_index = 36, },
319
320 [25] = { .name = "sp_svc", .cookie = 13, .mode = ARM_MODE_SVC, .gdb_index = 37, },
321 [26] = { .name = "lr_svc", .cookie = 14, .mode = ARM_MODE_SVC, .gdb_index = 38, },
322
323 [27] = { .name = "sp_abt", .cookie = 13, .mode = ARM_MODE_ABT, .gdb_index = 39, },
324 [28] = { .name = "lr_abt", .cookie = 14, .mode = ARM_MODE_ABT, .gdb_index = 40, },
325
326 [29] = { .name = "sp_und", .cookie = 13, .mode = ARM_MODE_UND, .gdb_index = 41, },
327 [30] = { .name = "lr_und", .cookie = 14, .mode = ARM_MODE_UND, .gdb_index = 42, },
328
329 [31] = { .name = "cpsr", .cookie = 16, .mode = ARM_MODE_ANY, .gdb_index = 25, },
330 [32] = { .name = "spsr_fiq", .cookie = 16, .mode = ARM_MODE_FIQ, .gdb_index = 43, },
331 [33] = { .name = "spsr_irq", .cookie = 16, .mode = ARM_MODE_IRQ, .gdb_index = 44, },
332 [34] = { .name = "spsr_svc", .cookie = 16, .mode = ARM_MODE_SVC, .gdb_index = 45, },
333 [35] = { .name = "spsr_abt", .cookie = 16, .mode = ARM_MODE_ABT, .gdb_index = 46, },
334 [36] = { .name = "spsr_und", .cookie = 16, .mode = ARM_MODE_UND, .gdb_index = 47, },
335
336 /* These are only used for GDB target description, banked registers are accessed instead */
337 [37] = { .name = "sp", .cookie = 13, .mode = ARM_MODE_ANY, .gdb_index = 13, },
338 [38] = { .name = "lr", .cookie = 14, .mode = ARM_MODE_ANY, .gdb_index = 14, },
339
340 /* These exist only when the Security Extension (TrustZone) is present */
341 [39] = { .name = "sp_mon", .cookie = 13, .mode = ARM_MODE_MON, .gdb_index = 48, },
342 [40] = { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
343 [41] = { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
344
345 };
346
347 static const struct {
348 unsigned int id;
349 const char *name;
350 uint32_t bits;
351 enum arm_mode mode;
352 enum reg_type type;
353 const char *group;
354 const char *feature;
355 } arm_vfp_v3_regs[] = {
356 { ARM_VFP_V3_D0, "d0", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
357 { ARM_VFP_V3_D1, "d1", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
358 { ARM_VFP_V3_D2, "d2", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
359 { ARM_VFP_V3_D3, "d3", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
360 { ARM_VFP_V3_D4, "d4", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
361 { ARM_VFP_V3_D5, "d5", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
362 { ARM_VFP_V3_D6, "d6", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
363 { ARM_VFP_V3_D7, "d7", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
364 { ARM_VFP_V3_D8, "d8", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
365 { ARM_VFP_V3_D9, "d9", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
366 { ARM_VFP_V3_D10, "d10", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
367 { ARM_VFP_V3_D11, "d11", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
368 { ARM_VFP_V3_D12, "d12", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
369 { ARM_VFP_V3_D13, "d13", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
370 { ARM_VFP_V3_D14, "d14", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
371 { ARM_VFP_V3_D15, "d15", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
372 { ARM_VFP_V3_D16, "d16", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
373 { ARM_VFP_V3_D17, "d17", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
374 { ARM_VFP_V3_D18, "d18", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
375 { ARM_VFP_V3_D19, "d19", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
376 { ARM_VFP_V3_D20, "d20", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
377 { ARM_VFP_V3_D21, "d21", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
378 { ARM_VFP_V3_D22, "d22", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
379 { ARM_VFP_V3_D23, "d23", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
380 { ARM_VFP_V3_D24, "d24", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
381 { ARM_VFP_V3_D25, "d25", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
382 { ARM_VFP_V3_D26, "d26", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
383 { ARM_VFP_V3_D27, "d27", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
384 { ARM_VFP_V3_D28, "d28", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
385 { ARM_VFP_V3_D29, "d29", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
386 { ARM_VFP_V3_D30, "d30", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
387 { ARM_VFP_V3_D31, "d31", 64, ARM_MODE_ANY, REG_TYPE_IEEE_DOUBLE, NULL, "org.gnu.gdb.arm.vfp"},
388 { ARM_VFP_V3_FPSCR, "fpscr", 32, ARM_MODE_ANY, REG_TYPE_INT, "float", "org.gnu.gdb.arm.vfp"},
389 };
390
391 /* map core mode (USR, FIQ, ...) and register number to
392 * indices into the register cache
393 */
394 const int armv4_5_core_reg_map[8][17] = {
395 { /* USR */
396 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
397 },
398 { /* FIQ (8 shadows of USR, vs normal 3) */
399 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
400 },
401 { /* IRQ */
402 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
403 },
404 { /* SVC */
405 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
406 },
407 { /* ABT */
408 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
409 },
410 { /* UND */
411 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
412 },
413 { /* SYS (same registers as USR) */
414 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
415 },
416 { /* MON */
417 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 39, 40, 15, 41,
418 }
419 };
420
421 /**
422 * Configures host-side ARM records to reflect the specified CPSR.
423 * Later, code can use arm_reg_current() to map register numbers
424 * according to how they are exposed by this mode.
425 */
426 void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
427 {
428 enum arm_mode mode = cpsr & 0x1f;
429 int num;
430
431 /* NOTE: this may be called very early, before the register
432 * cache is set up. We can't defend against many errors, in
433 * particular against CPSRs that aren't valid *here* ...
434 */
435 if (arm->cpsr) {
436 buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
437 arm->cpsr->valid = true;
438 arm->cpsr->dirty = false;
439 }
440
441 arm->core_mode = mode;
442
443 /* mode_to_number() warned; set up a somewhat-sane mapping */
444 num = arm_mode_to_number(mode);
445 if (num < 0) {
446 mode = ARM_MODE_USR;
447 num = 0;
448 }
449
450 arm->map = &armv4_5_core_reg_map[num][0];
451 arm->spsr = (mode == ARM_MODE_USR || mode == ARM_MODE_SYS)
452 ? NULL
453 : arm->core_cache->reg_list + arm->map[16];
454
455 /* Older ARMs won't have the J bit */
456 enum arm_state state;
457
458 if (cpsr & (1 << 5)) { /* T */
459 if (cpsr & (1 << 24)) { /* J */
460 LOG_WARNING("ThumbEE -- incomplete support");
461 state = ARM_STATE_THUMB_EE;
462 } else
463 state = ARM_STATE_THUMB;
464 } else {
465 if (cpsr & (1 << 24)) { /* J */
466 LOG_ERROR("Jazelle state handling is BROKEN!");
467 state = ARM_STATE_JAZELLE;
468 } else
469 state = ARM_STATE_ARM;
470 }
471 arm->core_state = state;
472
473 LOG_DEBUG("set CPSR %#8.8x: %s mode, %s state", (unsigned) cpsr,
474 arm_mode_name(mode),
475 arm_state_strings[arm->core_state]);
476 }
477
478 /**
479 * Returns handle to the register currently mapped to a given number.
480 * Someone must have called arm_set_cpsr() before.
481 *
482 * \param arm This core's state and registers are used.
483 * \param regnum From 0..15 corresponding to R0..R14 and PC.
484 * Note that R0..R7 don't require mapping; you may access those
485 * as the first eight entries in the register cache. Likewise
486 * R15 (PC) doesn't need mapping; you may also access it directly.
487 * However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
488 * CPSR (arm->cpsr) is also not mapped.
489 */
490 struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
491 {
492 struct reg *r;
493
494 if (regnum > 16)
495 return NULL;
496
497 if (!arm->map) {
498 LOG_ERROR("Register map is not available yet, the target is not fully initialised");
499 r = arm->core_cache->reg_list + regnum;
500 } else
501 r = arm->core_cache->reg_list + arm->map[regnum];
502
503 /* e.g. invalid CPSR said "secure monitor" mode on a core
504 * that doesn't support it...
505 */
506 if (!r) {
507 LOG_ERROR("Invalid CPSR mode");
508 r = arm->core_cache->reg_list + regnum;
509 }
510
511 return r;
512 }
513
514 static const uint8_t arm_gdb_dummy_fp_value[12];
515
516 static struct reg_feature arm_gdb_dummy_fp_features = {
517 .name = "net.sourceforge.openocd.fake_fpa"
518 };
519
520 /**
521 * Dummy FPA registers are required to support GDB on ARM.
522 * Register packets require eight obsolete FPA register values.
523 * Modern ARM cores use Vector Floating Point (VFP), if they
524 * have any floating point support. VFP is not FPA-compatible.
525 */
526 struct reg arm_gdb_dummy_fp_reg = {
527 .name = "GDB dummy FPA register",
528 .value = (uint8_t *) arm_gdb_dummy_fp_value,
529 .valid = true,
530 .size = 96,
531 .exist = false,
532 .number = 16,
533 .feature = &arm_gdb_dummy_fp_features,
534 .group = "fake_fpa",
535 };
536
537 static const uint8_t arm_gdb_dummy_fps_value[4];
538
539 /**
540 * Dummy FPA status registers are required to support GDB on ARM.
541 * Register packets require an obsolete FPA status register.
542 */
543 struct reg arm_gdb_dummy_fps_reg = {
544 .name = "GDB dummy FPA status register",
545 .value = (uint8_t *) arm_gdb_dummy_fps_value,
546 .valid = true,
547 .size = 32,
548 .exist = false,
549 .number = 24,
550 .feature = &arm_gdb_dummy_fp_features,
551 .group = "fake_fpa",
552 };
553
554 static void arm_gdb_dummy_init(void) __attribute__ ((constructor));
555
556 static void arm_gdb_dummy_init(void)
557 {
558 register_init_dummy(&arm_gdb_dummy_fp_reg);
559 register_init_dummy(&arm_gdb_dummy_fps_reg);
560 }
561
562 static int armv4_5_get_core_reg(struct reg *reg)
563 {
564 int retval;
565 struct arm_reg *reg_arch_info = reg->arch_info;
566 struct target *target = reg_arch_info->target;
567
568 if (target->state != TARGET_HALTED) {
569 LOG_ERROR("Target not halted");
570 return ERROR_TARGET_NOT_HALTED;
571 }
572
573 retval = reg_arch_info->arm->read_core_reg(target, reg,
574 reg_arch_info->num, reg_arch_info->mode);
575 if (retval == ERROR_OK) {
576 reg->valid = true;
577 reg->dirty = false;
578 }
579
580 return retval;
581 }
582
583 static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
584 {
585 struct arm_reg *reg_arch_info = reg->arch_info;
586 struct target *target = reg_arch_info->target;
587 struct arm *armv4_5_target = target_to_arm(target);
588 uint32_t value = buf_get_u32(buf, 0, 32);
589
590 if (target->state != TARGET_HALTED) {
591 LOG_ERROR("Target not halted");
592 return ERROR_TARGET_NOT_HALTED;
593 }
594
595 /* Except for CPSR, the "reg" command exposes a writeback model
596 * for the register cache.
597 */
598 if (reg == armv4_5_target->cpsr) {
599 arm_set_cpsr(armv4_5_target, value);
600
601 /* Older cores need help to be in ARM mode during halt
602 * mode debug, so we clear the J and T bits if we flush.
603 * For newer cores (v6/v7a/v7r) we don't need that, but
604 * it won't hurt since CPSR is always flushed anyway.
605 */
606 if (armv4_5_target->core_mode !=
607 (enum arm_mode)(value & 0x1f)) {
608 LOG_DEBUG("changing ARM core mode to '%s'",
609 arm_mode_name(value & 0x1f));
610 value &= ~((1 << 24) | (1 << 5));
611 uint8_t t[4];
612 buf_set_u32(t, 0, 32, value);
613 armv4_5_target->write_core_reg(target, reg,
614 16, ARM_MODE_ANY, t);
615 }
616 } else {
617 buf_set_u32(reg->value, 0, 32, value);
618 if (reg->size == 64) {
619 value = buf_get_u32(buf + 4, 0, 32);
620 buf_set_u32(reg->value + 4, 0, 32, value);
621 }
622 reg->valid = true;
623 }
624 reg->dirty = true;
625
626 return ERROR_OK;
627 }
628
629 static const struct reg_arch_type arm_reg_type = {
630 .get = armv4_5_get_core_reg,
631 .set = armv4_5_set_core_reg,
632 };
633
634 struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
635 {
636 int num_regs = ARRAY_SIZE(arm_core_regs);
637 int num_core_regs = num_regs;
638 if (arm->arm_vfp_version == ARM_VFP_V3)
639 num_regs += ARRAY_SIZE(arm_vfp_v3_regs);
640
641 struct reg_cache *cache = malloc(sizeof(struct reg_cache));
642 struct reg *reg_list = calloc(num_regs, sizeof(struct reg));
643 struct arm_reg *reg_arch_info = calloc(num_regs, sizeof(struct arm_reg));
644 int i;
645
646 if (!cache || !reg_list || !reg_arch_info) {
647 free(cache);
648 free(reg_list);
649 free(reg_arch_info);
650 return NULL;
651 }
652
653 cache->name = "ARM registers";
654 cache->next = NULL;
655 cache->reg_list = reg_list;
656 cache->num_regs = 0;
657
658 for (i = 0; i < num_core_regs; i++) {
659 /* Skip registers this core doesn't expose */
660 if (arm_core_regs[i].mode == ARM_MODE_MON
661 && arm->core_type != ARM_CORE_TYPE_SEC_EXT)
662 continue;
663
664 /* REVISIT handle Cortex-M, which only shadows R13/SP */
665
666 reg_arch_info[i].num = arm_core_regs[i].cookie;
667 reg_arch_info[i].mode = arm_core_regs[i].mode;
668 reg_arch_info[i].target = target;
669 reg_arch_info[i].arm = arm;
670
671 reg_list[i].name = arm_core_regs[i].name;
672 reg_list[i].number = arm_core_regs[i].gdb_index;
673 reg_list[i].size = 32;
674 reg_list[i].value = reg_arch_info[i].value;
675 reg_list[i].type = &arm_reg_type;
676 reg_list[i].arch_info = &reg_arch_info[i];
677 reg_list[i].exist = true;
678
679 /* This really depends on the calling convention in use */
680 reg_list[i].caller_save = false;
681
682 /* Registers data type, as used by GDB target description */
683 reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
684 switch (arm_core_regs[i].cookie) {
685 case 13:
686 reg_list[i].reg_data_type->type = REG_TYPE_DATA_PTR;
687 break;
688 case 14:
689 case 15:
690 reg_list[i].reg_data_type->type = REG_TYPE_CODE_PTR;
691 break;
692 default:
693 reg_list[i].reg_data_type->type = REG_TYPE_UINT32;
694 break;
695 }
696
697 /* let GDB shows banked registers only in "info all-reg" */
698 reg_list[i].feature = malloc(sizeof(struct reg_feature));
699 if (reg_list[i].number <= 15 || reg_list[i].number == 25) {
700 reg_list[i].feature->name = "org.gnu.gdb.arm.core";
701 reg_list[i].group = "general";
702 } else {
703 reg_list[i].feature->name = "net.sourceforge.openocd.banked";
704 reg_list[i].group = "banked";
705 }
706
707 cache->num_regs++;
708 }
709
710 int j;
711 for (i = num_core_regs, j = 0; i < num_regs; i++, j++) {
712 reg_arch_info[i].num = arm_vfp_v3_regs[j].id;
713 reg_arch_info[i].mode = arm_vfp_v3_regs[j].mode;
714 reg_arch_info[i].target = target;
715 reg_arch_info[i].arm = arm;
716
717 reg_list[i].name = arm_vfp_v3_regs[j].name;
718 reg_list[i].number = arm_vfp_v3_regs[j].id;
719 reg_list[i].size = arm_vfp_v3_regs[j].bits;
720 reg_list[i].value = reg_arch_info[i].value;
721 reg_list[i].type = &arm_reg_type;
722 reg_list[i].arch_info = &reg_arch_info[i];
723 reg_list[i].exist = true;
724
725 reg_list[i].caller_save = false;
726
727 reg_list[i].reg_data_type = malloc(sizeof(struct reg_data_type));
728 reg_list[i].reg_data_type->type = arm_vfp_v3_regs[j].type;
729
730 reg_list[i].feature = malloc(sizeof(struct reg_feature));
731 reg_list[i].feature->name = arm_vfp_v3_regs[j].feature;
732
733 reg_list[i].group = arm_vfp_v3_regs[j].group;
734
735 cache->num_regs++;
736 }
737
738 arm->pc = reg_list + 15;
739 arm->cpsr = reg_list + ARMV4_5_CPSR;
740 arm->core_cache = cache;
741
742 return cache;
743 }
744
745 int arm_arch_state(struct target *target)
746 {
747 struct arm *arm = target_to_arm(target);
748
749 if (arm->common_magic != ARM_COMMON_MAGIC) {
750 LOG_ERROR("BUG: called for a non-ARM target");
751 return ERROR_FAIL;
752 }
753
754 /* avoid filling log waiting for fileio reply */
755 if (target->semihosting && target->semihosting->hit_fileio)
756 return ERROR_OK;
757
758 LOG_USER("target halted in %s state due to %s, current mode: %s\n"
759 "cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s%s",
760 arm_state_strings[arm->core_state],
761 debug_reason_name(target),
762 arm_mode_name(arm->core_mode),
763 buf_get_u32(arm->cpsr->value, 0, 32),
764 buf_get_u32(arm->pc->value, 0, 32),
765 (target->semihosting && target->semihosting->is_active) ? ", semihosting" : "",
766 (target->semihosting && target->semihosting->is_fileio) ? " fileio" : "");
767
768 return ERROR_OK;
769 }
770
771 COMMAND_HANDLER(handle_armv4_5_reg_command)
772 {
773 struct target *target = get_current_target(CMD_CTX);
774 struct arm *arm = target_to_arm(target);
775 struct reg *regs;
776
777 if (!is_arm(arm)) {
778 command_print(CMD, "current target isn't an ARM");
779 return ERROR_FAIL;
780 }
781
782 if (target->state != TARGET_HALTED) {
783 command_print(CMD, "error: target must be halted for register accesses");
784 return ERROR_FAIL;
785 }
786
787 if (arm->core_type != ARM_CORE_TYPE_STD) {
788 command_print(CMD,
789 "Microcontroller Profile not supported - use standard reg cmd");
790 return ERROR_OK;
791 }
792
793 if (!is_arm_mode(arm->core_mode)) {
794 LOG_ERROR("not a valid arm core mode - communication failure?");
795 return ERROR_FAIL;
796 }
797
798 if (!arm->full_context) {
799 command_print(CMD, "error: target doesn't support %s",
800 CMD_NAME);
801 return ERROR_FAIL;
802 }
803
804 regs = arm->core_cache->reg_list;
805
806 for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
807 const char *name;
808 char *sep = "\n";
809 char *shadow = "";
810
811 /* label this bank of registers (or shadows) */
812 switch (arm_mode_data[mode].psr) {
813 case ARM_MODE_SYS:
814 continue;
815 case ARM_MODE_USR:
816 name = "System and User";
817 sep = "";
818 break;
819 case ARM_MODE_MON:
820 if (arm->core_type != ARM_CORE_TYPE_SEC_EXT)
821 continue;
822 /* FALLTHROUGH */
823 default:
824 name = arm_mode_data[mode].name;
825 shadow = "shadow ";
826 break;
827 }
828 command_print(CMD, "%s%s mode %sregisters",
829 sep, name, shadow);
830
831 /* display N rows of up to 4 registers each */
832 for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
833 char output[80];
834 int output_len = 0;
835
836 for (unsigned j = 0; j < 4; j++, i++) {
837 uint32_t value;
838 struct reg *reg = regs;
839
840 if (i >= arm_mode_data[mode].n_indices)
841 break;
842
843 reg += arm_mode_data[mode].indices[i];
844
845 /* REVISIT be smarter about faults... */
846 if (!reg->valid)
847 arm->full_context(target);
848
849 value = buf_get_u32(reg->value, 0, 32);
850 output_len += snprintf(output + output_len,
851 sizeof(output) - output_len,
852 "%8s: %8.8" PRIx32 " ",
853 reg->name, value);
854 }
855 command_print(CMD, "%s", output);
856 }
857 }
858
859 return ERROR_OK;
860 }
861
862 COMMAND_HANDLER(handle_armv4_5_core_state_command)
863 {
864 struct target *target = get_current_target(CMD_CTX);
865 struct arm *arm = target_to_arm(target);
866
867 if (!is_arm(arm)) {
868 command_print(CMD, "current target isn't an ARM");
869 return ERROR_FAIL;
870 }
871
872 if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
873 /* armv7m not supported */
874 command_print(CMD, "Unsupported Command");
875 return ERROR_OK;
876 }
877
878 if (CMD_ARGC > 0) {
879 if (strcmp(CMD_ARGV[0], "arm") == 0)
880 arm->core_state = ARM_STATE_ARM;
881 if (strcmp(CMD_ARGV[0], "thumb") == 0)
882 arm->core_state = ARM_STATE_THUMB;
883 }
884
885 command_print(CMD, "core state: %s", arm_state_strings[arm->core_state]);
886
887 return ERROR_OK;
888 }
889
890 COMMAND_HANDLER(handle_arm_disassemble_command)
891 {
892 int retval = ERROR_OK;
893 struct target *target = get_current_target(CMD_CTX);
894
895 if (target == NULL) {
896 LOG_ERROR("No target selected");
897 return ERROR_FAIL;
898 }
899
900 struct arm *arm = target_to_arm(target);
901 target_addr_t address;
902 int count = 1;
903 int thumb = 0;
904
905 if (!is_arm(arm)) {
906 command_print(CMD, "current target isn't an ARM");
907 return ERROR_FAIL;
908 }
909
910 if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
911 /* armv7m is always thumb mode */
912 thumb = 1;
913 }
914
915 switch (CMD_ARGC) {
916 case 3:
917 if (strcmp(CMD_ARGV[2], "thumb") != 0)
918 goto usage;
919 thumb = 1;
920 /* FALL THROUGH */
921 case 2:
922 COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
923 /* FALL THROUGH */
924 case 1:
925 COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
926 if (address & 0x01) {
927 if (!thumb) {
928 command_print(CMD, "Disassemble as Thumb");
929 thumb = 1;
930 }
931 address &= ~1;
932 }
933 break;
934 default:
935 usage:
936 count = 0;
937 retval = ERROR_COMMAND_SYNTAX_ERROR;
938 }
939
940 while (count-- > 0) {
941 struct arm_instruction cur_instruction;
942
943 if (thumb) {
944 /* Always use Thumb2 disassembly for best handling
945 * of 32-bit BL/BLX, and to work with newer cores
946 * (some ARMv6, all ARMv7) that use Thumb2.
947 */
948 retval = thumb2_opcode(target, address,
949 &cur_instruction);
950 if (retval != ERROR_OK)
951 break;
952 } else {
953 uint32_t opcode;
954
955 retval = target_read_u32(target, address, &opcode);
956 if (retval != ERROR_OK)
957 break;
958 retval = arm_evaluate_opcode(opcode, address,
959 &cur_instruction) != ERROR_OK;
960 if (retval != ERROR_OK)
961 break;
962 }
963 command_print(CMD, "%s", cur_instruction.text);
964 address += cur_instruction.instruction_size;
965 }
966
967 return retval;
968 }
969
970 static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
971 {
972 struct command_context *context;
973 struct target *target;
974 struct arm *arm;
975 int retval;
976
977 context = current_command_context(interp);
978 assert(context != NULL);
979
980 target = get_current_target(context);
981 if (target == NULL) {
982 LOG_ERROR("%s: no current target", __func__);
983 return JIM_ERR;
984 }
985 if (!target_was_examined(target)) {
986 LOG_ERROR("%s: not yet examined", target_name(target));
987 return JIM_ERR;
988 }
989 arm = target_to_arm(target);
990 if (!is_arm(arm)) {
991 LOG_ERROR("%s: not an ARM", target_name(target));
992 return JIM_ERR;
993 }
994
995 if ((argc < 6) || (argc > 7)) {
996 /* FIXME use the command name to verify # params... */
997 LOG_ERROR("%s: wrong number of arguments", __func__);
998 return JIM_ERR;
999 }
1000
1001 int cpnum;
1002 uint32_t op1;
1003 uint32_t op2;
1004 uint32_t CRn;
1005 uint32_t CRm;
1006 uint32_t value;
1007 long l;
1008
1009 /* NOTE: parameter sequence matches ARM instruction set usage:
1010 * MCR pNUM, op1, rX, CRn, CRm, op2 ; write CP from rX
1011 * MRC pNUM, op1, rX, CRn, CRm, op2 ; read CP into rX
1012 * The "rX" is necessarily omitted; it uses Tcl mechanisms.
1013 */
1014 retval = Jim_GetLong(interp, argv[1], &l);
1015 if (retval != JIM_OK)
1016 return retval;
1017 if (l & ~0xf) {
1018 LOG_ERROR("%s: %s %d out of range", __func__,
1019 "coprocessor", (int) l);
1020 return JIM_ERR;
1021 }
1022 cpnum = l;
1023
1024 retval = Jim_GetLong(interp, argv[2], &l);
1025 if (retval != JIM_OK)
1026 return retval;
1027 if (l & ~0x7) {
1028 LOG_ERROR("%s: %s %d out of range", __func__,
1029 "op1", (int) l);
1030 return JIM_ERR;
1031 }
1032 op1 = l;
1033
1034 retval = Jim_GetLong(interp, argv[3], &l);
1035 if (retval != JIM_OK)
1036 return retval;
1037 if (l & ~0xf) {
1038 LOG_ERROR("%s: %s %d out of range", __func__,
1039 "CRn", (int) l);
1040 return JIM_ERR;
1041 }
1042 CRn = l;
1043
1044 retval = Jim_GetLong(interp, argv[4], &l);
1045 if (retval != JIM_OK)
1046 return retval;
1047 if (l & ~0xf) {
1048 LOG_ERROR("%s: %s %d out of range", __func__,
1049 "CRm", (int) l);
1050 return JIM_ERR;
1051 }
1052 CRm = l;
1053
1054 retval = Jim_GetLong(interp, argv[5], &l);
1055 if (retval != JIM_OK)
1056 return retval;
1057 if (l & ~0x7) {
1058 LOG_ERROR("%s: %s %d out of range", __func__,
1059 "op2", (int) l);
1060 return JIM_ERR;
1061 }
1062 op2 = l;
1063
1064 value = 0;
1065
1066 /* FIXME don't assume "mrc" vs "mcr" from the number of params;
1067 * that could easily be a typo! Check both...
1068 *
1069 * FIXME change the call syntax here ... simplest to just pass
1070 * the MRC() or MCR() instruction to be executed. That will also
1071 * let us support the "mrc2" and "mcr2" opcodes (toggling one bit)
1072 * if that's ever needed.
1073 */
1074 if (argc == 7) {
1075 retval = Jim_GetLong(interp, argv[6], &l);
1076 if (retval != JIM_OK)
1077 return retval;
1078 value = l;
1079
1080 /* NOTE: parameters reordered! */
1081 /* ARMV4_5_MCR(cpnum, op1, 0, CRn, CRm, op2) */
1082 retval = arm->mcr(target, cpnum, op1, op2, CRn, CRm, value);
1083 if (retval != ERROR_OK)
1084 return JIM_ERR;
1085 } else {
1086 /* NOTE: parameters reordered! */
1087 /* ARMV4_5_MRC(cpnum, op1, 0, CRn, CRm, op2) */
1088 retval = arm->mrc(target, cpnum, op1, op2, CRn, CRm, &value);
1089 if (retval != ERROR_OK)
1090 return JIM_ERR;
1091
1092 Jim_SetResult(interp, Jim_NewIntObj(interp, value));
1093 }
1094
1095 return JIM_OK;
1096 }
1097
1098 extern const struct command_registration semihosting_common_handlers[];
1099
1100 static const struct command_registration arm_exec_command_handlers[] = {
1101 {
1102 .name = "reg",
1103 .handler = handle_armv4_5_reg_command,
1104 .mode = COMMAND_EXEC,
1105 .help = "display ARM core registers",
1106 .usage = "",
1107 },
1108 {
1109 .name = "core_state",
1110 .handler = handle_armv4_5_core_state_command,
1111 .mode = COMMAND_EXEC,
1112 .usage = "['arm'|'thumb']",
1113 .help = "display/change ARM core state",
1114 },
1115 {
1116 .name = "disassemble",
1117 .handler = handle_arm_disassemble_command,
1118 .mode = COMMAND_EXEC,
1119 .usage = "address [count ['thumb']]",
1120 .help = "disassemble instructions ",
1121 },
1122 {
1123 .name = "mcr",
1124 .mode = COMMAND_EXEC,
1125 .jim_handler = &jim_mcrmrc,
1126 .help = "write coprocessor register",
1127 .usage = "cpnum op1 CRn CRm op2 value",
1128 },
1129 {
1130 .name = "mrc",
1131 .mode = COMMAND_EXEC,
1132 .jim_handler = &jim_mcrmrc,
1133 .help = "read coprocessor register",
1134 .usage = "cpnum op1 CRn CRm op2",
1135 },
1136 {
1137 .chain = semihosting_common_handlers,
1138 },
1139 COMMAND_REGISTRATION_DONE
1140 };
1141 const struct command_registration arm_command_handlers[] = {
1142 {
1143 .name = "arm",
1144 .mode = COMMAND_ANY,
1145 .help = "ARM command group",
1146 .usage = "",
1147 .chain = arm_exec_command_handlers,
1148 },
1149 COMMAND_REGISTRATION_DONE
1150 };
1151
1152 /*
1153 * gdb for arm targets (e.g. arm-none-eabi-gdb) supports several variants
1154 * of arm architecture. You can list them using the autocompletion of gdb
1155 * command prompt by typing "set architecture " and then press TAB key.
1156 * The default, selected automatically, is "arm".
1157 * Let's use the default value, here, to make gdb-multiarch behave in the
1158 * same way as a gdb for arm. This can be changed later on. User can still
1159 * set the specific architecture variant with the gdb command.
1160 */
1161 const char *arm_get_gdb_arch(struct target *target)
1162 {
1163 return "arm";
1164 }
1165
1166 int arm_get_gdb_reg_list(struct target *target,
1167 struct reg **reg_list[], int *reg_list_size,
1168 enum target_register_class reg_class)
1169 {
1170 struct arm *arm = target_to_arm(target);
1171 unsigned int i;
1172
1173 if (!is_arm_mode(arm->core_mode)) {
1174 LOG_ERROR("not a valid arm core mode - communication failure?");
1175 return ERROR_FAIL;
1176 }
1177
1178 switch (reg_class) {
1179 case REG_CLASS_GENERAL:
1180 *reg_list_size = 26;
1181 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1182
1183 for (i = 0; i < 16; i++)
1184 (*reg_list)[i] = arm_reg_current(arm, i);
1185
1186 /* For GDB compatibility, take FPA registers size into account and zero-fill it*/
1187 for (i = 16; i < 24; i++)
1188 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1189 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1190
1191 (*reg_list)[25] = arm->cpsr;
1192
1193 return ERROR_OK;
1194 break;
1195
1196 case REG_CLASS_ALL:
1197 *reg_list_size = (arm->core_type != ARM_CORE_TYPE_SEC_EXT ? 48 : 51);
1198 unsigned int list_size_core = *reg_list_size;
1199 if (arm->arm_vfp_version == ARM_VFP_V3)
1200 *reg_list_size += 33;
1201
1202 *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
1203
1204 for (i = 0; i < 16; i++)
1205 (*reg_list)[i] = arm_reg_current(arm, i);
1206
1207 for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
1208 int reg_index = arm->core_cache->reg_list[i].number;
1209 if (!(arm_core_regs[i].mode == ARM_MODE_MON
1210 && arm->core_type != ARM_CORE_TYPE_SEC_EXT))
1211 (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
1212 }
1213
1214 /* When we supply the target description, there is no need for fake FPA */
1215 for (i = 16; i < 24; i++) {
1216 (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
1217 (*reg_list)[i]->size = 0;
1218 }
1219 (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
1220 (*reg_list)[24]->size = 0;
1221
1222 if (arm->arm_vfp_version == ARM_VFP_V3) {
1223 unsigned int num_core_regs = ARRAY_SIZE(arm_core_regs);
1224 for (i = 0; i < 33; i++)
1225 (*reg_list)[list_size_core + i] = &(arm->core_cache->reg_list[num_core_regs + i]);
1226 }
1227
1228 return ERROR_OK;
1229 break;
1230
1231 default:
1232 LOG_ERROR("not a valid register class type in query.");
1233 return ERROR_FAIL;
1234 break;
1235 }
1236 }
1237
1238 /* wait for execution to complete and check exit point */
1239 static int armv4_5_run_algorithm_completion(struct target *target,
1240 uint32_t exit_point,
1241 int timeout_ms,
1242 void *arch_info)
1243 {
1244 int retval;
1245 struct arm *arm = target_to_arm(target);
1246
1247 retval = target_wait_state(target, TARGET_HALTED, timeout_ms);
1248 if (retval != ERROR_OK)
1249 return retval;
1250 if (target->state != TARGET_HALTED) {
1251 retval = target_halt(target);
1252 if (retval != ERROR_OK)
1253 return retval;
1254 retval = target_wait_state(target, TARGET_HALTED, 500);
1255 if (retval != ERROR_OK)
1256 return retval;
1257 return ERROR_TARGET_TIMEOUT;
1258 }
1259
1260 /* fast exit: ARMv5+ code can use BKPT */
1261 if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
1262 LOG_WARNING(
1263 "target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
1264 buf_get_u32(arm->pc->value, 0, 32));
1265 return ERROR_TARGET_TIMEOUT;
1266 }
1267
1268 return ERROR_OK;
1269 }
1270
1271 int armv4_5_run_algorithm_inner(struct target *target,
1272 int num_mem_params, struct mem_param *mem_params,
1273 int num_reg_params, struct reg_param *reg_params,
1274 uint32_t entry_point, uint32_t exit_point,
1275 int timeout_ms, void *arch_info,
1276 int (*run_it)(struct target *target, uint32_t exit_point,
1277 int timeout_ms, void *arch_info))
1278 {
1279 struct arm *arm = target_to_arm(target);
1280 struct arm_algorithm *arm_algorithm_info = arch_info;
1281 enum arm_state core_state = arm->core_state;
1282 uint32_t context[17];
1283 uint32_t cpsr;
1284 int exit_breakpoint_size = 0;
1285 int i;
1286 int retval = ERROR_OK;
1287
1288 LOG_DEBUG("Running algorithm");
1289
1290 if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
1291 LOG_ERROR("current target isn't an ARMV4/5 target");
1292 return ERROR_TARGET_INVALID;
1293 }
1294
1295 if (target->state != TARGET_HALTED) {
1296 LOG_WARNING("target not halted");
1297 return ERROR_TARGET_NOT_HALTED;
1298 }
1299
1300 if (!is_arm_mode(arm->core_mode)) {
1301 LOG_ERROR("not a valid arm core mode - communication failure?");
1302 return ERROR_FAIL;
1303 }
1304
1305 /* armv5 and later can terminate with BKPT instruction; less overhead */
1306 if (!exit_point && arm->is_armv4) {
1307 LOG_ERROR("ARMv4 target needs HW breakpoint location");
1308 return ERROR_FAIL;
1309 }
1310
1311 /* save r0..pc, cpsr-or-spsr, and then cpsr-for-sure;
1312 * they'll be restored later.
1313 */
1314 for (i = 0; i <= 16; i++) {
1315 struct reg *r;
1316
1317 r = &ARMV4_5_CORE_REG_MODE(arm->core_cache,
1318 arm_algorithm_info->core_mode, i);
1319 if (!r->valid)
1320 arm->read_core_reg(target, r, i,
1321 arm_algorithm_info->core_mode);
1322 context[i] = buf_get_u32(r->value, 0, 32);
1323 }
1324 cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
1325
1326 for (i = 0; i < num_mem_params; i++) {
1327 if (mem_params[i].direction == PARAM_IN)
1328 continue;
1329 retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
1330 mem_params[i].value);
1331 if (retval != ERROR_OK)
1332 return retval;
1333 }
1334
1335 for (i = 0; i < num_reg_params; i++) {
1336 if (reg_params[i].direction == PARAM_IN)
1337 continue;
1338
1339 struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, 0);
1340 if (!reg) {
1341 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1342 return ERROR_COMMAND_SYNTAX_ERROR;
1343 }
1344
1345 if (reg->size != reg_params[i].size) {
1346 LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
1347 reg_params[i].reg_name);
1348 return ERROR_COMMAND_SYNTAX_ERROR;
1349 }
1350
1351 retval = armv4_5_set_core_reg(reg, reg_params[i].value);
1352 if (retval != ERROR_OK)
1353 return retval;
1354 }
1355
1356 arm->core_state = arm_algorithm_info->core_state;
1357 if (arm->core_state == ARM_STATE_ARM)
1358 exit_breakpoint_size = 4;
1359 else if (arm->core_state == ARM_STATE_THUMB)
1360 exit_breakpoint_size = 2;
1361 else {
1362 LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
1363 return ERROR_COMMAND_SYNTAX_ERROR;
1364 }
1365
1366 if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
1367 LOG_DEBUG("setting core_mode: 0x%2.2x",
1368 arm_algorithm_info->core_mode);
1369 buf_set_u32(arm->cpsr->value, 0, 5,
1370 arm_algorithm_info->core_mode);
1371 arm->cpsr->dirty = true;
1372 arm->cpsr->valid = true;
1373 }
1374
1375 /* terminate using a hardware or (ARMv5+) software breakpoint */
1376 if (exit_point) {
1377 retval = breakpoint_add(target, exit_point,
1378 exit_breakpoint_size, BKPT_HARD);
1379 if (retval != ERROR_OK) {
1380 LOG_ERROR("can't add HW breakpoint to terminate algorithm");
1381 return ERROR_TARGET_FAILURE;
1382 }
1383 }
1384
1385 retval = target_resume(target, 0, entry_point, 1, 1);
1386 if (retval != ERROR_OK)
1387 return retval;
1388 retval = run_it(target, exit_point, timeout_ms, arch_info);
1389
1390 if (exit_point)
1391 breakpoint_remove(target, exit_point);
1392
1393 if (retval != ERROR_OK)
1394 return retval;
1395
1396 for (i = 0; i < num_mem_params; i++) {
1397 if (mem_params[i].direction != PARAM_OUT) {
1398 int retvaltemp = target_read_buffer(target, mem_params[i].address,
1399 mem_params[i].size,
1400 mem_params[i].value);
1401 if (retvaltemp != ERROR_OK)
1402 retval = retvaltemp;
1403 }
1404 }
1405
1406 for (i = 0; i < num_reg_params; i++) {
1407 if (reg_params[i].direction != PARAM_OUT) {
1408
1409 struct reg *reg = register_get_by_name(arm->core_cache,
1410 reg_params[i].reg_name,
1411 0);
1412 if (!reg) {
1413 LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
1414 retval = ERROR_COMMAND_SYNTAX_ERROR;
1415 continue;
1416 }
1417
1418 if (reg->size != reg_params[i].size) {
1419 LOG_ERROR(
1420 "BUG: register '%s' size doesn't match reg_params[i].size",
1421 reg_params[i].reg_name);
1422 retval = ERROR_COMMAND_SYNTAX_ERROR;
1423 continue;
1424 }
1425
1426 buf_set_u32(reg_params[i].value, 0, 32, buf_get_u32(reg->value, 0, 32));
1427 }
1428 }
1429
1430 /* restore everything we saved before (17 or 18 registers) */
1431 for (i = 0; i <= 16; i++) {
1432 uint32_t regvalue;
1433 regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1434 arm_algorithm_info->core_mode, i).value, 0, 32);
1435 if (regvalue != context[i]) {
1436 LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
1437 ARMV4_5_CORE_REG_MODE(arm->core_cache,
1438 arm_algorithm_info->core_mode, i).name, context[i]);
1439 buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
1440 arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
1441 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1442 i).valid = true;
1443 ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
1444 i).dirty = true;
1445 }
1446 }
1447
1448 arm_set_cpsr(arm, cpsr);
1449 arm->cpsr->dirty = true;
1450
1451 arm->core_state = core_state;
1452
1453 return retval;
1454 }
1455
1456 int armv4_5_run_algorithm(struct target *target,
1457 int num_mem_params,
1458 struct mem_param *mem_params,
1459 int num_reg_params,
1460 struct reg_param *reg_params,
1461 target_addr_t entry_point,
1462 target_addr_t exit_point,
1463 int timeout_ms,
1464 void *arch_info)
1465 {
1466 return armv4_5_run_algorithm_inner(target,
1467 num_mem_params,
1468 mem_params,
1469 num_reg_params,
1470 reg_params,
1471 (uint32_t)entry_point,
1472 (uint32_t)exit_point,
1473 timeout_ms,
1474 arch_info,
1475 armv4_5_run_algorithm_completion);
1476 }
1477
1478 /**
1479 * Runs ARM code in the target to calculate a CRC32 checksum.
1480 *
1481 */
1482 int arm_checksum_memory(struct target *target,
1483 target_addr_t address, uint32_t count, uint32_t *checksum)
1484 {
1485 struct working_area *crc_algorithm;
1486 struct arm_algorithm arm_algo;
1487 struct arm *arm = target_to_arm(target);
1488 struct reg_param reg_params[2];
1489 int retval;
1490 uint32_t i;
1491 uint32_t exit_var = 0;
1492
1493 static const uint8_t arm_crc_code_le[] = {
1494 #include "../../contrib/loaders/checksum/armv4_5_crc.inc"
1495 };
1496
1497 assert(sizeof(arm_crc_code_le) % 4 == 0);
1498
1499 retval = target_alloc_working_area(target,
1500 sizeof(arm_crc_code_le), &crc_algorithm);
1501 if (retval != ERROR_OK)
1502 return retval;
1503
1504 /* convert code into a buffer in target endianness */
1505 for (i = 0; i < ARRAY_SIZE(arm_crc_code_le) / 4; i++) {
1506 retval = target_write_u32(target,
1507 crc_algorithm->address + i * sizeof(uint32_t),
1508 le_to_h_u32(&arm_crc_code_le[i * 4]));
1509 if (retval != ERROR_OK)
1510 goto cleanup;
1511 }
1512
1513 arm_algo.common_magic = ARM_COMMON_MAGIC;
1514 arm_algo.core_mode = ARM_MODE_SVC;
1515 arm_algo.core_state = ARM_STATE_ARM;
1516
1517 init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);
1518 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1519
1520 buf_set_u32(reg_params[0].value, 0, 32, address);
1521 buf_set_u32(reg_params[1].value, 0, 32, count);
1522
1523 /* 20 second timeout/megabyte */
1524 int timeout = 20000 * (1 + (count / (1024 * 1024)));
1525
1526 /* armv4 must exit using a hardware breakpoint */
1527 if (arm->is_armv4)
1528 exit_var = crc_algorithm->address + sizeof(arm_crc_code_le) - 8;
1529
1530 retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
1531 crc_algorithm->address,
1532 exit_var,
1533 timeout, &arm_algo);
1534
1535 if (retval == ERROR_OK)
1536 *checksum = buf_get_u32(reg_params[0].value, 0, 32);
1537 else
1538 LOG_ERROR("error executing ARM crc algorithm");
1539
1540 destroy_reg_param(&reg_params[0]);
1541 destroy_reg_param(&reg_params[1]);
1542
1543 cleanup:
1544 target_free_working_area(target, crc_algorithm);
1545
1546 return retval;
1547 }
1548
1549 /**
1550 * Runs ARM code in the target to check whether a memory block holds
1551 * all ones. NOR flash which has been erased, and thus may be written,
1552 * holds all ones.
1553 *
1554 */
1555 int arm_blank_check_memory(struct target *target,
1556 struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value)
1557 {
1558 struct working_area *check_algorithm;
1559 struct reg_param reg_params[3];
1560 struct arm_algorithm arm_algo;
1561 struct arm *arm = target_to_arm(target);
1562 int retval;
1563 uint32_t i;
1564 uint32_t exit_var = 0;
1565
1566 static const uint8_t check_code_le[] = {
1567 #include "../../contrib/loaders/erase_check/armv4_5_erase_check.inc"
1568 };
1569
1570 assert(sizeof(check_code_le) % 4 == 0);
1571
1572 if (erased_value != 0xff) {
1573 LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
1574 erased_value);
1575 return ERROR_FAIL;
1576 }
1577
1578 /* make sure we have a working area */
1579 retval = target_alloc_working_area(target,
1580 sizeof(check_code_le), &check_algorithm);
1581 if (retval != ERROR_OK)
1582 return retval;
1583
1584 /* convert code into a buffer in target endianness */
1585 for (i = 0; i < ARRAY_SIZE(check_code_le) / 4; i++) {
1586 retval = target_write_u32(target,
1587 check_algorithm->address
1588 + i * sizeof(uint32_t),
1589 le_to_h_u32(&check_code_le[i * 4]));
1590 if (retval != ERROR_OK)
1591 goto cleanup;
1592 }
1593
1594 arm_algo.common_magic = ARM_COMMON_MAGIC;
1595 arm_algo.core_mode = ARM_MODE_SVC;
1596 arm_algo.core_state = ARM_STATE_ARM;
1597
1598 init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
1599 buf_set_u32(reg_params[0].value, 0, 32, blocks[0].address);
1600
1601 init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
1602 buf_set_u32(reg_params[1].value, 0, 32, blocks[0].size);
1603
1604 init_reg_param(&reg_params[2], "r2", 32, PARAM_IN_OUT);
1605 buf_set_u32(reg_params[2].value, 0, 32, erased_value);
1606
1607 /* armv4 must exit using a hardware breakpoint */
1608 if (arm->is_armv4)
1609 exit_var = check_algorithm->address + sizeof(check_code_le) - 4;
1610
1611 retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
1612 check_algorithm->address,
1613 exit_var,
1614 10000, &arm_algo);
1615
1616 if (retval == ERROR_OK)
1617 blocks[0].result = buf_get_u32(reg_params[2].value, 0, 32);
1618
1619 destroy_reg_param(&reg_params[0]);
1620 destroy_reg_param(&reg_params[1]);
1621 destroy_reg_param(&reg_params[2]);
1622
1623 cleanup:
1624 target_free_working_area(target, check_algorithm);
1625
1626 if (retval != ERROR_OK)
1627 return retval;
1628
1629 return 1; /* only one block has been checked */
1630 }
1631
1632 static int arm_full_context(struct target *target)
1633 {
1634 struct arm *arm = target_to_arm(target);
1635 unsigned num_regs = arm->core_cache->num_regs;
1636 struct reg *reg = arm->core_cache->reg_list;
1637 int retval = ERROR_OK;
1638
1639 for (; num_regs && retval == ERROR_OK; num_regs--, reg++) {
1640 if (reg->valid)
1641 continue;
1642 retval = armv4_5_get_core_reg(reg);
1643 }
1644 return retval;
1645 }
1646
1647 static int arm_default_mrc(struct target *target, int cpnum,
1648 uint32_t op1, uint32_t op2,
1649 uint32_t CRn, uint32_t CRm,
1650 uint32_t *value)
1651 {
1652 LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
1653 return ERROR_FAIL;
1654 }
1655
1656 static int arm_default_mcr(struct target *target, int cpnum,
1657 uint32_t op1, uint32_t op2,
1658 uint32_t CRn, uint32_t CRm,
1659 uint32_t value)
1660 {
1661 LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
1662 return ERROR_FAIL;
1663 }
1664
1665 int arm_init_arch_info(struct target *target, struct arm *arm)
1666 {
1667 target->arch_info = arm;
1668 arm->target = target;
1669
1670 arm->common_magic = ARM_COMMON_MAGIC;
1671
1672 /* core_type may be overridden by subtype logic */
1673 if (arm->core_type != ARM_CORE_TYPE_M_PROFILE) {
1674 arm->core_type = ARM_CORE_TYPE_STD;
1675 arm_set_cpsr(arm, ARM_MODE_USR);
1676 }
1677
1678 /* default full_context() has no core-specific optimizations */
1679 if (!arm->full_context && arm->read_core_reg)
1680 arm->full_context = arm_full_context;
1681
1682 if (!arm->mrc)
1683 arm->mrc = arm_default_mrc;
1684 if (!arm->mcr)
1685 arm->mcr = arm_default_mcr;
1686
1687 return ERROR_OK;
1688 }
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